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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
*
*/
#ifndef __CLK_MICROCHIP_PIC32
#define __CLK_MICROCHIP_PIC32
/* clock output indices */
#define BASECLK 0
#define PLLCLK 1
#define MPLL 2
#define SYSCLK 3
#define PB1CLK 4
#define PB2CLK 5
#define PB3CLK 6
#define PB4CLK 7
#define PB5CLK 8
#define PB6CLK 9
#define PB7CLK 10
#define REF1CLK 11
#define REF2CLK 12
#define REF3CLK 13
#define REF4CLK 14
#define REF5CLK 15
#endif /* __CLK_MICROCHIP_PIC32 */
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