diff options
| author | Tom Rini <trini@konsulko.com> | 2016-11-29 19:42:48 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-11-29 19:42:48 -0500 |
| commit | 6b29a395b62965eef6b5065d3a526a8588a92038 (patch) | |
| tree | d9404d155aa96dd58ff9d02cdb2a30e7136405da | |
| parent | dbd5df89d65172f94dec78af809f1e50dbd61fe6 (diff) | |
| parent | e8a390f0189c5868f2fa305004821bcfcd71d32c (diff) | |
Merge git://git.denx.de/u-boot-mpc85xx
306 files changed, 1071 insertions, 1104 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 9bcbda006d..3ee7d2f0c5 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -10,25 +10,37 @@ choice config TARGET_SBC8548 bool "Support sbc8548" + select ARCH_MPC8548 config TARGET_SOCRATES bool "Support socrates" + select ARCH_MPC8544 + +config TARGET_B4420QDS + bool "Support B4420QDS" + select ARCH_B4420 + select SUPPORT_SPL + select PHYS_64BIT config TARGET_B4860QDS bool "Support B4860QDS" + select ARCH_B4860 select SUPPORT_SPL select PHYS_64BIT config TARGET_BSC9131RDB bool "Support BSC9131RDB" + select ARCH_BSC9131 select SUPPORT_SPL config TARGET_BSC9132QDS bool "Support BSC9132QDS" + select ARCH_BSC9132 select SUPPORT_SPL config TARGET_C29XPCIE bool "Support C29XPCIE" + select ARCH_C29X select SUPPORT_SPL select SUPPORT_TPL select PHYS_64BIT @@ -36,135 +48,266 @@ config TARGET_C29XPCIE config TARGET_P3041DS bool "Support P3041DS" select PHYS_64BIT + select ARCH_P3041 config TARGET_P4080DS bool "Support P4080DS" select PHYS_64BIT + select ARCH_P4080 config TARGET_P5020DS bool "Support P5020DS" select PHYS_64BIT + select ARCH_P5020 config TARGET_P5040DS bool "Support P5040DS" select PHYS_64BIT + select ARCH_P5040 config TARGET_MPC8536DS bool "Support MPC8536DS" + select ARCH_MPC8536 config TARGET_MPC8540ADS bool "Support MPC8540ADS" + select ARCH_MPC8540 config TARGET_MPC8541CDS bool "Support MPC8541CDS" + select ARCH_MPC8541 config TARGET_MPC8544DS bool "Support MPC8544DS" + select ARCH_MPC8544 config TARGET_MPC8548CDS bool "Support MPC8548CDS" + select ARCH_MPC8548 config TARGET_MPC8555CDS bool "Support MPC8555CDS" + select ARCH_MPC8555 config TARGET_MPC8560ADS bool "Support MPC8560ADS" + select ARCH_MPC8560 config TARGET_MPC8568MDS bool "Support MPC8568MDS" + select ARCH_MPC8568 config TARGET_MPC8569MDS bool "Support MPC8569MDS" + select ARCH_MPC8569 config TARGET_MPC8572DS bool "Support MPC8572DS" + select ARCH_MPC8572 + +config TARGET_P1010RDB_PA + bool "Support P1010RDB_PA" + select ARCH_P1010 + select SUPPORT_SPL + select SUPPORT_TPL -config TARGET_P1010RDB - bool "Support P1010RDB" +config TARGET_P1010RDB_PB + bool "Support P1010RDB_PB" + select ARCH_P1010 select SUPPORT_SPL select SUPPORT_TPL config TARGET_P1022DS bool "Support P1022DS" + select ARCH_P1022 select SUPPORT_SPL select SUPPORT_TPL config TARGET_P1023RDB bool "Support P1023RDB" + select ARCH_P1023 + +config TARGET_P1020MBG + bool "Support P1020MBG-PC" + select SUPPORT_SPL + select SUPPORT_TPL + select ARCH_P1020 + +config TARGET_P1020RDB_PC + bool "Support P1020RDB-PC" + select SUPPORT_SPL + select SUPPORT_TPL + select ARCH_P1020 -config TARGET_P1_P2_RDB_PC - bool "Support p1_p2_rdb_pc" +config TARGET_P1020RDB_PD + bool "Support P1020RDB-PD" select SUPPORT_SPL select SUPPORT_TPL + select ARCH_P1020 + +config TARGET_P1020UTM + bool "Support P1020UTM" + select SUPPORT_SPL + select SUPPORT_TPL + select ARCH_P1020 + +config TARGET_P1021RDB + bool "Support P1021RDB" + select SUPPORT_SPL + select SUPPORT_TPL + select ARCH_P1021 + +config TARGET_P1024RDB + bool "Support P1024RDB" + select SUPPORT_SPL + select SUPPORT_TPL + select ARCH_P1024 + +config TARGET_P1025RDB + bool "Support P1025RDB" + select SUPPORT_SPL + select SUPPORT_TPL + select ARCH_P1025 + +config TARGET_P2020RDB + bool "Support P2020RDB-PC" + select SUPPORT_SPL + select SUPPORT_TPL + select ARCH_P2020 config TARGET_P1_TWR bool "Support p1_twr" + select ARCH_P1025 config TARGET_P2041RDB bool "Support P2041RDB" + select ARCH_P2041 select PHYS_64BIT config TARGET_QEMU_PPCE500 bool "Support qemu-ppce500" + select ARCH_QEMU_E500 select PHYS_64BIT -config TARGET_T102XQDS - bool "Support T102xQDS" +config TARGET_T1024QDS + bool "Support T1024QDS" + select ARCH_T1024 select SUPPORT_SPL select PHYS_64BIT -config TARGET_T102XRDB - bool "Support T102xRDB" +config TARGET_T1023RDB + bool "Support T1023RDB" + select ARCH_T1023 + select SUPPORT_SPL + select PHYS_64BIT + +config TARGET_T1024RDB + bool "Support T1024RDB" + select ARCH_T1024 select SUPPORT_SPL select PHYS_64BIT config TARGET_T1040QDS bool "Support T1040QDS" + select ARCH_T1040 + select PHYS_64BIT + +config TARGET_T1040RDB + bool "Support T1040RDB" + select ARCH_T1040 + select SUPPORT_SPL + select PHYS_64BIT + +config TARGET_T1040D4RDB + bool "Support T1040D4RDB" + select ARCH_T1040 + select SUPPORT_SPL + select PHYS_64BIT + +config TARGET_T1042RDB + bool "Support T1042RDB" + select ARCH_T1042 + select SUPPORT_SPL + select PHYS_64BIT + +config TARGET_T1042D4RDB + bool "Support T1042D4RDB" + select ARCH_T1042 + select SUPPORT_SPL + select PHYS_64BIT + +config TARGET_T1042RDB_PI + bool "Support T1042RDB_PI" + select ARCH_T1042 + select SUPPORT_SPL select PHYS_64BIT -config TARGET_T104XRDB - bool "Support T104xRDB" +config TARGET_T2080QDS + bool "Support T2080QDS" + select ARCH_T2080 select SUPPORT_SPL select PHYS_64BIT -config TARGET_T208XQDS - bool "Support T208xQDS" +config TARGET_T2080RDB + bool "Support T2080RDB" + select ARCH_T2080 select SUPPORT_SPL select PHYS_64BIT -config TARGET_T208XRDB - bool "Support T208xRDB" +config TARGET_T2081QDS + bool "Support T2081QDS" + select ARCH_T2081 + select SUPPORT_SPL + select PHYS_64BIT + +config TARGET_T4160QDS + bool "Support T4160QDS" + select ARCH_T4160 + select SUPPORT_SPL + select PHYS_64BIT + +config TARGET_T4160RDB + bool "Support T4160RDB" + select ARCH_T4160 select SUPPORT_SPL select PHYS_64BIT config TARGET_T4240QDS bool "Support T4240QDS" + select ARCH_T4240 select SUPPORT_SPL select PHYS_64BIT config TARGET_T4240RDB bool "Support T4240RDB" + select ARCH_T4240 select SUPPORT_SPL select PHYS_64BIT config TARGET_CONTROLCENTERD bool "Support controlcenterd" + select ARCH_P1022 config TARGET_KMP204X bool "Support kmp204x" + select ARCH_P2041 select PHYS_64BIT config TARGET_XPEDITE520X bool "Support xpedite520x" + select ARCH_MPC8548 config TARGET_XPEDITE537X bool "Support xpedite537x" + select ARCH_MPC8572 config TARGET_XPEDITE550X bool "Support xpedite550x" + select ARCH_P2020 config TARGET_UCP1020 bool "Support uCP1020" + select ARCH_P1020 config TARGET_CYRUS bool "Support Varisys Cyrus" @@ -172,6 +315,156 @@ config TARGET_CYRUS endchoice +config ARCH_B4420 + bool + +config ARCH_B4860 + bool + +config ARCH_BSC9131 + bool + +config ARCH_BSC9132 + bool + +config ARCH_C29X + bool + +config ARCH_MPC8536 + bool + +config ARCH_MPC8540 + bool + +config ARCH_MPC8541 + bool + +config ARCH_MPC8544 + bool + +config ARCH_MPC8548 + bool + +config ARCH_MPC8555 + bool + +config ARCH_MPC8560 + bool + +config ARCH_MPC8568 + bool + +config ARCH_MPC8569 + bool + +config ARCH_MPC8572 + bool + +config ARCH_P1010 + bool + +config ARCH_P1011 + bool + +config ARCH_P1020 + bool + +config ARCH_P1021 + bool + +config ARCH_P1022 + bool + +config ARCH_P1023 + bool + +config ARCH_P1024 + bool + +config ARCH_P1025 + bool + +config ARCH_P2020 + bool + +config ARCH_P2041 + bool + +config ARCH_P3041 + bool + +config ARCH_P4080 + bool + +config ARCH_P5020 + bool + +config ARCH_P5040 + bool + +config ARCH_QEMU_E500 + bool + +config ARCH_T1023 + bool + +config ARCH_T1024 + bool + +config ARCH_T1040 + bool + +config ARCH_T1042 + bool + +config ARCH_T2080 + bool + +config ARCH_T2081 + bool + +config ARCH_T4160 + bool + +config ARCH_T4240 + bool + +config MAX_CPUS + int "Maximum number of CPUs permitted for MPC85xx" + default 12 if ARCH_T4240 + default 8 if ARCH_P4080 || \ + ARCH_T4160 + default 4 if ARCH_B4860 || \ + ARCH_P2041 || \ + ARCH_P3041 || \ + ARCH_P5040 || \ + ARCH_T1040 || \ + ARCH_T1042 || \ + ARCH_T2080 || \ + ARCH_T2081 + default 2 if ARCH_B4420 || \ + ARCH_BSC9132 || \ + ARCH_MPC8572 || \ + ARCH_P1020 || \ + ARCH_P1021 || \ + ARCH_P1022 || \ + ARCH_P1023 || \ + ARCH_P1024 || \ + ARCH_P1025 || \ + ARCH_P2020 || \ + ARCH_P5020 || \ + ARCH_T1020 || \ + ARCH_T1022 || \ + ARCH_T1023 || \ + ARCH_T1024 + default 1 + help + Set this number to the maximum number of possible CPUs in the SoC. + SoCs may have multiple clusters with each cluster may have multiple + ports. If some ports are reserved but higher ports are used for + cores, count the reserved ports. This will allocate enough memory + in spin table to properly handle all cores. + source "board/freescale/b4860qds/Kconfig" source "board/freescale/bsc9131rdb/Kconfig" source "board/freescale/bsc9132qds/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index f4c4fe2602..46ed22cafc 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -39,24 +39,23 @@ obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o # various SoC specific assignments -obj-$(CONFIG_PPC_P2041) += p2041_ids.o -obj-$(CONFIG_PPC_P3041) += p3041_ids.o -obj-$(CONFIG_PPC_P4080) += p4080_ids.o -obj-$(CONFIG_PPC_P5020) += p5020_ids.o -obj-$(CONFIG_PPC_P5040) += p5040_ids.o -obj-$(CONFIG_PPC_T4240) += t4240_ids.o -obj-$(CONFIG_PPC_T4160) += t4240_ids.o -obj-$(CONFIG_PPC_T4080) += t4240_ids.o -obj-$(CONFIG_PPC_B4420) += b4860_ids.o -obj-$(CONFIG_PPC_B4860) += b4860_ids.o -obj-$(CONFIG_PPC_T1040) += t1040_ids.o -obj-$(CONFIG_PPC_T1042) += t1040_ids.o +obj-$(CONFIG_ARCH_P2041) += p2041_ids.o +obj-$(CONFIG_ARCH_P3041) += p3041_ids.o +obj-$(CONFIG_ARCH_P4080) += p4080_ids.o +obj-$(CONFIG_ARCH_P5020) += p5020_ids.o +obj-$(CONFIG_ARCH_P5040) += p5040_ids.o +obj-$(CONFIG_ARCH_T4240) += t4240_ids.o +obj-$(CONFIG_ARCH_T4160) += t4240_ids.o +obj-$(CONFIG_ARCH_B4420) += b4860_ids.o +obj-$(CONFIG_ARCH_B4860) += b4860_ids.o +obj-$(CONFIG_ARCH_T1040) += t1040_ids.o +obj-$(CONFIG_ARCH_T1042) += t1040_ids.o obj-$(CONFIG_PPC_T1020) += t1040_ids.o obj-$(CONFIG_PPC_T1022) += t1040_ids.o -obj-$(CONFIG_PPC_T1023) += t1024_ids.o -obj-$(CONFIG_PPC_T1024) += t1024_ids.o -obj-$(CONFIG_PPC_T2080) += t2080_ids.o -obj-$(CONFIG_PPC_T2081) += t2080_ids.o +obj-$(CONFIG_ARCH_T1023) += t1024_ids.o +obj-$(CONFIG_ARCH_T1024) += t1024_ids.o +obj-$(CONFIG_ARCH_T2080) += t2080_ids.o +obj-$(CONFIG_ARCH_T2081) += t2080_ids.o obj-$(CONFIG_QE) += qe_io.o @@ -65,52 +64,46 @@ obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o # SoC specific SERDES support -obj-$(CONFIG_PPC_C29X) += c29x_serdes.o -obj-$(CONFIG_MPC8536) += mpc8536_serdes.o -obj-$(CONFIG_MPC8544) += mpc8544_serdes.o -obj-$(CONFIG_MPC8548) += mpc8548_serdes.o -obj-$(CONFIG_MPC8568) += mpc8568_serdes.o -obj-$(CONFIG_MPC8569) += mpc8569_serdes.o -obj-$(CONFIG_MPC8572) += mpc8572_serdes.o -obj-$(CONFIG_P1010) += p1010_serdes.o -obj-$(CONFIG_P1011) += p1021_serdes.o -obj-$(CONFIG_P1012) += p1021_serdes.o -obj-$(CONFIG_P1013) += p1022_serdes.o -obj-$(CONFIG_P1014) += p1010_serdes.o -obj-$(CONFIG_P1017) += p1023_serdes.o -obj-$(CONFIG_P1020) += p1021_serdes.o -obj-$(CONFIG_P1021) += p1021_serdes.o -obj-$(CONFIG_P1022) += p1022_serdes.o -obj-$(CONFIG_P1023) += p1023_serdes.o -obj-$(CONFIG_P1024) += p1021_serdes.o -obj-$(CONFIG_P1025) += p1021_serdes.o -obj-$(CONFIG_P2010) += p2020_serdes.o -obj-$(CONFIG_P2020) += p2020_serdes.o -obj-$(CONFIG_PPC_P2041) += p2041_serdes.o -obj-$(CONFIG_PPC_P3041) += p3041_serdes.o -obj-$(CONFIG_PPC_P4080) += p4080_serdes.o -obj-$(CONFIG_PPC_P5020) += p5020_serdes.o -obj-$(CONFIG_PPC_P5040) += p5040_serdes.o -obj-$(CONFIG_PPC_T4240) += t4240_serdes.o -obj-$(CONFIG_PPC_T4160) += t4240_serdes.o -obj-$(CONFIG_PPC_T4080) += t4240_serdes.o -obj-$(CONFIG_PPC_B4420) += b4860_serdes.o -obj-$(CONFIG_PPC_B4860) += b4860_serdes.o -obj-$(CONFIG_BSC9132) += bsc9132_serdes.o -obj-$(CONFIG_PPC_T1040) += t1040_serdes.o -obj-$(CONFIG_PPC_T1042) += t1040_serdes.o +obj-$(CONFIG_ARCH_C29X) += c29x_serdes.o +obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o +obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o +obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o +obj-$(CONFIG_ARCH_MPC8568) += mpc8568_serdes.o +obj-$(CONFIG_ARCH_MPC8569) += mpc8569_serdes.o +obj-$(CONFIG_ARCH_MPC8572) += mpc8572_serdes.o +obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o +obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o +obj-$(CONFIG_ARCH_P1020) += p1021_serdes.o +obj-$(CONFIG_ARCH_P1021) += p1021_serdes.o +obj-$(CONFIG_ARCH_P1022) += p1022_serdes.o +obj-$(CONFIG_ARCH_P1023) += p1023_serdes.o +obj-$(CONFIG_ARCH_P1024) += p1021_serdes.o +obj-$(CONFIG_ARCH_P1025) += p1021_serdes.o +obj-$(CONFIG_ARCH_P2020) += p2020_serdes.o +obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o +obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o +obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o +obj-$(CONFIG_ARCH_P5020) += p5020_serdes.o +obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o +obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o +obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o +obj-$(CONFIG_ARCH_B4420) += b4860_serdes.o +obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o +obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o +obj-$(CONFIG_ARCH_T1040) += t1040_serdes.o +obj-$(CONFIG_ARCH_T1042) += t1040_serdes.o obj-$(CONFIG_PPC_T1020) += t1040_serdes.o obj-$(CONFIG_PPC_T1022) += t1040_serdes.o -obj-$(CONFIG_PPC_T1023) += t1024_serdes.o -obj-$(CONFIG_PPC_T1024) += t1024_serdes.o -obj-$(CONFIG_PPC_T2080) += t2080_serdes.o -obj-$(CONFIG_PPC_T2081) += t2080_serdes.o +obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o +obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o +obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o +obj-$(CONFIG_ARCH_T2081) += t2080_serdes.o obj-y += cpu.o obj-y += cpu_init.o obj-y += cpu_init_early.o obj-y += interrupts.o -ifneq ($(CONFIG_QEMU_E500),y) +ifneq ($(CONFIG_ARCH_QEMU_E500),y) obj-y += speed.o endif obj-y += tlb.o diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c index 85eba0b22d..4ceb6f51f3 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -62,7 +62,7 @@ struct liodn_id_table liodn_tbl[] = { SET_DMA_LIODN(1, "fsl,elo3-dma", 147), SET_DMA_LIODN(2, "fsl,elo3-dma", 227), -#ifndef CONFIG_PPC_B4420 +#ifndef CONFIG_ARCH_B4420 SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), @@ -81,7 +81,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 3, 91), SET_FMAN_RX_1G_LIODN(1, 4, 92), SET_FMAN_RX_1G_LIODN(1, 5, 93), -#ifndef CONFIG_PPC_B4420 +#ifndef CONFIG_ARCH_B4420 SET_FMAN_RX_10G_LIODN(1, 0, 94), SET_FMAN_RX_10G_LIODN(1, 1, 95), #endif diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c index 63172def68..a5709dddc0 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c @@ -15,7 +15,7 @@ struct serdes_config { u8 lanes[SRDS_MAX_LANES]; }; -#ifdef CONFIG_PPC_B4860 +#ifdef CONFIG_ARCH_B4860 static struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ {0x01, {AURORA, AURORA, CPRI6, CPRI5, @@ -180,7 +180,7 @@ static struct serdes_config serdes2_cfg_tbl[] = { }; #endif -#ifdef CONFIG_PPC_B4420 +#ifdef CONFIG_ARCH_B4420 static struct serdes_config serdes1_cfg_tbl[] = { {0x0D, {NONE, NONE, CPRI6, CPRI5, CPRI4, CPRI3, NONE, NONE} }, diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 3b06ae42e4..402a1ff33c 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -26,12 +26,12 @@ static void check_erratum_a4849(uint32_t svr) void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000; unsigned int i; -#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041) +#if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041) static const uint8_t offsets[] = { 0x50, 0x54, 0x58, 0x90, 0x94, 0x98 }; #endif -#ifdef CONFIG_PPC_P4080 +#ifdef CONFIG_ARCH_P4080 static const uint8_t offsets[] = { 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac }; @@ -45,11 +45,11 @@ static void check_erratum_a4849(uint32_t svr) } } -#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041) +#if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041) x108 = 0x12; #endif -#ifdef CONFIG_PPC_P4080 +#ifdef CONFIG_ARCH_P4080 /* * For P4080, the erratum document says that the value at offset 0x108 * should be 0x12 on rev2, or 0x1c on rev3. @@ -323,7 +323,8 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (IS_SVR_REV(svr, 1, 0)) puts("Work-around for Erratum A-008044 enabled\n"); #endif -#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && defined(CONFIG_B4860QDS) +#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && \ + (defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)) puts("Work-around for Erratum XFI on B4860QDS enabled\n"); #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A009663 diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index cabf64cf8c..d180c73929 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -293,8 +293,8 @@ int checkcpu (void) int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { /* Everything after the first generation of PQ3 parts has RSTCR */ -#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ - defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) +#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \ + defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560) unsigned long val, msr; /* @@ -404,7 +404,7 @@ void mpc85xx_reginfo(void) phys_size_t initdram(int board_type) { #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \ - defined(CONFIG_QEMU_E500) + defined(CONFIG_ARCH_QEMU_E500) return fsl_ddr_sdram_size(); #else return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 53b3729f98..c2402a8bda 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -442,7 +442,7 @@ ulong cpu_init_f(void) #if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT) struct law_entry law; #endif -#ifdef CONFIG_MPC8548 +#ifdef CONFIG_ARCH_MPC8548 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); uint svr = get_svr(); @@ -959,7 +959,7 @@ int cpu_init_r(void) #ifdef CONFIG_FSL_CAAM sec_init(); -#if defined(CONFIG_PPC_C29X) +#if defined(CONFIG_ARCH_C29X) if ((SVR_SOC_VER(svr) == SVR_C292) || (SVR_SOC_VER(svr) == SVR_C293)) sec_init_idx(1); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index aa519b03fe..345d693ec4 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -97,7 +97,7 @@ void cpu_init_early_f(void *fdt) /* gd area was zeroed during startup */ -#ifdef CONFIG_QEMU_E500 +#ifdef CONFIG_ARCH_QEMU_E500 /* * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems, * so we need to populate it before it accesses it. diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 047c972ac7..12001f85e9 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -490,7 +490,7 @@ static void ft_fixup_qe_snum(void *blob) } #endif -#if defined(CONFIG_PPC_P4080) +#if defined(CONFIG_ARCH_P4080) static void fdt_fixup_usb(void *fdt) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -511,8 +511,8 @@ static void fdt_fixup_usb(void *fdt) #define fdt_fixup_usb(x) #endif -#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T4240) || \ - defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080) +#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \ + defined(CONFIG_ARCH_T4160) void fdt_fixup_dma3(void *blob) { /* the 3rd DMA is not functional if SRIO2 is chosen */ @@ -520,7 +520,7 @@ void fdt_fixup_dma3(void *blob) ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300) -#if defined(CONFIG_PPC_T2080) +#if defined(CONFIG_ARCH_T2080) u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; @@ -529,8 +529,7 @@ void fdt_fixup_dma3(void *blob) case 0x29: case 0x2d: case 0x2e: -#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ - defined(CONFIG_PPC_T4080) +#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS4_PRTCL; srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; @@ -556,7 +555,7 @@ void fdt_fixup_dma3(void *blob) #define fdt_fixup_dma3(x) #endif -#if defined(CONFIG_PPC_T1040) +#if defined(CONFIG_ARCH_T1040) static void fdt_fixup_l2_switch(void *blob) { uchar l2swaddr[6]; diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 810ddb0867..677b062044 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -391,7 +391,7 @@ const char *serdes_clock_to_string(u32 clock) case SRDS_PLLCR0_RFCK_SEL_161_13: return "161.1328123"; default: -#if defined(CONFIG_T4240QDS) +#if defined(CONFIG_TARGET_T4240QDS) || defined(CONFIG_TARGET_T4160QDS) return "???"; #else return "122.88"; diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index b6c4341544..1bc0c64cfc 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -76,7 +76,7 @@ static const struct { { 17, 163, FSL_SRDS_BANK_2 }, { 18, 164, FSL_SRDS_BANK_2 }, { 19, 165, FSL_SRDS_BANK_2 }, -#ifdef CONFIG_PPC_P4080 +#ifdef CONFIG_ARCH_P4080 { 20, 170, FSL_SRDS_BANK_3 }, { 21, 171, FSL_SRDS_BANK_3 }, { 22, 172, FSL_SRDS_BANK_3 }, @@ -491,7 +491,7 @@ void fsl_serdes_init(void) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int cfg; serdes_corenet_t *srds_regs; -#ifdef CONFIG_PPC_P5040 +#ifdef CONFIG_ARCH_P5040 serdes_corenet_t *srds2_regs; #endif int lane, bank, idx; @@ -577,7 +577,7 @@ void fsl_serdes_init(void) } } -#ifdef CONFIG_PPC_P5040 +#ifdef CONFIG_ARCH_P5040 /* * Lanes on bank 4 on P5040 are commented-out, but for some SERDES * protocols, these lanes are routed to SATA. We use serdes_prtcl_map diff --git a/arch/powerpc/cpu/mpc85xx/pci.c b/arch/powerpc/cpu/mpc85xx/pci.c index c6d2fda5db..538729f388 100644 --- a/arch/powerpc/cpu/mpc85xx/pci.c +++ b/arch/powerpc/cpu/mpc85xx/pci.c @@ -120,7 +120,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose) pci_register_hose(hose); -#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS) +#if defined(CONFIG_TARGET_MPC8555CDS) || defined(CONFIG_TARGET_MPC8541CDS) /* * This is a SW workaround for an apparent HW problem * in the PCI controller on the MPC85555/41 CDS boards. diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index e732969e41..fcf5d92af5 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -130,9 +130,8 @@ void get_sys_info(sys_info_t *sys_info) * it uses 6. * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0 */ -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ - defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) || \ - defined(CONFIG_PPC_T2081) +#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \ + defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) svr = get_svr(); switch (SVR_SOC_VER(svr)) { case SVR_T4240: @@ -202,11 +201,11 @@ void get_sys_info(sys_info_t *sys_info) } #endif -#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \ - defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \ + defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) #define FM1_CLK_SEL 0xe0000000 #define FM1_CLK_SHIFT 29 -#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) +#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) #define FM1_CLK_SEL 0x00000007 #define FM1_CLK_SHIFT 0 #else @@ -216,7 +215,7 @@ void get_sys_info(sys_info_t *sys_info) #define FM1_CLK_SHIFT 26 #endif #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) -#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) +#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) rcw_tmp = in_be32(&gur->rcwsr[15]) - 4; #else rcw_tmp = in_be32(&gur->rcwsr[7]); @@ -456,7 +455,7 @@ void get_sys_info(sys_info_t *sys_info) #endif #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK -#if defined(CONFIG_PPC_T2080) +#if defined(CONFIG_ARCH_T2080) #define ESDHC_CLK_SEL 0x00000007 #define ESDHC_CLK_SHIFT 0 #define ESDHC_CLK_RCWSR 15 @@ -480,7 +479,7 @@ void get_sys_info(sys_info_t *sys_info) case 4: sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4; break; -#if defined(CONFIG_PPC_T2080) +#if defined(CONFIG_ARCH_T2080) case 5: sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK]; break; @@ -596,7 +595,7 @@ void get_sys_info(sys_info_t *sys_info) #endif #ifdef CONFIG_QE -#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) sys_info->freq_qe = sys_info->freq_systembus; #else qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) @@ -625,8 +624,8 @@ void get_sys_info(sys_info_t *sys_info) * for four times the clock divider values. */ lcrr_div *= 4; -#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ - !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) +#elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \ + !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_ARCH_MPC8560) /* * Yes, the entire PQ38 family use the same * bit-representation for twice the clock divider values. @@ -652,7 +651,7 @@ void get_sys_info(sys_info_t *sys_info) int get_clocks (void) { sys_info_t sys_info; -#ifdef CONFIG_MPC8544 +#ifdef CONFIG_ARCH_MPC8544 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; #endif #if defined(CONFIG_CPM2) @@ -681,11 +680,11 @@ int get_clocks (void) * for that SOC. This information is taken from application note * AN2919. */ -#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ - defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \ - defined(CONFIG_P1022) +#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \ + defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \ + defined(CONFIG_ARCH_P1022) gd->arch.i2c1_clk = sys_info.freq_systembus; -#elif defined(CONFIG_MPC8544) +#elif defined(CONFIG_ARCH_MPC8544) /* * On the 8544, the I2C clock is the same as the SEC clock. This can be * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See @@ -707,8 +706,7 @@ int get_clocks (void) #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK gd->arch.sdhc_clk = sys_info.freq_sdhc / 2; #else -#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ - defined(CONFIG_P1014) +#if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010) gd->arch.sdhc_clk = gd->bus_clk; #else gd->arch.sdhc_clk = gd->bus_clk / 2; diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index c3e12349f7..932216c237 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -311,7 +311,7 @@ l2_disabled: #endif mtspr HID0,r0 -#if !defined(CONFIG_E500MC) && !defined(CONFIG_QEMU_E500) +#if !defined(CONFIG_E500MC) && !defined(CONFIG_ARCH_QEMU_E500) li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ mfspr r3,PVR andi. r3,r3, 0xff @@ -345,7 +345,7 @@ l2_disabled: mtspr DBCR0,r0 #endif -#ifdef CONFIG_MPC8569 +#ifdef CONFIG_ARCH_MPC8569 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000) #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0) @@ -376,7 +376,7 @@ l2_disabled: tlbivax 0,r4 isync -#endif /* CONFIG_MPC8569 */ +#endif /* CONFIG_ARCH_MPC8569 */ /* * Search for the TLB that covers the code we're executing, and shrink it diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c index c65f41d0f8..fc63fe3613 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c @@ -161,7 +161,7 @@ static const struct serdes_config serdes1_cfg_tbl[] = { {} }; -#ifndef CONFIG_PPC_T2081 +#ifndef CONFIG_ARCH_T2081 static const struct serdes_config serdes2_cfg_tbl[] = { /* SerDes 2 */ {0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, @@ -181,7 +181,7 @@ static const struct serdes_config serdes2_cfg_tbl[] = { static const struct serdes_config *serdes_cfg_tbl[] = { serdes1_cfg_tbl, -#ifndef CONFIG_PPC_T2081 +#ifndef CONFIG_ARCH_T2081 serdes2_cfg_tbl, #endif }; diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c index 7b43b282bb..3fc527d375 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -15,7 +15,7 @@ struct serdes_config { u8 lanes[SRDS_MAX_LANES]; }; -#ifdef CONFIG_PPC_T4240 +#ifdef CONFIG_ARCH_T4240 static const struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, @@ -263,7 +263,7 @@ static const struct serdes_config serdes4_cfg_tbl[] = { {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}}, {} }; -#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080) +#elif defined(CONFIG_ARCH_T4160) static const struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ {1, {NONE, NONE, NONE, NONE, diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig index fe1859d206..98fb702e86 100644 --- a/arch/powerpc/cpu/mpc86xx/Kconfig +++ b/arch/powerpc/cpu/mpc86xx/Kconfig @@ -10,18 +10,28 @@ choice config TARGET_SBC8641D bool "Support sbc8641d" + select ARCH_MPC8641 config TARGET_MPC8610HPCD bool "Support MPC8610HPCD" + select ARCH_MPC8610 config TARGET_MPC8641HPCN bool "Support MPC8641HPCN" + select ARCH_MPC8641 config TARGET_XPEDITE517X bool "Support xpedite517x" + select ARCH_MPC8641 endchoice +config ARCH_MPC8610 + bool + +config ARCH_MPC8641 + bool + source "board/freescale/mpc8610hpcd/Kconfig" source "board/freescale/mpc8641hpcn/Kconfig" source "board/sbc8641d/Kconfig" diff --git a/arch/powerpc/cpu/mpc86xx/Makefile b/arch/powerpc/cpu/mpc86xx/Makefile index 0f790b0efc..88c23fc58c 100644 --- a/arch/powerpc/cpu/mpc86xx/Makefile +++ b/arch/powerpc/cpu/mpc86xx/Makefile @@ -19,6 +19,6 @@ obj-y += cpu_init.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-y += interrupts.o obj-$(CONFIG_MP) += mp.o -obj-$(CONFIG_MPC8610) += mpc8610_serdes.o -obj-$(CONFIG_MPC8641) += mpc8641_serdes.o +obj-$(CONFIG_ARCH_MPC8610) += mpc8610_serdes.o +obj-$(CONFIG_ARCH_MPC8641) += mpc8641_serdes.o obj-y += speed.o diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c index 30518544dd..7a9570c8ec 100644 --- a/arch/powerpc/cpu/mpc86xx/cpu.c +++ b/arch/powerpc/cpu/mpc86xx/cpu.c @@ -90,9 +90,9 @@ checkcpu(void) puts("L2: "); if (get_l2cr() & 0x80000000) { -#if defined(CONFIG_MPC8610) +#if defined(CONFIG_ARCH_MPC8610) puts("256"); -#elif defined(CONFIG_MPC8641) +#elif defined(CONFIG_ARCH_MPC8641) puts("512"); #endif puts(" KiB enabled\n"); @@ -139,7 +139,7 @@ get_tbclk(void) void watchdog_reset(void) { -#if defined(CONFIG_MPC8610) +#if defined(CONFIG_ARCH_MPC8610) /* * This actually feed the hard enabled watchdog. */ diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c index 5abe6f0bf2..05f23db457 100644 --- a/arch/powerpc/cpu/mpc86xx/speed.c +++ b/arch/powerpc/cpu/mpc86xx/speed.c @@ -115,7 +115,7 @@ int get_clocks(void) * for that SOC. This information is taken from application note * AN2919. */ -#ifdef CONFIG_MPC8610 +#ifdef CONFIG_ARCH_MPC8610 gd->arch.i2c1_clk = sys_info.freq_systembus; #else gd->arch.i2c1_clk = sys_info.freq_systembus / 2; diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index bb23756d79..9d3a3b45c0 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -57,10 +57,6 @@ #endif #endif -#ifndef CONFIG_MAX_CPUS -#define CONFIG_MAX_CPUS 1 -#endif - /* * Provide a default boot page translation virtual address that lines up with * Freescale's default e500 reset page. diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 6d845e859f..c92bc1ec40 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -35,8 +35,7 @@ #define CONFIG_SYS_NUM_TLBCAMS 16 #endif -#if defined(CONFIG_MPC8536) -#define CONFIG_MAX_CPUS 1 +#if defined(CONFIG_ARCH_MPC8536) #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -44,21 +43,18 @@ #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 -#elif defined(CONFIG_MPC8540) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_MPC8540) #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#elif defined(CONFIG_MPC8541) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_MPC8541) #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#elif defined(CONFIG_MPC8544) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_MPC8544) #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 @@ -66,8 +62,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_A005125 -#elif defined(CONFIG_MPC8548) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_MPC8548) #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 @@ -85,21 +80,18 @@ #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 -#elif defined(CONFIG_MPC8555) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_MPC8555) #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#elif defined(CONFIG_MPC8560) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_MPC8560) #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#elif defined(CONFIG_MPC8568) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_MPC8568) #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -113,8 +105,7 @@ #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 -#elif defined(CONFIG_MPC8569) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_MPC8569) #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define QE_MURAM_SIZE 0x20000UL @@ -129,8 +120,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 -#elif defined(CONFIG_MPC8572) -#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_ARCH_MPC8572) #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -140,8 +130,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 -#elif defined(CONFIG_P1010) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_P1010) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 @@ -169,8 +158,7 @@ #define CONFIG_ESDHC_HC_BLK_ADDR /* P1011 is single core version of P1020 */ -#elif defined(CONFIG_P1011) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_P1011) #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 @@ -183,75 +171,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 -/* P1012 is single core version of P1021 */ -#elif defined(CONFIG_P1012) -#define CONFIG_MAX_CPUS 1 -#define CONFIG_SYS_FSL_NUM_LAWS 12 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 -#define CONFIG_TSECV2 -#define CONFIG_FSL_PCIE_DISABLE_ASPM -#define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define QE_MURAM_SIZE 0x6000UL -#define MAX_QE_RISC 1 -#define QE_NUM_OF_SNUM 28 -#define CONFIG_SYS_FSL_ERRATUM_A004508 -#define CONFIG_SYS_FSL_ERRATUM_A005125 - -/* P1013 is single core version of P1022 */ -#elif defined(CONFIG_P1013) -#define CONFIG_MAX_CPUS 1 -#define CONFIG_SYS_FSL_NUM_LAWS 12 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 -#define CONFIG_TSECV2 -#define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define CONFIG_FSL_SATA_ERRATUM_A001 -#define CONFIG_SYS_FSL_ERRATUM_A004508 -#define CONFIG_SYS_FSL_ERRATUM_A005125 - -#elif defined(CONFIG_P1014) -#define CONFIG_MAX_CPUS 1 -#define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_SYS_FSL_NUM_LAWS 12 -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 -#define CONFIG_TSECV2 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 -#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 -#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 -#define CONFIG_SYS_FSL_ERRATUM_A004508 - -/* P1017 is single core version of P1023 */ -#elif defined(CONFIG_P1017) -#define CONFIG_MAX_CPUS 1 -#define CONFIG_SYS_FSL_NUM_LAWS 12 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 2 -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_SYS_QMAN_NUM_PORTALS 3 -#define CONFIG_SYS_BMAN_NUM_PORTALS 3 -#define CONFIG_SYS_FM_MURAM_SIZE 0x10000 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 -#define CONFIG_SYS_FSL_ERRATUM_A004508 -#define CONFIG_SYS_FSL_ERRATUM_A005125 - -#elif defined(CONFIG_P1020) -#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_ARCH_P1020) #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 @@ -266,8 +186,7 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif -#elif defined(CONFIG_P1021) -#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_ARCH_P1021) #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 @@ -283,8 +202,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#elif defined(CONFIG_P1022) -#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_ARCH_P1022) #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 @@ -298,8 +216,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_A004477 -#elif defined(CONFIG_P1023) -#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_ARCH_P1023) #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 @@ -317,8 +234,7 @@ #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 /* P1024 is lower end variant of P1020 */ -#elif defined(CONFIG_P1024) -#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_ARCH_P1024) #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 @@ -332,8 +248,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125 /* P1025 is lower end variant of P1021 */ -#elif defined(CONFIG_P1025) -#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_ARCH_P1025) #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 @@ -349,21 +264,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 -/* P2010 is single core version of P2020 */ -#elif defined(CONFIG_P2010) -#define CONFIG_MAX_CPUS 1 -#define CONFIG_SYS_FSL_NUM_LAWS 12 -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 -#define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 -#define CONFIG_SYS_FSL_ERRATUM_A004508 -#define CONFIG_SYS_FSL_ERRATUM_A005125 - -#elif defined(CONFIG_P2020) -#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_ARCH_P2020) #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -380,10 +281,9 @@ #define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ +#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 @@ -418,10 +318,9 @@ #define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 -#elif defined(CONFIG_PPC_P3041) +#elif defined(CONFIG_ARCH_P3041) #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 @@ -458,10 +357,9 @@ #define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 -#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ +#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_MAX_CPUS 8 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 @@ -509,11 +407,10 @@ #define CONFIG_SYS_FSL_ERRATUM_A007075 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 -#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ +#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */ #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 @@ -545,11 +442,10 @@ #define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 -#elif defined(CONFIG_PPC_P5040) +#elif defined(CONFIG_ARCH_P5040) #define CONFIG_SYS_PPC64 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 @@ -579,8 +475,7 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #define CONFIG_SYS_FSL_ERRATUM_A005812 -#elif defined(CONFIG_BSC9131) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_BSC9131) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 @@ -598,8 +493,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_ESDHC_HC_BLK_ADDR -#elif defined(CONFIG_BSC9132) -#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_ARCH_BSC9132) #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 @@ -625,16 +519,14 @@ #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #define CONFIG_ESDHC_HC_BLK_ADDR -#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ - defined(CONFIG_PPC_T4080) +#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) #define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ -#ifdef CONFIG_PPC_T4240 -#define CONFIG_MAX_CPUS 12 +#ifdef CONFIG_ARCH_T4240 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 2 @@ -648,12 +540,8 @@ #define CONFIG_SYS_NUM_FM2_DTSEC 8 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 -#if defined(CONFIG_PPC_T4160) -#define CONFIG_MAX_CPUS 8 +#if defined(CONFIG_ARCH_T4160) #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#elif defined(CONFIG_PPC_T4080) -#define CONFIG_MAX_CPUS 4 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 } #endif #endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 @@ -691,7 +579,7 @@ #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_PCI_VER_3_X -#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) +#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) #define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -733,9 +621,8 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_SFP_VER_3_0 -#ifdef CONFIG_PPC_B4860 +#ifdef CONFIG_ARCH_B4860 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 -#define CONFIG_MAX_CPUS 4 #define CONFIG_MAX_DSP_CPUS 12 #define CONFIG_NUM_DSP_CPUS 6 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 @@ -749,7 +636,6 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_SRIO_LIODN #else -#define CONFIG_MAX_CPUS 2 #define CONFIG_MAX_DSP_CPUS 2 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 @@ -759,7 +645,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #endif -#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ +#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_E5500 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -769,11 +655,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #ifdef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_FSL_DDRC_GEN4 #endif -#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) -#define CONFIG_MAX_CPUS 4 -#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) -#define CONFIG_MAX_CPUS 2 -#endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_NUM_LAWS 16 @@ -810,7 +691,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_ERRATUM_A008378 #define CONFIG_SYS_FSL_ERRATUM_A009663 -#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ +#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) ||\ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_E5500 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -821,11 +702,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #ifdef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_FSL_DDRC_GEN4 #endif -#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) -#define CONFIG_MAX_CPUS 2 -#elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) -#define CONFIG_MAX_CPUS 1 -#endif #define CONFIG_SYS_FSL_NUM_CC_PLL 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_NUM_LAWS 16 @@ -859,7 +735,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_ERRATUM_A008378 #define CONFIG_SYS_FSL_ERRATUM_A009663 -#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) #define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -867,14 +743,13 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_QMAN_V3 -#define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_PCI_VER_3_X -#if defined(CONFIG_PPC_T2080) +#if defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 4 #define CONFIG_SYS_FSL_SRDS_2 @@ -882,7 +757,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#elif defined(CONFIG_PPC_T2081) +#elif defined(CONFIG_ARCH_T2081) #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 #endif @@ -914,8 +789,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_SFP_VER_3_0 -#elif defined(CONFIG_PPC_C29X) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_C29X) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 @@ -930,8 +804,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000 -#elif defined(CONFIG_QEMU_E500) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_QEMU_E500) #define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000 #else @@ -955,7 +828,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_DDRC_GEN3 #endif -#if !defined(CONFIG_PPC_C29X) +#if !defined(CONFIG_ARCH_C29X) #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #endif diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h index 4f9b2252be..c41dc99681 100644 --- a/arch/powerpc/include/asm/config_mpc86xx.h +++ b/arch/powerpc/include/asm/config_mpc86xx.h @@ -11,12 +11,10 @@ /* SoC specific defines for Freescale MPC86xx processors */ -#if defined(CONFIG_MPC8610) -#define CONFIG_MAX_CPUS 1 +#if defined(CONFIG_ARCH_MPC8610) #define CONFIG_SYS_FSL_NUM_LAWS 10 -#elif defined(CONFIG_MPC8641) -#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_ARCH_MPC8641) #define CONFIG_SYS_FSL_NUM_LAWS 10 #else diff --git a/arch/powerpc/include/asm/cpm_85xx.h b/arch/powerpc/include/asm/cpm_85xx.h index b137a71450..b46e20e5ce 100644 --- a/arch/powerpc/include/asm/cpm_85xx.h +++ b/arch/powerpc/include/asm/cpm_85xx.h @@ -77,7 +77,7 @@ */ #define CPM_DATAONLY_BASE ((uint)128) #define CPM_DP_NOSPACE ((uint)0x7FFFFFFF) -#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) #define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) #else /* MPC8540, MPC8560 */ diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 2a759c85b8..b348cc1f20 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -79,13 +79,13 @@ enum law_trgt_if { enum law_trgt_if { LAW_TRGT_IF_PCI = 0x00, LAW_TRGT_IF_PCI_2 = 0x01, -#ifndef CONFIG_MPC8641 +#ifndef CONFIG_ARCH_MPC8641 LAW_TRGT_IF_PCIE_1 = 0x02, #endif -#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132) +#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) LAW_TRGT_IF_OCN_DSP = 0x03, #else -#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020) +#if !defined(CONFIG_ARCH_MPC8572) && !defined(CONFIG_ARCH_P2020) LAW_TRGT_IF_PCIE_3 = 0x03, #endif #endif @@ -95,7 +95,7 @@ enum law_trgt_if { LAW_TRGT_IF_PLATFORM_SRAM = 0x0a, LAW_TRGT_IF_DDR_INTRLV = 0x0b, LAW_TRGT_IF_RIO = 0x0c, -#if defined(CONFIG_BSC9132) +#if defined(CONFIG_ARCH_BSC9132) LAW_TRGT_IF_CLASS_DSP = 0x0d, #else LAW_TRGT_IF_RIO_2 = 0x0d, @@ -117,11 +117,11 @@ enum law_trgt_if { #define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO #define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC -#ifdef CONFIG_MPC8641 +#ifdef CONFIG_ARCH_MPC8641 #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI #endif -#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) +#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020) #define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI #endif #endif /* CONFIG_FSL_CORENET */ diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 402edd7a2a..b8270c5ffd 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -325,9 +325,9 @@ void lbc_sdram_init(void); */ #define LCRR_CLKDIV 0x0000001F #define LCRR_CLKDIV_SHIFT 0 -#if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \ - defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \ - defined(CONFIG_MPC8560) +#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \ + defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) || \ + defined(CONFIG_ARCH_MPC8560) #define LCRR_CLKDIV_2 0x00000002 #define LCRR_CLKDIV_4 0x00000004 #define LCRR_CLKDIV_8 0x00000008 diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index f9154d3b40..808adae82d 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -16,25 +16,30 @@ #if defined(CONFIG_FSL_CORENET) #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 -#elif defined(CONFIG_BSC9132QDS) +#elif defined(CONFIG_TARGET_BSC9132QDS) #define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000 -#elif defined(CONFIG_C29XPCIE) +#elif defined(CONFIG_TARGET_C29XPCIE) #define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000 #else #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 #endif #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 -#if defined(CONFIG_B4860QDS) || \ - defined(CONFIG_T4240QDS) || \ +#if defined(CONFIG_TARGET_B4860QDS) || \ + defined(CONFIG_TARGET_B4420QDS) || \ + defined(CONFIG_TARGET_T4160QDS) || \ + defined(CONFIG_TARGET_T4240QDS) || \ defined(CONFIG_T2080QDS) || \ defined(CONFIG_T2080RDB) || \ defined(CONFIG_T1040QDS) || \ defined(CONFIG_T104xD4QDS) || \ - defined(CONFIG_T104xRDB) || \ - defined(CONFIG_T104xD4RDB) || \ - defined(CONFIG_PPC_T1023) || \ - defined(CONFIG_PPC_T1024) + defined(CONFIG_TARGET_T1040RDB) || \ + defined(CONFIG_TARGET_T1040D4RDB) || \ + defined(CONFIG_TARGET_T1042RDB) || \ + defined(CONFIG_TARGET_T1042D4RDB) || \ + defined(CONFIG_TARGET_T1042RDB_PI) || \ + defined(CONFIG_ARCH_T1023) || \ + defined(CONFIG_ARCH_T1024) #ifndef CONFIG_SYS_RAMBOOT #define CONFIG_SYS_CPC_REINIT_F #endif @@ -54,15 +59,15 @@ #endif #endif -#if defined(CONFIG_C29XPCIE) +#if defined(CONFIG_TARGET_C29XPCIE) #define CONFIG_KEY_REVOCATION #endif -#if defined(CONFIG_PPC_P3041) || \ - defined(CONFIG_PPC_P4080) || \ - defined(CONFIG_PPC_P5020) || \ - defined(CONFIG_PPC_P5040) || \ - defined(CONFIG_PPC_P2041) +#if defined(CONFIG_ARCH_P3041) || \ + defined(CONFIG_ARCH_P4080) || \ + defined(CONFIG_ARCH_P5020) || \ + defined(CONFIG_ARCH_P5040) || \ + defined(CONFIG_ARCH_P2041) #define CONFIG_FSL_TRUST_ARCH_v1 #endif @@ -134,13 +139,13 @@ /* The bootscript header address is different for B4860 because the NOR * mapping is different on B4 due to reduced NOR size. */ -#if defined(CONFIG_B4860QDS) +#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS) #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000 #elif defined(CONFIG_FSL_CORENET) #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000 -#elif defined(CONFIG_BSC9132QDS) +#elif defined(CONFIG_TARGET_BSC9132QDS) #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000 -#elif defined(CONFIG_C29XPCIE) +#elif defined(CONFIG_TARGET_C29XPCIE) #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000 #else #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 76ea00b04f..786e4f6765 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -124,10 +124,10 @@ typedef struct ccsr_i2c { u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)]; } ccsr_i2c_t; -#if defined(CONFIG_MPC8540) \ - || defined(CONFIG_MPC8541) \ - || defined(CONFIG_MPC8548) \ - || defined(CONFIG_MPC8555) +#if defined(CONFIG_ARCH_MPC8540) || \ + defined(CONFIG_ARCH_MPC8541) || \ + defined(CONFIG_ARCH_MPC8548) || \ + defined(CONFIG_ARCH_MPC8555) /* DUART Registers */ typedef struct ccsr_duart { u8 res1[1280]; @@ -1759,8 +1759,7 @@ typedef struct ccsr_gur { /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */ #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ - defined(CONFIG_PPC_T4080) +#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 @@ -1770,13 +1769,13 @@ typedef struct ccsr_gur { #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 -#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) +#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 -#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ +#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 @@ -1797,7 +1796,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define PXCKEN_MASK 0x80000000 #define PXCK_MASK 0x00FF0000 #define PXCK_BITS_START 16 -#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) || \ +#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) || \ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23 @@ -1812,7 +1811,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define PXCKEN_MASK 0x80000000 #define PXCK_MASK 0x00FF0000 #define PXCK_BITS_START 16 -#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 @@ -1848,7 +1847,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 #define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */ -#ifdef CONFIG_PPC_P4080 +#ifdef CONFIG_ARCH_P4080 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000 #define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */ @@ -1856,8 +1855,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000 #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000 #endif -#if defined(CONFIG_PPC_P2041) \ - || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020) +#if defined(CONFIG_ARCH_P2041) || \ + defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020) #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000 @@ -1866,7 +1865,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000 #endif -#if defined(CONFIG_PPC_P5040) +#if defined(CONFIG_ARCH_P5040) #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000 @@ -1875,8 +1874,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 #endif -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ - defined(CONFIG_PPC_T4080) +#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 @@ -1885,7 +1883,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 #endif -#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000 @@ -2120,16 +2118,16 @@ typedef struct ccsr_rcpm { #else typedef struct ccsr_gur { u32 porpllsr; /* POR PLL ratio status */ -#ifdef CONFIG_MPC8536 +#ifdef CONFIG_ARCH_MPC8536 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 -#elif defined(CONFIG_PPC_C29X) +#elif defined(CONFIG_ARCH_C29X) #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \ & MPC85xx_PORDEVSR2_DDR_SPD_0) \ >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT)) #else -#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132) +#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 #else #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 @@ -2150,7 +2148,7 @@ typedef struct ccsr_gur { #define PORBMSR_ROMLOC_NOR 0xf u32 porimpscr; /* POR I/O impedance status & control */ u32 pordevsr; /* POR I/O device status regsiter */ -#if defined(CONFIG_P1017) || defined(CONFIG_P1023) +#if defined(CONFIG_ARCH_P1023) #define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000 #define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000 @@ -2162,26 +2160,26 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 #define MPC85xx_PORDEVSR_PCI1 0x00800000 -#if defined(CONFIG_P1013) || defined(CONFIG_P1022) +#if defined(CONFIG_ARCH_P1022) #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18 -#elif defined(CONFIG_P1017) || defined(CONFIG_P1023) +#elif defined(CONFIG_ARCH_P1023) #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 #else -#if defined(CONFIG_P1010) +#if defined(CONFIG_ARCH_P1010) #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 -#elif defined(CONFIG_BSC9132) +#elif defined(CONFIG_ARCH_BSC9132) #define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17 -#elif defined(CONFIG_PPC_C29X) +#elif defined(CONFIG_ARCH_C29X) #define MPC85xx_PORDEVSR_IO_SEL 0x00e00000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 #else #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 -#endif /* if defined(CONFIG_P1010) */ +#endif /* if defined(CONFIG_ARCH_P1010) */ #endif #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 @@ -2193,7 +2191,7 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 u32 pordbgmsr; /* POR debug mode status */ u32 pordevsr2; /* POR I/O device status 2 */ -#if defined(CONFIG_PPC_C29X) +#if defined(CONFIG_ARCH_C29X) #define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3 #endif @@ -2203,14 +2201,14 @@ typedef struct ccsr_gur { u8 res1[8]; u32 gpporcr; /* General-purpose POR configuration */ u8 res2[12]; -#if defined(CONFIG_MPC8536) +#if defined(CONFIG_ARCH_MPC8536) u32 gencfgr; /* General Configuration Register */ #define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000 #else u32 gpiocr; /* GPIO control */ #endif u8 res3[12]; -#if defined(CONFIG_MPC8569) +#if defined(CONFIG_ARCH_MPC8569) u32 plppar1; /* Platform port pin assignment 1 */ u32 plppar2; /* Platform port pin assignment 2 */ u32 plpdir1; /* Platform port pin direction 1 */ @@ -2222,7 +2220,7 @@ typedef struct ccsr_gur { u32 gpindr; /* General-purpose input data */ u8 res5[12]; u32 pmuxcr; /* Alt. function signal multiplex control */ -#if defined(CONFIG_P1010) || defined(CONFIG_P1014) +#if defined(CONFIG_ARCH_P1010) #define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000 #define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000 #define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000 @@ -2268,7 +2266,7 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_CAN2_TDM 0x00000002 #define MPC85xx_PMUXCR_CAN2_RES 0x00000003 #endif -#if defined(CONFIG_P1017) || defined(CONFIG_P1023) +#if defined(CONFIG_ARCH_P1023) #define MPC85xx_PMUXCR_TSEC1_1 0x10000000 #else #define MPC85xx_PMUXCR_SD_DATA 0x80000000 @@ -2290,13 +2288,13 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_QE11 0x00000010 #define MPC85xx_PMUXCR_QE12 0x00000008 #endif -#if defined(CONFIG_P1013) || defined(CONFIG_P1022) +#if defined(CONFIG_ARCH_P1022) #define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00 #define MPC85xx_PMUXCR_TDM 0x00014800 #define MPC85xx_PMUXCR_SPI_MASK 0x00600000 #define MPC85xx_PMUXCR_SPI 0x00000000 #endif -#if defined(CONFIG_BSC9131) +#if defined(CONFIG_ARCH_BSC9131) #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000 #define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000 #define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000 @@ -2340,17 +2338,17 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002 #define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003 #endif -#ifdef CONFIG_BSC9132 +#ifdef CONFIG_ARCH_BSC9132 #define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000 #define MPC85xx_PMUXCR0_SIM_SEL 0x00014000 #endif -#if defined(CONFIG_PPC_C29X) +#if defined(CONFIG_ARCH_C29X) #define MPC85xx_PMUXCR_SPI_MASK 0x00000300 #define MPC85xx_PMUXCR_SPI 0x00000000 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000100 #endif u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ -#if defined(CONFIG_P1010) || defined(CONFIG_P1014) +#if defined(CONFIG_ARCH_P1010) #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000 #define MPC85xx_PMUXCR2_UART_TDM 0x80000000 #define MPC85xx_PMUXCR2_UART_RES 0xC0000000 @@ -2375,12 +2373,12 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000 #endif -#if defined(CONFIG_P1013) || defined(CONFIG_P1022) +#if defined(CONFIG_ARCH_P1022) #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000 #define MPC85xx_PMUXCR2_USB 0x00150000 #endif -#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132) -#if defined(CONFIG_BSC9131) +#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) +#if defined(CONFIG_ARCH_BSC9131) #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000 #define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000 #define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000 @@ -2425,7 +2423,7 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002 #endif u32 pmuxcr3; -#if defined(CONFIG_BSC9131) +#if defined(CONFIG_ARCH_BSC9131) #define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000 #define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000 #define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000 @@ -2441,7 +2439,7 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000 #define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000 #endif -#ifdef CONFIG_BSC9132 +#ifdef CONFIG_ARCH_BSC9132 #define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00 #define MPC85xx_PMUXCR3_UART2_SEL 0x00005000 #define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000 @@ -2484,11 +2482,11 @@ typedef struct ccsr_gur { u32 svr; /* System version */ u8 res10[8]; u32 rstcr; /* Reset control */ -#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569) +#if defined(CONFIG_ARCH_MPC8568) || defined(CONFIG_ARCH_MPC8569) u8 res11a[76]; par_io_t qe_par_io[7]; u8 res11b[1600]; -#elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) +#elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) u8 res11a[12]; u32 iovselsr; u8 res11b[60]; @@ -2504,7 +2502,7 @@ typedef struct ccsr_gur { u32 ddrdllcr; /* DDR DLL control */ u8 res14[12]; u32 lbcdllcr; /* LBC DLL control */ -#if defined(CONFIG_BSC9131) +#if defined(CONFIG_ARCH_BSC9131) u8 res15[12]; u32 halt_req_mask; #define HALTED_TO_HALT_REQ_MASK_0 0x80000000 @@ -2883,8 +2881,8 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000 #define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 -#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\ - && !defined(CONFIG_PPC_B4420) +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \ + !defined(CONFIG_ARCH_B4420) #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000 @@ -2940,7 +2938,7 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000 -#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) +#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020) #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000 #else #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000 @@ -2964,7 +2962,7 @@ struct ccsr_pman { #endif #define CONFIG_SYS_MDIO1_OFFSET 0x24000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 -#if defined(CONFIG_PPC_C29X) +#if defined(CONFIG_ARCH_C29X) #define CONFIG_SYS_FSL_SEC_OFFSET 0x80000 #define CONFIG_SYS_FSL_JR0_OFFSET 0x81000 #else @@ -2988,7 +2986,7 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000 -#if defined(CONFIG_BSC9132) +#if defined(CONFIG_ARCH_BSC9132) #define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \ (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET) diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h index b078569c45..1fbc63a5ce 100644 --- a/arch/powerpc/include/asm/immap_86xx.h +++ b/arch/powerpc/include/asm/immap_86xx.h @@ -1195,7 +1195,7 @@ extern immap_t *immr; #define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000 -#ifdef CONFIG_MPC8610 +#ifdef CONFIG_ARCH_MPC8610 #define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0xa000 #else #define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0x8000 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index fdfca9086f..fbf72bb7c6 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1048,7 +1048,7 @@ #define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ #define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ -#ifdef CONFIG_MPC8536 +#ifdef CONFIG_ARCH_MPC8536 #define SVR_MAJ(svr) (((svr) >> 4) & 0x7) /* Major revision field*/ #else #define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ diff --git a/board/freescale/b4860qds/Kconfig b/board/freescale/b4860qds/Kconfig index c7aab7521b..01d68e14e2 100644 --- a/board/freescale/b4860qds/Kconfig +++ b/board/freescale/b4860qds/Kconfig @@ -1,4 +1,4 @@ -if TARGET_B4860QDS +if TARGET_B4860QDS || TARGET_B4420QDS config SYS_BOARD default "b4860qds" diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile index 673d2ea56a..c032242f22 100644 --- a/board/freescale/b4860qds/Makefile +++ b/board/freescale/b4860qds/Makefile @@ -8,7 +8,8 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else obj-y += b4860qds.o -obj-$(CONFIG_B4860QDS) += eth_b4860qds.o +obj-$(CONFIG_TARGET_B4860QDS) += eth_b4860qds.o +obj-$(CONFIG_TARGET_B4420QDS) += eth_b4860qds.o obj-$(CONFIG_PCI) += pci.o endif diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index c2ceb8014e..83a70153e8 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -437,7 +437,7 @@ int configure_vsc3316_3308(void) } break; -#ifdef CONFIG_PPC_B4420 +#ifdef CONFIG_ARCH_B4420 case 0x17: case 0x18: /* @@ -496,7 +496,7 @@ int configure_vsc3316_3308(void) /* Configure VSC3308 crossbar switch */ ret = select_i2c_ch_pca(I2C_CH_VSC3308); switch (serdes2_prtcl) { -#ifdef CONFIG_PPC_B4420 +#ifdef CONFIG_ARCH_B4420 case 0x9d: #endif case 0x9E: @@ -929,7 +929,7 @@ int config_serdes2_refclks(void) * For this SerDes2's Refclk1 need to be set to 100MHz */ switch (serdes2_prtcl) { -#ifdef CONFIG_PPC_B4420 +#ifdef CONFIG_ARCH_B4420 case 0x9d: #endif case 0x9E: diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h index fcccb8f9b3..901f8b0039 100644 --- a/board/freescale/b4860qds/b4860qds_crossbar_con.h +++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h @@ -28,7 +28,7 @@ static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0}, {5, 14}, {4, 15}, {2, 12}, {12, 13} }; -#ifdef CONFIG_PPC_B4420 +#ifdef CONFIG_ARCH_B4420 static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; #endif @@ -54,7 +54,7 @@ static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9}, {14, 11}, {15, 10}, {13, 3}, {12, 12} }; -#ifdef CONFIG_PPC_B4420 +#ifdef CONFIG_ARCH_B4420 static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; #endif diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c index 164ec0a47b..89a1883782 100644 --- a/board/freescale/b4860qds/eth_b4860qds.c +++ b/board/freescale/b4860qds/eth_b4860qds.c @@ -213,7 +213,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); break; -#ifdef CONFIG_PPC_B4420 +#ifdef CONFIG_ARCH_B4420 case 0x17: case 0x18: /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */ diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index be114cebef..e9419492bc 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -45,18 +45,18 @@ endif obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o -obj-$(CONFIG_MPC8541CDS) += cds_pci_ft.o -obj-$(CONFIG_MPC8548CDS) += cds_pci_ft.o -obj-$(CONFIG_MPC8555CDS) += cds_pci_ft.o +obj-$(CONFIG_TARGET_MPC8541CDS) += cds_pci_ft.o +obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o +obj-$(CONFIG_TARGET_MPC8555CDS) += cds_pci_ft.o -obj-$(CONFIG_MPC8536DS) += ics307_clk.o -obj-$(CONFIG_MPC8572DS) += ics307_clk.o -obj-$(CONFIG_P1022DS) += ics307_clk.o +obj-$(CONFIG_TARGET_MPC8536DS) += ics307_clk.o +obj-$(CONFIG_TARGET_MPC8572DS) += ics307_clk.o +obj-$(CONFIG_TARGET_P1022DS) += ics307_clk.o obj-$(CONFIG_P2020DS) += ics307_clk.o -obj-$(CONFIG_P3041DS) += ics307_clk.o -obj-$(CONFIG_P4080DS) += ics307_clk.o -obj-$(CONFIG_P5020DS) += ics307_clk.o -obj-$(CONFIG_P5040DS) += ics307_clk.o +obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o +obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o +obj-$(CONFIG_TARGET_P5020DS) += ics307_clk.o +obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o obj-$(CONFIG_ZM7300) += zm7300.o @@ -65,11 +65,11 @@ obj-$(CONFIG_POWER_PFUZE100) += pfuze.o obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o # deal with common files for P-series corenet based devices -obj-$(CONFIG_P2041RDB) += p_corenet/ -obj-$(CONFIG_P3041DS) += p_corenet/ -obj-$(CONFIG_P4080DS) += p_corenet/ -obj-$(CONFIG_P5020DS) += p_corenet/ -obj-$(CONFIG_P5040DS) += p_corenet/ +obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/ +obj-$(CONFIG_TARGET_P3041DS) += p_corenet/ +obj-$(CONFIG_TARGET_P4080DS) += p_corenet/ +obj-$(CONFIG_TARGET_P5020DS) += p_corenet/ +obj-$(CONFIG_TARGET_P5040DS) += p_corenet/ obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o diff --git a/board/freescale/common/pixis.h b/board/freescale/common/pixis.h index 9328404ff2..e6e0f66fe3 100644 --- a/board/freescale/common/pixis.h +++ b/board/freescale/common/pixis.h @@ -7,7 +7,7 @@ #define __PIXIS_H_ 1 /* PIXIS register set. */ -#if defined(CONFIG_MPC8536DS) +#if defined(CONFIG_TARGET_MPC8536DS) typedef struct pixis { u8 id; u8 ver; @@ -46,7 +46,7 @@ typedef struct pixis { u8 res2[4]; } __attribute__ ((packed)) pixis_t; -#elif defined(CONFIG_MPC8544DS) +#elif defined(CONFIG_TARGET_MPC8544DS) typedef struct pixis { u8 id; u8 ver; @@ -73,7 +73,7 @@ typedef struct pixis { u8 res2[34]; } __attribute__ ((packed)) pixis_t; -#elif defined(CONFIG_MPC8572DS) +#elif defined(CONFIG_TARGET_MPC8572DS) typedef struct pixis { u8 id; u8 ver; @@ -102,7 +102,7 @@ typedef struct pixis { u8 res4[25]; } __attribute__ ((packed)) pixis_t; -#elif defined(CONFIG_MPC8610HPCD) +#elif defined(CONFIG_TARGET_MPC8610HPCD) typedef struct pixis { u8 id; u8 ver; /* also called arch */ @@ -132,7 +132,7 @@ typedef struct pixis { u8 res4[33]; } __attribute__ ((packed)) pixis_t; -#elif defined(CONFIG_MPC8641HPCN) +#elif defined(CONFIG_TARGET_MPC8641HPCN) typedef struct pixis { u8 id; u8 ver; diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c index 1eb37866e3..d152a7821f 100644 --- a/board/freescale/common/pq-mds-pib.c +++ b/board/freescale/common/pq-mds-pib.c @@ -63,7 +63,7 @@ int pib_init(void) #endif #if defined(CONFIG_PQ_MDS_PIB_ATM) -#if defined(CONFIG_MPC8569MDS) +#if defined(CONFIG_TARGET_MPC8569MDS) val8 = 0; i2c_write(0x20, 0x6, 1, &val8, 1); i2c_write(0x20, 0x7, 1, &val8, 1); diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile index 9ade9472ea..100ba926cf 100644 --- a/board/freescale/corenet_ds/Makefile +++ b/board/freescale/corenet_ds/Makefile @@ -8,11 +8,11 @@ obj-y += corenet_ds.o obj-y += ddr.o -obj-$(CONFIG_P3041DS) += eth_hydra.o -obj-$(CONFIG_P4080DS) += eth_p4080.o -obj-$(CONFIG_P5020DS) += eth_hydra.o -obj-$(CONFIG_P5040DS) += eth_superhydra.o -obj-$(CONFIG_P3041DS) += p3041ds_ddr.o -obj-$(CONFIG_P4080DS) += p4080ds_ddr.o -obj-$(CONFIG_P5020DS) += p5020ds_ddr.o -obj-$(CONFIG_P5040DS) += p5040ds_ddr.o +obj-$(CONFIG_TARGET_P3041DS) += eth_hydra.o +obj-$(CONFIG_TARGET_P4080DS) += eth_p4080.o +obj-$(CONFIG_TARGET_P5020DS) += eth_hydra.o +obj-$(CONFIG_TARGET_P5040DS) += eth_superhydra.o +obj-$(CONFIG_TARGET_P3041DS) += p3041ds_ddr.o +obj-$(CONFIG_TARGET_P4080DS) += p4080ds_ddr.o +obj-$(CONFIG_TARGET_P5020DS) += p5020ds_ddr.o +obj-$(CONFIG_TARGET_P5040DS) += p5040ds_ddr.o diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 8a44a9a972..93e1258295 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -26,8 +26,8 @@ int checkboard (void) { u8 sw; struct cpu_type *cpu = gd->arch.cpu; -#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) || \ - defined(CONFIG_P5040DS) +#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ + defined(CONFIG_TARGET_P5040DS) unsigned int i; #endif static const char * const freq[] = {"100", "125", "156.25", "212.5" }; @@ -56,15 +56,15 @@ int checkboard (void) * don't match. */ puts("SERDES Reference Clocks: "); -#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ - || defined(CONFIG_P5040DS) +#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ + defined(CONFIG_TARGET_P5040DS) sw = in_8(&PIXIS_SW(5)); for (i = 0; i < 3; i++) { unsigned int clock = (sw >> (6 - (2 * i))) & 3; printf("Bank%u=%sMhz ", i+1, freq[clock]); } -#ifdef CONFIG_P5040DS +#ifdef CONFIG_TARGET_P5040DS /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */ sw = in_8(&PIXIS_SW(9)); printf("Bank4=%sMhz ", freq[sw & 3]); @@ -136,8 +136,8 @@ int misc_init_r(void) unsigned int i; u8 sw; -#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ - || defined(CONFIG_P5040DS) +#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ + defined(CONFIG_TARGET_P5040DS) sw = in_8(&PIXIS_SW(5)); for (i = 0; i < 3; i++) { unsigned int clock = (sw >> (6 - (2 * i))) & 3; diff --git a/board/freescale/p1010rdb/Kconfig b/board/freescale/p1010rdb/Kconfig index b0a7a8d9df..159bcc4f54 100644 --- a/board/freescale/p1010rdb/Kconfig +++ b/board/freescale/p1010rdb/Kconfig @@ -1,4 +1,4 @@ -if TARGET_P1010RDB +if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB config SYS_BOARD default "p1010rdb" diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 8eecb0647b..65bb575a96 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -54,7 +54,7 @@ static uint sd_ifc_mux; struct cpld_data { u8 cpld_ver; /* cpld revision */ -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) u8 pcba_ver; /* pcb revision number */ u8 twindie_ddr3; u8 res1[6]; @@ -69,7 +69,7 @@ struct cpld_data { u8 por1; /* POR Options */ u8 por2; /* POR Options */ u8 por3; /* POR Options */ -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) u8 rom_loc; #endif }; @@ -135,7 +135,7 @@ int config_board_mux(int ctrl_type) ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u8 tmp; -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); switch (ctrl_type) { @@ -171,7 +171,7 @@ int config_board_mux(int ctrl_type) default: break; } -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) uint orig_bus = i2c_get_bus_num(); i2c_set_bus_num(I2C_PCA9557_BUS_NUM); @@ -245,7 +245,7 @@ int config_board_mux(int ctrl_type) return 0; } -#ifdef CONFIG_P1010RDB_PB +#ifdef CONFIG_TARGET_P1010RDB_PB int i2c_pca9557_read(int type) { u8 val; @@ -275,9 +275,9 @@ int checkboard(void) u8 val; cpu = gd->arch.cpu; -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) printf("Board: %sRDB-PA, ", cpu->name); -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) printf("Board: %sRDB-PB, ", cpu->name); i2c_set_bus_num(I2C_PCA9557_BUS_NUM); i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE); @@ -290,10 +290,10 @@ int checkboard(void) config_board_mux(MUX_TYPE_IFC); #endif -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) val = (in_8(&cpld_data->pcba_ver) & 0xf); printf("PCB: v%x.0\n", val); -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) val = in_8(&cpld_data->cpld_ver); printf("CPLD: v%x.%x, ", val >> 4, val & 0xf); printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER)); @@ -544,7 +544,7 @@ int misc_init_r(void) else if (hwconfig("ifc")) config_board_mux(MUX_TYPE_IFC); -#ifdef CONFIG_P1010RDB_PB +#ifdef CONFIG_TARGET_P1010RDB_PB setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); #endif return 0; diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c index 9844194eb5..c22e215675 100644 --- a/board/freescale/p1010rdb/spl.c +++ b/board/freescale/p1010rdb/spl.c @@ -32,7 +32,7 @@ void board_init_f(ulong bootflag) /* Clock configuration to access CPLD using IFC(GPCM) */ setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); -#ifdef CONFIG_P1010RDB_PB +#ifdef CONFIG_TARGET_P1010RDB_PB setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); #endif diff --git a/board/freescale/p1_p2_rdb_pc/Kconfig b/board/freescale/p1_p2_rdb_pc/Kconfig index d3352d2856..2f9640b67c 100644 --- a/board/freescale/p1_p2_rdb_pc/Kconfig +++ b/board/freescale/p1_p2_rdb_pc/Kconfig @@ -1,4 +1,11 @@ -if TARGET_P1_P2_RDB_PC +if TARGET_P1020MBG || \ + TARGET_P1020RDB_PC || \ + TARGET_P1020RDB_PD || \ + TARGET_P1020UTM || \ + TARGET_P1021RDB || \ + TARGET_P1024RDB || \ + TARGET_P1025RDB || \ + TARGET_P2020RDB config SYS_BOARD default "p1_p2_rdb_pc" diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 1f3793b853..fc38326138 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -15,8 +15,8 @@ #ifdef CONFIG_SYS_DDR_RAW_TIMING #if defined(CONFIG_P1020RDB_PROTO) || \ - defined(CONFIG_P1021RDB) || \ - defined(CONFIG_P1020UTM) + defined(CONFIG_TARGET_P1021RDB) || \ + defined(CONFIG_TARGET_P1020UTM) /* Micron MT41J256M8_187E */ dimm_params_t ddr_raw_timing = { .n_ranks = 1, @@ -47,7 +47,7 @@ dimm_params_t ddr_raw_timing = { .refresh_rate_ps = 7800000, .tfaw_ps = 37500, }; -#elif defined(CONFIG_P2020RDB) +#elif defined(CONFIG_TARGET_P2020RDB) /* Micron MT41J128M16_15E */ dimm_params_t ddr_raw_timing = { .n_ranks = 1, @@ -78,7 +78,7 @@ dimm_params_t ddr_raw_timing = { .refresh_rate_ps = 7800000, .tfaw_ps = 30000, }; -#elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) +#elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) /* Micron MT41J512M8_187E */ dimm_params_t ddr_raw_timing = { .n_ranks = 2, @@ -109,7 +109,7 @@ dimm_params_t ddr_raw_timing = { .refresh_rate_ps = 7800000, .tfaw_ps = 37500, }; -#elif defined(CONFIG_P1020RDB_PC) +#elif defined(CONFIG_TARGET_P1020RDB_PC) /* * Samsung K4B2G0846C-HCF8 * The following timing are for "downshift" @@ -146,8 +146,8 @@ dimm_params_t ddr_raw_timing = { .refresh_rate_ps = 7800000, .tfaw_ps = 37500, }; -#elif defined(CONFIG_P1024RDB) || \ - defined(CONFIG_P1025RDB) +#elif defined(CONFIG_TARGET_P1024RDB) || \ + defined(CONFIG_TARGET_P1025RDB) /* * Samsung K4B2G0846C-HCH9 * The following timing are for "downshift" diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index d61c3a5413..51217c58e5 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -39,7 +39,7 @@ #define GPIO_SLIC_PIN 30 #define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN)) -#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) #define GPIO_DDR_RST_PORT 1 #define GPIO_DDR_RST_PIN 8 #define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN)) @@ -47,7 +47,7 @@ #define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2)) #endif -#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB) +#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB) #define PCA_IOPORT_I2C_ADDR 0x23 #define PCA_IOPORT_OUTPUT_CMD 0x2 #define PCA_IOPORT_CFG_CMD 0x6 @@ -58,14 +58,14 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { /* GPIO */ {1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */ -#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) {1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */ #endif {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */ {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */ {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */ -#ifdef CONFIG_P1025RDB +#ifdef CONFIG_TARGET_P1025RDB /* QE_MUX_MDC */ {1, 19, 1, 0, 1}, /* QE_MUX_MDC */ @@ -150,7 +150,7 @@ void board_gpio_init(void) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); par_io_t *par_io = (par_io_t *) &(gur->qe_par_io); -#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) /* reset DDR3 */ setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA); udelay(1000); @@ -379,7 +379,7 @@ int board_eth_init(bd_t *bis) } #if defined(CONFIG_QE) && \ - (defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)) + (defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)) static void fdt_board_fixup_qe_pins(void *blob) { unsigned int oldbus; @@ -428,7 +428,7 @@ int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; -#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC) +#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC) const char *soc_usb_compat = "fsl-usb2-dr"; int usb_err, usb1_off, usb2_off; #endif @@ -448,7 +448,7 @@ int ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_QE do_fixup_by_compat(blob, "fsl,qe", "status", "okay", sizeof("okay"), 0); -#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB) +#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB) fdt_board_fixup_qe_pins(blob); #endif #endif @@ -478,7 +478,7 @@ int ft_board_setup(void *blob, bd_t *bd) } #endif -#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC) +#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC) /* Delete USB2 node as it is muxed with eLBC */ usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat); diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 1c0008b2e6..7cba411007 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -85,13 +85,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 8, BOOKE_PAGESZ_1G, 1), -#if defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD) /* 2G DDR on P1020MBG, map the second 1G */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_1G, 1), -#endif /* P1020MBG */ +#endif /* TARGET_P1020MBG */ #endif /* RAMBOOT/SPL */ #ifdef CONFIG_SYS_INIT_L2_ADDR diff --git a/board/freescale/t102xqds/Kconfig b/board/freescale/t102xqds/Kconfig index 4d17798d5c..6ee7468b21 100644 --- a/board/freescale/t102xqds/Kconfig +++ b/board/freescale/t102xqds/Kconfig @@ -1,4 +1,4 @@ -if TARGET_T102XQDS +if TARGET_T1024QDS config SYS_BOARD default "t102xqds" diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c index 61bfb295ef..c9239b87db 100644 --- a/board/freescale/t102xqds/spl.c +++ b/board/freescale/t102xqds/spl.c @@ -66,7 +66,7 @@ void board_init_f(ulong bootflag) u32 plat_ratio, sys_clk, ccb_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; -#if defined(CONFIG_PPC_T1040) && defined(CONFIG_SPL_NAND_BOOT) +#if defined(CONFIG_ARCH_T1040) && defined(CONFIG_SPL_NAND_BOOT) /* * There is T1040 SoC issue where NOR, FPGA are inaccessible during * NAND boot because IFC signals > IFC_AD7 are not enabled. diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c index 1affa0b3a8..1b2f6b2487 100644 --- a/board/freescale/t102xqds/t102xqds.c +++ b/board/freescale/t102xqds/t102xqds.c @@ -152,7 +152,7 @@ static int board_mux_lane_to_slot(void) return 0; } -#ifdef CONFIG_PPC_T1024 +#ifdef CONFIG_ARCH_T1024 static void board_mux_setup(void) { u8 brdcfg15; @@ -332,7 +332,7 @@ unsigned long get_board_ddr_clk(void) #define NUM_SRDS_PLL 2 int misc_init_r(void) { -#ifdef CONFIG_PPC_T1024 +#ifdef CONFIG_ARCH_T1024 board_mux_setup(); #endif return 0; diff --git a/board/freescale/t102xrdb/Kconfig b/board/freescale/t102xrdb/Kconfig index 10d49f5831..d538386d43 100644 --- a/board/freescale/t102xrdb/Kconfig +++ b/board/freescale/t102xrdb/Kconfig @@ -1,4 +1,4 @@ -if TARGET_T102XRDB +if TARGET_T1023RDB || TARGET_T1024RDB config SYS_BOARD default "t102xrdb" diff --git a/board/freescale/t104xrdb/Kconfig b/board/freescale/t104xrdb/Kconfig index f28728d33d..e33d317365 100644 --- a/board/freescale/t104xrdb/Kconfig +++ b/board/freescale/t104xrdb/Kconfig @@ -1,4 +1,6 @@ -if TARGET_T104XRDB +if TARGET_T1040RDB || TARGET_T1040D4RDB || \ + TARGET_T1042RDB || TARGET_T1042D4RDB || \ + TARGET_T1042RDB_PI config SYS_BOARD default "t104xrdb" diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c index 0ce4e470a7..95ff6a70d8 100644 --- a/board/freescale/t104xrdb/cpld.c +++ b/board/freescale/t104xrdb/cpld.c @@ -69,7 +69,7 @@ static void cpld_dump_regs(void) printf("int_status = 0x%02x\n", CPLD_READ(int_status)); printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status)); printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status)); -#if defined(CONFIG_T104XD4RDB) +#if defined(CONFIG_TARGET_T1040D4D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); #else printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status)); diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h index 86de26cc9d..7adf5e4c3d 100644 --- a/board/freescale/t104xrdb/cpld.h +++ b/board/freescale/t104xrdb/cpld.h @@ -21,7 +21,7 @@ struct cpld_data { u8 int_status; /* 0x12 - Interrupt status Register */ u8 flash_ctl_status; /* 0x13 - Flash control and status register */ u8 fan_ctl_status; /* 0x14 - Fan control and status register */ -#if defined(CONFIG_T104XD4RDB) +#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) u8 int_mask; /* 0x15 - Interrupt mask Register */ #else u8 led_ctl_status; /* 0x15 - LED control and status register */ diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index 52cd112249..ab8c8bb2aa 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -43,7 +43,7 @@ int board_eth_init(bd_t *bis) int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) +#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) case PHY_INTERFACE_MODE_SGMII: /* T1040RDB & T1040D4RDB only supports SGMII on * DTSEC3 @@ -52,7 +52,7 @@ int board_eth_init(bd_t *bis) CONFIG_SYS_SGMII1_PHY_ADDR); break; #endif -#ifdef CONFIG_T1042RDB +#ifdef CONFIG_TARGET_T1042RDB case PHY_INTERFACE_MODE_SGMII: /* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */ if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i)) @@ -62,7 +62,7 @@ int board_eth_init(bd_t *bis) CONFIG_SYS_SGMII1_PHY_ADDR); break; #endif -#ifdef CONFIG_T1042D4RDB +#ifdef CONFIG_TARGET_T1042D4RDB case PHY_INTERFACE_MODE_SGMII: /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2 * & DTSEC3 diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 6bad6a4540..d4c3d4dcb4 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -29,7 +29,7 @@ int checkboard(void) struct cpu_type *cpu = gd->arch.cpu; u8 sw; -#ifdef CONFIG_T104XD4RDB +#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) printf("Board: %sD4RDB\n", cpu->name); #else printf("Board: %sRDB\n", cpu->name); @@ -105,7 +105,7 @@ int misc_init_r(void) CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL); -#if defined(CONFIG_T1040D4RDB) +#if defined(CONFIG_TARGET_T1040D4RDB) if (hwconfig("qe-tdm")) { CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) | MISC_MUX_QE_TDM); diff --git a/board/freescale/t208xqds/Kconfig b/board/freescale/t208xqds/Kconfig index 4e329dddf3..26ef530b93 100644 --- a/board/freescale/t208xqds/Kconfig +++ b/board/freescale/t208xqds/Kconfig @@ -1,4 +1,4 @@ -if TARGET_T208XQDS +if TARGET_T2080QDS || TARGET_T2081QDS config SYS_BOARD default "t208xqds" diff --git a/board/freescale/t208xrdb/Kconfig b/board/freescale/t208xrdb/Kconfig index 845af3dd2f..71e11303ba 100644 --- a/board/freescale/t208xrdb/Kconfig +++ b/board/freescale/t208xrdb/Kconfig @@ -1,4 +1,4 @@ -if TARGET_T208XRDB +if TARGET_T2080RDB config SYS_BOARD default "t208xrdb" diff --git a/board/freescale/t4qds/Kconfig b/board/freescale/t4qds/Kconfig index 27a64b64b9..563a87c456 100644 --- a/board/freescale/t4qds/Kconfig +++ b/board/freescale/t4qds/Kconfig @@ -1,4 +1,4 @@ -if TARGET_T4240QDS +if TARGET_T4160QDS || TARGET_T4240QDS config SYS_BOARD default "t4qds" diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile index 731ccb0b29..1eacbcc016 100644 --- a/board/freescale/t4qds/Makefile +++ b/board/freescale/t4qds/Makefile @@ -7,7 +7,8 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else -obj-$(CONFIG_T4240QDS) += t4240qds.o eth.o +obj-$(CONFIG_TARGET_T4160QDS) += t4240qds.o eth.o +obj-$(CONFIG_TARGET_T4240QDS) += t4240qds.o eth.o obj-$(CONFIG_PCI) += pci.o endif diff --git a/board/freescale/t4rdb/Kconfig b/board/freescale/t4rdb/Kconfig index d93e4532ac..67832da30b 100644 --- a/board/freescale/t4rdb/Kconfig +++ b/board/freescale/t4rdb/Kconfig @@ -1,4 +1,4 @@ -if TARGET_T4240RDB +if TARGET_T4160RDB || TARGET_T4240RDB config SYS_BOARD default "t4rdb" diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile index 4f29eea0f4..209983a24b 100644 --- a/board/freescale/t4rdb/Makefile +++ b/board/freescale/t4rdb/Makefile @@ -7,7 +7,8 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else -obj-$(CONFIG_T4240RDB) += t4240rdb.o +obj-$(CONFIG_TARGET_T4160RDB) += t4240rdb.o +obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o obj-y += cpld.o obj-y += eth.o obj-$(CONFIG_PCI) += pci.o diff --git a/board/varisys/cyrus/eth.c b/board/varisys/cyrus/eth.c index bcadc67794..fc2192a4d2 100644 --- a/board/varisys/cyrus/eth.c +++ b/board/varisys/cyrus/eth.c @@ -19,7 +19,7 @@ #define FIRST_PORT_ADDR 3 #define SECOND_PORT_ADDR 7 -#ifdef CONFIG_PPC_P5040 +#ifdef CONFIG_ARCH_P5040 #define FIRST_PORT FM1_DTSEC5 #define SECOND_PORT FM2_DTSEC5 #else @@ -83,7 +83,7 @@ int board_eth_init(bd_t *bis) fm_disable_port(i); } -#ifdef CONFIG_PPC_P5040 +#ifdef CONFIG_ARCH_P5040 for (i = FM2_DTSEC2; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { if (!IS_VALID_PORT(i)) fm_disable_port(i); diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile index 65d321abdd..db1f029f96 100644 --- a/board/xes/common/Makefile +++ b/board/xes/common/Makefile @@ -6,9 +6,9 @@ # obj-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o -obj-$(CONFIG_MPC8572) += fsl_8xxx_clk.o +obj-$(CONFIG_ARCH_MPC8572) += fsl_8xxx_clk.o obj-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o -obj-$(CONFIG_P2020) += fsl_8xxx_clk.o +obj-$(CONFIG_ARCH_P2020) += fsl_8xxx_clk.o obj-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o obj-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o obj-$(CONFIG_NAND_ACTL) += actl_nand.o diff --git a/board/xes/common/fsl_8xxx_clk.c b/board/xes/common/fsl_8xxx_clk.c index 2a604d448b..e102b0cfc3 100644 --- a/board/xes/common/fsl_8xxx_clk.c +++ b/board/xes/common/fsl_8xxx_clk.c @@ -22,7 +22,7 @@ unsigned long get_board_sys_clk(ulong dummy) if (in_be32(&gur->gpporcr) & 0x10000) return 66666666; else -#ifdef CONFIG_P2020 +#ifdef CONFIG_ARCH_P2020 return 100000000; #else return 50000000; @@ -42,7 +42,7 @@ unsigned long get_board_ddr_clk(ulong dummy) if (ddr_ratio == 0x7) return get_board_sys_clk(dummy); -#ifdef CONFIG_P2020 +#ifdef CONFIG_ARCH_P2020 if (in_be32(&gur->gpporcr) & 0x20000) return 66666666; else diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c index 510f638ffe..62375717f0 100644 --- a/board/xes/common/fsl_8xxx_pci.c +++ b/board/xes/common/fsl_8xxx_pci.c @@ -55,7 +55,7 @@ void pci_init_board(void) } else { printf("PCI1: disabled\n"); } -#elif defined CONFIG_MPC8548 +#elif defined CONFIG_ARCH_MPC8548 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); /* PCI1 not present on MPC8572 */ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); diff --git a/common/env_embedded.c b/common/env_embedded.c index 56a13cb882..b368fdaa80 100644 --- a/common/env_embedded.c +++ b/common/env_embedded.c @@ -5,6 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <linux/kconfig.h> + #ifndef __ASSEMBLY__ #define __ASSEMBLY__ /* Dirty trick to get only #defines */ #endif diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig index d3cf28662c..dc5f5e36ab 100644 --- a/configs/B4420QDS_NAND_defconfig +++ b/configs/B4420QDS_NAND_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_B4860QDS=y +CONFIG_TARGET_B4420QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/B4420QDS_SPIFLASH_defconfig b/configs/B4420QDS_SPIFLASH_defconfig index 2dd25fee4e..fcf683d13c 100644 --- a/configs/B4420QDS_SPIFLASH_defconfig +++ b/configs/B4420QDS_SPIFLASH_defconfig @@ -1,11 +1,11 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_B4860QDS=y +CONFIG_TARGET_B4420QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/B4420QDS_defconfig b/configs/B4420QDS_defconfig index 406241a7c2..6c3c5ab914 100644 --- a/configs/B4420QDS_defconfig +++ b/configs/B4420QDS_defconfig @@ -1,11 +1,10 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_B4860QDS=y +CONFIG_TARGET_B4420QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig index 00fe1826fb..28ffcb6eb6 100644 --- a/configs/B4860QDS_NAND_defconfig +++ b/configs/B4860QDS_NAND_defconfig @@ -12,7 +12,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig index 292354742e..53c122ca9a 100644 --- a/configs/B4860QDS_SECURE_BOOT_defconfig +++ b/configs/B4860QDS_SECURE_BOOT_defconfig @@ -6,7 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/B4860QDS_SPIFLASH_defconfig b/configs/B4860QDS_SPIFLASH_defconfig index 80e729eb4d..94a07fa2cf 100644 --- a/configs/B4860QDS_SPIFLASH_defconfig +++ b/configs/B4860QDS_SPIFLASH_defconfig @@ -5,7 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig index 09c8a5b3fa..cb3e134077 100644 --- a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig @@ -5,7 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/B4860QDS_defconfig b/configs/B4860QDS_defconfig index 31f64abc86..077ffd248c 100644 --- a/configs/B4860QDS_defconfig +++ b/configs/B4860QDS_defconfig @@ -5,7 +5,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig index 484baf8b34..e88e2340d1 100644 --- a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig +++ b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig @@ -7,7 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND,SYS_CLK_100" +CONFIG_SYS_EXTRA_OPTIONS="NAND,SYS_CLK_100" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/BSC9131RDB_NAND_defconfig b/configs/BSC9131RDB_NAND_defconfig index ad24afa1b5..5c4d45d9e7 100644 --- a/configs/BSC9131RDB_NAND_defconfig +++ b/configs/BSC9131RDB_NAND_defconfig @@ -7,7 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND" +CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig index 4904da45fa..23a74c333f 100644 --- a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig +++ b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig @@ -5,7 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH,SYS_CLK_100" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/BSC9131RDB_SPIFLASH_defconfig b/configs/BSC9131RDB_SPIFLASH_defconfig index 47b4486e6d..2c5d637a67 100644 --- a/configs/BSC9131RDB_SPIFLASH_defconfig +++ b/configs/BSC9131RDB_SPIFLASH_defconfig @@ -5,7 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig index 8ebd0da982..a8fa5ab4ac 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig @@ -6,7 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig index cb3b0ee556..dde8fdb2e7 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig @@ -7,7 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_100" +CONFIG_SYS_EXTRA_OPTIONS="NAND,SYS_CLK_100_DDR_100" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig index aa4f4181ce..4d79281db3 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig @@ -6,7 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig index 29646d2752..e44aac38f1 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig @@ -7,7 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_133" +CONFIG_SYS_EXTRA_OPTIONS="NAND,SYS_CLK_100_DDR_133" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig index 6f3c5e59cf..2ad2c6ee26 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig @@ -6,7 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig index dc75009682..db14156eae 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig @@ -5,7 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100" +CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig index f9472156a6..e5ef6ad59c 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig @@ -6,7 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig index 190e2e7e9f..9076f0bdd1 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig @@ -5,7 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133" +CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig index 512a6754de..e90044a119 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig @@ -6,7 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig index 83b8deed62..caa7015bfe 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig @@ -5,7 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_100" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig index c92458e22d..19252c13dc 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig @@ -6,7 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig index 0a49a45ab3..1c42d906b3 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig @@ -5,7 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_133" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig index 1e90d68eab..d08dd8e131 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig @@ -6,7 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig index a6a814da8c..258862f8da 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig @@ -5,7 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_100" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig index 4ba0a15359..6519e2218c 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig @@ -6,7 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig index cbf0a59a8e..cc4e385689 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig @@ -5,7 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_133" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/C29XPCIE_NAND_defconfig b/configs/C29XPCIE_NAND_defconfig index c3cc168e00..9398844800 100644 --- a/configs/C29XPCIE_NAND_defconfig +++ b/configs/C29XPCIE_NAND_defconfig @@ -8,7 +8,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,NAND" +CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_BOOTDELAY=-1 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig index 15d89f13ac..2f1ed21d42 100644 --- a/configs/C29XPCIE_NOR_SECBOOT_defconfig +++ b/configs/C29XPCIE_NOR_SECBOOT_defconfig @@ -6,7 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_BOOTDELAY=-1 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig index 49799be24b..0c2c0b75c9 100644 --- a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig +++ b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig @@ -6,7 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,SPIFLASH,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SECURE_BOOT" CONFIG_BOOTDELAY=-1 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/C29XPCIE_SPIFLASH_defconfig b/configs/C29XPCIE_SPIFLASH_defconfig index 9f892638ce..43c88ee0e8 100644 --- a/configs/C29XPCIE_SPIFLASH_defconfig +++ b/configs/C29XPCIE_SPIFLASH_defconfig @@ -5,7 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_BOOTDELAY=-1 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/C29XPCIE_defconfig b/configs/C29XPCIE_defconfig index 83493d4773..c2b58d19df 100644 --- a/configs/C29XPCIE_defconfig +++ b/configs/C29XPCIE_defconfig @@ -5,7 +5,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE" CONFIG_BOOTDELAY=-1 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/Cyrus_P5020_defconfig b/configs/Cyrus_P5020_defconfig index 5eb5660243..94fc387e79 100644 --- a/configs/Cyrus_P5020_defconfig +++ b/configs/Cyrus_P5020_defconfig @@ -5,7 +5,7 @@ CONFIG_TARGET_CYRUS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5020" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,ARCH_P5020" CONFIG_BOOTDELAY=10 CONFIG_CONSOLE_MUX=y CONFIG_HUSH_PARSER=y diff --git a/configs/Cyrus_P5040_defconfig b/configs/Cyrus_P5040_defconfig index e33340bb2c..4b50772843 100644 --- a/configs/Cyrus_P5040_defconfig +++ b/configs/Cyrus_P5040_defconfig @@ -5,7 +5,7 @@ CONFIG_TARGET_CYRUS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5040" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,ARCH_P5040" CONFIG_BOOTDELAY=10 CONFIG_CONSOLE_MUX=y CONFIG_HUSH_PARSER=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig index 986dc7f66a..b07900ca0c 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig @@ -1,13 +1,13 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PA=y # CONFIG_SYS_MALLOC_F is not set CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index 7155011583..f769d58b44 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -3,13 +3,13 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PA=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND" +CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig index f687a84a2d..72df73742b 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig @@ -1,13 +1,13 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PA=y # CONFIG_SYS_MALLOC_F is not set CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index cf42d2fd5e..3b6f420227 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -1,12 +1,11 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PA=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index f3f0fca23b..45021e90b0 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -7,13 +7,13 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PA=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig index 94a1c220d7..7bab7f49e3 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig @@ -1,13 +1,13 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PA=y # CONFIG_SYS_MALLOC_F is not set CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index c56d9e3481..1d512de95f 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -8,13 +8,13 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PA=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig index df0cc7aa8c..28c33e5ed7 100644 --- a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PA=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index f6943a88d7..09a97ad8c8 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -3,12 +3,12 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PA=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND" +CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig index 50166ce804..319e40d77f 100644 --- a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PA=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index 6a6bcaffac..f7312f9bd8 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -1,11 +1,10 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PA=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 64959d7dae..d63f4d86f9 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PA=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig index a4073f6b3c..61a745a481 100644 --- a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PA=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index eea19e6795..ace10776d5 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -8,12 +8,12 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PA=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig index 3ac38393a3..868af101d9 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig @@ -1,13 +1,13 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PB=y # CONFIG_SYS_MALLOC_F is not set CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 406a58aa6d..b7e29e30b4 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -3,13 +3,13 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND" +CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig index a1375b3dab..bf0194e7ae 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig @@ -1,13 +1,13 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PB=y # CONFIG_SYS_MALLOC_F is not set CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index c95c28c268..091f578593 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -1,12 +1,11 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 38fbb1832f..089082d5d3 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -7,13 +7,13 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig index f201f13482..48d8dfcb9b 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig @@ -1,13 +1,13 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PB=y # CONFIG_SYS_MALLOC_F is not set CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 87e23dd271..2d356aead7 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -8,13 +8,13 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig index ececb7ea49..898fc26162 100644 --- a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PB=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index f45db61f1e..6310512017 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -3,12 +3,12 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND" +CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig index ecafb2449c..cb56ce9505 100644 --- a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PB=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 231c806449..ec27153b91 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -1,11 +1,10 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 14f67b03cb..5770ae946d 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig index 524afd972c..3a64b20668 100644 --- a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PB=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 591075f237..f63c0dca8c 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -8,12 +8,12 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB=y +CONFIG_TARGET_P1010RDB_PB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig index 9858190deb..d3fb861e6e 100644 --- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig @@ -6,13 +6,13 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1020MBG=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig index 3eb32f8bf4..ccf8398e50 100644 --- a/configs/P1020MBG-PC_36BIT_defconfig +++ b/configs/P1020MBG-PC_36BIT_defconfig @@ -1,12 +1,11 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1020MBG=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1020MBG" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y diff --git a/configs/P1020MBG-PC_SDCARD_defconfig b/configs/P1020MBG-PC_SDCARD_defconfig index fe73db8769..c9fdcc5030 100644 --- a/configs/P1020MBG-PC_SDCARD_defconfig +++ b/configs/P1020MBG-PC_SDCARD_defconfig @@ -6,12 +6,12 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1020MBG=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P1020MBG-PC_defconfig b/configs/P1020MBG-PC_defconfig index 4f87745bfd..c83299358f 100644 --- a/configs/P1020MBG-PC_defconfig +++ b/configs/P1020MBG-PC_defconfig @@ -1,11 +1,10 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1020MBG=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1020MBG" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index ca98c3122a..a31690753f 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -2,13 +2,13 @@ CONFIG_PPC=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1020RDB_PC=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND" +CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_TPL=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index ffaca1e11d..ce9d293e54 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -6,13 +6,13 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1020RDB_PC=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 4caaad493c..d6c06fe2ac 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -7,13 +7,13 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1020RDB_PC=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 8033e716b3..2598e15b4d 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -1,12 +1,11 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1020RDB_PC=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 4dea4a1d0d..7ed4d97534 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -2,12 +2,12 @@ CONFIG_PPC=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1020RDB_PC=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND" +CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_TPL=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 83fed219cf..b75aa5ea8f 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -6,12 +6,12 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1020RDB_PC=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index fa3b7f078b..7134a1961a 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1020RDB_PC=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 7411c1417d..99bc59c411 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -1,11 +1,10 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1020RDB_PC=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index f2d8fe2124..86cf952762 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -2,12 +2,12 @@ CONFIG_PPC=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1020RDB_PD=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,NAND" +CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_TPL=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 80516e0b50..7131bceb28 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -6,12 +6,12 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1020RDB_PD=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 6ac21e7042..3bc9afdddf 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1020RDB_PD=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index ecb227250c..1cae066425 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -1,11 +1,10 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1020RDB_PD=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig index 1e7c60872e..19e448d330 100644 --- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig @@ -6,13 +6,13 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1020UTM=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig index 7044b78103..aa266f96d5 100644 --- a/configs/P1020UTM-PC_36BIT_defconfig +++ b/configs/P1020UTM-PC_36BIT_defconfig @@ -1,12 +1,11 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1020UTM=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1020UTM" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y diff --git a/configs/P1020UTM-PC_SDCARD_defconfig b/configs/P1020UTM-PC_SDCARD_defconfig index 20353a7800..c03c7c576b 100644 --- a/configs/P1020UTM-PC_SDCARD_defconfig +++ b/configs/P1020UTM-PC_SDCARD_defconfig @@ -6,12 +6,12 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1020UTM=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P1020UTM-PC_defconfig b/configs/P1020UTM-PC_defconfig index 9f70afdcab..c47d5143d3 100644 --- a/configs/P1020UTM-PC_defconfig +++ b/configs/P1020UTM-PC_defconfig @@ -1,11 +1,10 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1020UTM=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1020UTM" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig index d06aa5732a..82dcec5409 100644 --- a/configs/P1021RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1021RDB-PC_36BIT_NAND_defconfig @@ -2,13 +2,13 @@ CONFIG_PPC=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1021RDB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND" +CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_TPL=y diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig index 98705dd359..2ef2edae54 100644 --- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig @@ -6,13 +6,13 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1021RDB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig index bc002af1a2..f7910b6c5d 100644 --- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig @@ -7,13 +7,13 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1021RDB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig index 6c1cb28961..87d45b2919 100644 --- a/configs/P1021RDB-PC_36BIT_defconfig +++ b/configs/P1021RDB-PC_36BIT_defconfig @@ -1,12 +1,11 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1021RDB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1021RDB" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig index ebfc053f21..29335b13af 100644 --- a/configs/P1021RDB-PC_NAND_defconfig +++ b/configs/P1021RDB-PC_NAND_defconfig @@ -2,12 +2,12 @@ CONFIG_PPC=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1021RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND" +CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_TPL=y diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig index c9e4ed7608..bde4d3d8f1 100644 --- a/configs/P1021RDB-PC_SDCARD_defconfig +++ b/configs/P1021RDB-PC_SDCARD_defconfig @@ -6,12 +6,12 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1021RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig index 2fd40b76fd..4f1db4f244 100644 --- a/configs/P1021RDB-PC_SPIFLASH_defconfig +++ b/configs/P1021RDB-PC_SPIFLASH_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1021RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P1021RDB-PC_defconfig b/configs/P1021RDB-PC_defconfig index b7b93e29dc..e26967b854 100644 --- a/configs/P1021RDB-PC_defconfig +++ b/configs/P1021RDB-PC_defconfig @@ -1,11 +1,10 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1021RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1021RDB" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig index 46cd39167b..76724649c6 100644 --- a/configs/P1024RDB_36BIT_defconfig +++ b/configs/P1024RDB_36BIT_defconfig @@ -1,12 +1,11 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1024RDB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1024RDB" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y diff --git a/configs/P1024RDB_NAND_defconfig b/configs/P1024RDB_NAND_defconfig index 36d0867a0c..f4d5485182 100644 --- a/configs/P1024RDB_NAND_defconfig +++ b/configs/P1024RDB_NAND_defconfig @@ -2,12 +2,12 @@ CONFIG_PPC=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1024RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,NAND" +CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_TPL=y diff --git a/configs/P1024RDB_SDCARD_defconfig b/configs/P1024RDB_SDCARD_defconfig index 9bbbae1915..101647f53b 100644 --- a/configs/P1024RDB_SDCARD_defconfig +++ b/configs/P1024RDB_SDCARD_defconfig @@ -6,12 +6,12 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1024RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P1024RDB_SPIFLASH_defconfig b/configs/P1024RDB_SPIFLASH_defconfig index 837b0692c6..94c45c0d1a 100644 --- a/configs/P1024RDB_SPIFLASH_defconfig +++ b/configs/P1024RDB_SPIFLASH_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1024RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P1024RDB_defconfig b/configs/P1024RDB_defconfig index 7dffb2b59a..0d204753a6 100644 --- a/configs/P1024RDB_defconfig +++ b/configs/P1024RDB_defconfig @@ -1,11 +1,10 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1024RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1024RDB" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig index d94c7af2f9..27151820cc 100644 --- a/configs/P1025RDB_36BIT_defconfig +++ b/configs/P1025RDB_36BIT_defconfig @@ -1,12 +1,11 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1025RDB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1025RDB" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig index 0cf5bd24c3..90e83679ad 100644 --- a/configs/P1025RDB_NAND_defconfig +++ b/configs/P1025RDB_NAND_defconfig @@ -2,12 +2,12 @@ CONFIG_PPC=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1025RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,NAND" +CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_TPL=y diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig index c9eda77588..90b005a920 100644 --- a/configs/P1025RDB_SDCARD_defconfig +++ b/configs/P1025RDB_SDCARD_defconfig @@ -6,12 +6,12 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1025RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig index a990a5e9e4..0e5335da32 100644 --- a/configs/P1025RDB_SPIFLASH_defconfig +++ b/configs/P1025RDB_SPIFLASH_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1025RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P1025RDB_defconfig b/configs/P1025RDB_defconfig index 80e997d80c..7094db49b5 100644 --- a/configs/P1025RDB_defconfig +++ b/configs/P1025RDB_defconfig @@ -1,11 +1,10 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P1025RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P1025RDB" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 1661db21d2..d8f375bcf7 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -2,13 +2,13 @@ CONFIG_PPC=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P2020RDB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND" +CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_TPL=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 220bafc2b6..d5e44a0e1c 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -6,13 +6,13 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P2020RDB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index ebb89dde64..7112255aac 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -7,13 +7,13 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P2020RDB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index c422273e1d..a2af2d7fbd 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -1,12 +1,11 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P2020RDB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 4af6039ac9..fd36351c1d 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -2,12 +2,12 @@ CONFIG_PPC=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P2020RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND" +CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_TPL=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index fc8378b32c..7330926c04 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -6,12 +6,12 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P2020RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 754ef24c75..2d380d5e93 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P2020RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 7c40cd645d..7fc2dcd648 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -1,11 +1,10 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_P1_P2_RDB_PC=y +CONFIG_TARGET_P2020RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig index fed256053b..564965206c 100644 --- a/configs/T1023RDB_NAND_defconfig +++ b/configs/T1023RDB_NAND_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T102XRDB=y +CONFIG_TARGET_T1023RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_EXTRA_OPTIONS="T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig index c45de13cb3..cc15635a8a 100644 --- a/configs/T1023RDB_SDCARD_defconfig +++ b/configs/T1023RDB_SDCARD_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T102XRDB=y +CONFIG_TARGET_T1023RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig index 3e5765ee0c..633128ab95 100644 --- a/configs/T1023RDB_SECURE_BOOT_defconfig +++ b/configs/T1023RDB_SECURE_BOOT_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T102XRDB=y +CONFIG_TARGET_T1023RDB=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="T1023RDB,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig index 9ec82d5f9f..28350ad3da 100644 --- a/configs/T1023RDB_SPIFLASH_defconfig +++ b/configs/T1023RDB_SPIFLASH_defconfig @@ -8,12 +8,12 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T102XRDB=y +CONFIG_TARGET_T1023RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig index c0fe36b678..ef0005e3ce 100644 --- a/configs/T1023RDB_defconfig +++ b/configs/T1023RDB_defconfig @@ -1,11 +1,11 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T102XRDB=y +CONFIG_TARGET_T1023RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB" +CONFIG_SYS_EXTRA_OPTIONS="T1023RDB" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig index 72df6ea028..d7bd23ac5f 100644 --- a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig +++ b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig @@ -1,13 +1,13 @@ CONFIG_PPC=y CONFIG_VIDEO=y CONFIG_MPC85xx=y -CONFIG_TARGET_T102XQDS=y +CONFIG_TARGET_T1024QDS=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig index eebfb59f28..bd2b438288 100644 --- a/configs/T1024QDS_DDR4_defconfig +++ b/configs/T1024QDS_DDR4_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y CONFIG_VIDEO=y CONFIG_MPC85xx=y -CONFIG_TARGET_T102XQDS=y +CONFIG_TARGET_T1024QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig index 428bb9bc4d..1563609b4f 100644 --- a/configs/T1024QDS_NAND_defconfig +++ b/configs/T1024QDS_NAND_defconfig @@ -8,12 +8,12 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_VIDEO=y CONFIG_MPC85xx=y -CONFIG_TARGET_T102XQDS=y +CONFIG_TARGET_T1024QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig index 3b3bf63e3b..a86657d313 100644 --- a/configs/T1024QDS_SDCARD_defconfig +++ b/configs/T1024QDS_SDCARD_defconfig @@ -8,12 +8,12 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_VIDEO=y CONFIG_MPC85xx=y -CONFIG_TARGET_T102XQDS=y +CONFIG_TARGET_T1024QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig index 0a6e0b7ab7..ce7d142f61 100644 --- a/configs/T1024QDS_SECURE_BOOT_defconfig +++ b/configs/T1024QDS_SECURE_BOOT_defconfig @@ -1,13 +1,13 @@ CONFIG_PPC=y CONFIG_VIDEO=y CONFIG_MPC85xx=y -CONFIG_TARGET_T102XQDS=y +CONFIG_TARGET_T1024QDS=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig index 3ea8dfc9ef..2ab4752d1a 100644 --- a/configs/T1024QDS_SPIFLASH_defconfig +++ b/configs/T1024QDS_SPIFLASH_defconfig @@ -9,12 +9,12 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_VIDEO=y CONFIG_MPC85xx=y -CONFIG_TARGET_T102XQDS=y +CONFIG_TARGET_T1024QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig index fb2e993955..e45baefe94 100644 --- a/configs/T1024QDS_defconfig +++ b/configs/T1024QDS_defconfig @@ -1,12 +1,11 @@ CONFIG_PPC=y CONFIG_VIDEO=y CONFIG_MPC85xx=y -CONFIG_TARGET_T102XQDS=y +CONFIG_TARGET_T1024QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index dfc9697d4e..96a6b653b1 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T102XRDB=y +CONFIG_TARGET_T1024RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_EXTRA_OPTIONS="T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 15545d887b..c6fdb22611 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T102XRDB=y +CONFIG_TARGET_T1024RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig index 43ba56b9e7..806cc214b0 100644 --- a/configs/T1024RDB_SECURE_BOOT_defconfig +++ b/configs/T1024RDB_SECURE_BOOT_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T102XRDB=y +CONFIG_TARGET_T1024RDB=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="T1024RDB,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 99d2a40d55..bce2a599b5 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -8,12 +8,12 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T102XRDB=y +CONFIG_TARGET_T1024RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 72fc86f53c..0aef7574da 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -1,11 +1,11 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T102XRDB=y +CONFIG_TARGET_T1024RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB" +CONFIG_SYS_EXTRA_OPTIONS="T1024RDB" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig index c420dc3978..c5ab87be99 100644 --- a/configs/T1040D4RDB_NAND_defconfig +++ b/configs/T1040D4RDB_NAND_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1040D4RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND,SYS_FSL_DDR4" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig index ff4bbe3474..63af509bf9 100644 --- a/configs/T1040D4RDB_SDCARD_defconfig +++ b/configs/T1040D4RDB_SDCARD_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1040D4RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,SYS_FSL_DDR4" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig index f548e21dd0..a89786a2b3 100644 --- a/configs/T1040D4RDB_SECURE_BOOT_defconfig +++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1040D4RDB=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig index 00feb36366..587cca1bca 100644 --- a/configs/T1040D4RDB_SPIFLASH_defconfig +++ b/configs/T1040D4RDB_SPIFLASH_defconfig @@ -8,12 +8,12 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1040D4RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,SYS_FSL_DDR4" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig index 55adc62dfd..87be2b59db 100644 --- a/configs/T1040D4RDB_defconfig +++ b/configs/T1040D4RDB_defconfig @@ -1,11 +1,11 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1040D4RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1040QDS_DDR4_defconfig b/configs/T1040QDS_DDR4_defconfig index c4f1f5a443..0af3b36156 100644 --- a/configs/T1040QDS_DDR4_defconfig +++ b/configs/T1040QDS_DDR4_defconfig @@ -6,7 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig index 226a0c5bce..9666832cf4 100644 --- a/configs/T1040QDS_SECURE_BOOT_defconfig +++ b/configs/T1040QDS_SECURE_BOOT_defconfig @@ -7,7 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig index c2c01a04e8..1c183f4be3 100644 --- a/configs/T1040QDS_defconfig +++ b/configs/T1040QDS_defconfig @@ -6,7 +6,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig index da6ef10e2f..2129bf487c 100644 --- a/configs/T1040RDB_NAND_defconfig +++ b/configs/T1040RDB_NAND_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1040RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig index 49b6221e39..fc74dec744 100644 --- a/configs/T1040RDB_SDCARD_defconfig +++ b/configs/T1040RDB_SDCARD_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1040RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig index 98e78559f1..db5316db16 100644 --- a/configs/T1040RDB_SECURE_BOOT_defconfig +++ b/configs/T1040RDB_SECURE_BOOT_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1040RDB=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT,T1040RDB" +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig index 31ea58903d..9f05ac370b 100644 --- a/configs/T1040RDB_SPIFLASH_defconfig +++ b/configs/T1040RDB_SPIFLASH_defconfig @@ -8,12 +8,12 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1040RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig index b898f93a5a..e246c435d2 100644 --- a/configs/T1040RDB_defconfig +++ b/configs/T1040RDB_defconfig @@ -1,11 +1,10 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1040RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 44303c7c01..4c6b918a17 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -8,12 +8,12 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_VIDEO=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1042D4RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND,SYS_FSL_DDR4" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index c14b641fc6..c2c03ee723 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -8,12 +8,12 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_VIDEO=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1042D4RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,SYS_FSL_DDR4" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig index f531001cd5..ced54e17c6 100644 --- a/configs/T1042D4RDB_SECURE_BOOT_defconfig +++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig @@ -1,13 +1,13 @@ CONFIG_PPC=y CONFIG_VIDEO=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1042D4RDB=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 31527b3a12..0a2f37903a 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -9,12 +9,12 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_VIDEO=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1042D4RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,SYS_FSL_DDR4" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index d503070136..ef68c5ff5a 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y CONFIG_VIDEO=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1042D4RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig index 7e78aa2a1e..c07a29c0a1 100644 --- a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig +++ b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig @@ -8,12 +8,12 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_VIDEO=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1042RDB_PI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND,SECURE_BOOT" CONFIG_BOOTDELAY=0 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig index ae40fe6a3f..d8aa1f73ca 100644 --- a/configs/T1042RDB_PI_NAND_defconfig +++ b/configs/T1042RDB_PI_NAND_defconfig @@ -8,12 +8,12 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_VIDEO=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1042RDB_PI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig index 3c31b367ff..af98400481 100644 --- a/configs/T1042RDB_PI_SDCARD_defconfig +++ b/configs/T1042RDB_PI_SDCARD_defconfig @@ -8,12 +8,12 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_VIDEO=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1042RDB_PI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig index 12068a6690..369944dec2 100644 --- a/configs/T1042RDB_PI_SPIFLASH_defconfig +++ b/configs/T1042RDB_PI_SPIFLASH_defconfig @@ -9,12 +9,12 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_VIDEO=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1042RDB_PI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig index 85b3cbf24e..4a9bd3a307 100644 --- a/configs/T1042RDB_PI_defconfig +++ b/configs/T1042RDB_PI_defconfig @@ -1,12 +1,11 @@ CONFIG_PPC=y CONFIG_VIDEO=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1042RDB_PI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig index e9d41455a1..2e6e44162c 100644 --- a/configs/T1042RDB_SECURE_BOOT_defconfig +++ b/configs/T1042RDB_SECURE_BOOT_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1042RDB=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB" +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig index 8e11872b93..2223e6d6c9 100644 --- a/configs/T1042RDB_defconfig +++ b/configs/T1042RDB_defconfig @@ -1,11 +1,10 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T104XRDB=y +CONFIG_TARGET_T1042RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index e42dd6b123..834e441f16 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T208XQDS=y +CONFIG_TARGET_T2080QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 70a996575c..2393bc7f75 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T208XQDS=y +CONFIG_TARGET_T2080QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index f6174e076f..ac8842e56b 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T208XQDS=y +CONFIG_TARGET_T2080QDS=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 93b5ed6afc..e4568b6193 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -8,12 +8,12 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T208XQDS=y +CONFIG_TARGET_T2080QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 4a80068872..282e1c28c4 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -1,11 +1,11 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T208XQDS=y +CONFIG_TARGET_T2080QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 7e23651e94..393d4e534b 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -1,11 +1,10 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T208XQDS=y +CONFIG_TARGET_T2080QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 5e17f3bd51..f548e38bee 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T208XRDB=y +CONFIG_TARGET_T2080RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index 76dcaf977e..ec4e5767ac 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T208XRDB=y +CONFIG_TARGET_T2080RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig index 0818d9ce23..4675ac64cf 100644 --- a/configs/T2080RDB_SECURE_BOOT_defconfig +++ b/configs/T2080RDB_SECURE_BOOT_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T208XRDB=y +CONFIG_TARGET_T2080RDB=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MEMTEST=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index f33fd4e61a..34e1c67aaa 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -8,12 +8,12 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T208XRDB=y +CONFIG_TARGET_T2080RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig index 1b8ede8d9b..4b328807b8 100644 --- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig @@ -1,11 +1,11 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T208XRDB=y +CONFIG_TARGET_T2080RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 94c2e08757..14310c4ba9 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -1,11 +1,10 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T208XRDB=y +CONFIG_TARGET_T2080RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MEMTEST=y diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig index 410d375b81..34350aa055 100644 --- a/configs/T2081QDS_NAND_defconfig +++ b/configs/T2081QDS_NAND_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T208XQDS=y +CONFIG_TARGET_T2081QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig index a0f49d7002..630a5ce4b0 100644 --- a/configs/T2081QDS_SDCARD_defconfig +++ b/configs/T2081QDS_SDCARD_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T208XQDS=y +CONFIG_TARGET_T2081QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig index 902566d79c..0c43f890eb 100644 --- a/configs/T2081QDS_SPIFLASH_defconfig +++ b/configs/T2081QDS_SPIFLASH_defconfig @@ -8,12 +8,12 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T208XQDS=y +CONFIG_TARGET_T2081QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig index 4caa2e4eef..1665ca539d 100644 --- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig @@ -1,11 +1,11 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T208XQDS=y +CONFIG_TARGET_T2081QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig index 07ff6b61d9..822b92f044 100644 --- a/configs/T2081QDS_defconfig +++ b/configs/T2081QDS_defconfig @@ -1,11 +1,10 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T208XQDS=y +CONFIG_TARGET_T2081QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y diff --git a/configs/T4160QDS_NAND_defconfig b/configs/T4160QDS_NAND_defconfig index 5c981aa1ea..2d2297b659 100644 --- a/configs/T4160QDS_NAND_defconfig +++ b/configs/T4160QDS_NAND_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T4240QDS=y +CONFIG_TARGET_T4160QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/T4160QDS_SDCARD_defconfig b/configs/T4160QDS_SDCARD_defconfig index 8c5d4ad3d5..95a2a3f723 100644 --- a/configs/T4160QDS_SDCARD_defconfig +++ b/configs/T4160QDS_SDCARD_defconfig @@ -7,12 +7,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_MPC85xx=y -CONFIG_TARGET_T4240QDS=y +CONFIG_TARGET_T4160QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig index 70abd6eda4..36940e4da5 100644 --- a/configs/T4160QDS_SECURE_BOOT_defconfig +++ b/configs/T4160QDS_SECURE_BOOT_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T4240QDS=y +CONFIG_TARGET_T4160QDS=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y diff --git a/configs/T4160QDS_defconfig b/configs/T4160QDS_defconfig index 109d6109f5..46ec844fea 100644 --- a/configs/T4160QDS_defconfig +++ b/configs/T4160QDS_defconfig @@ -1,11 +1,10 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T4240QDS=y +CONFIG_TARGET_T4160QDS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig index 9336a3fd9d..b76836841d 100644 --- a/configs/T4160RDB_defconfig +++ b/configs/T4160RDB_defconfig @@ -1,11 +1,10 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_TARGET_T4240RDB=y +CONFIG_TARGET_T4160RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y diff --git a/configs/T4240QDS_NAND_defconfig b/configs/T4240QDS_NAND_defconfig index 4cdbeb42db..493f3c1baf 100644 --- a/configs/T4240QDS_NAND_defconfig +++ b/configs/T4240QDS_NAND_defconfig @@ -12,7 +12,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/T4240QDS_SDCARD_defconfig b/configs/T4240QDS_SDCARD_defconfig index 8f8837c88e..2357d829d5 100644 --- a/configs/T4240QDS_SDCARD_defconfig +++ b/configs/T4240QDS_SDCARD_defconfig @@ -12,7 +12,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig index 85ca4960b3..ed2d093a9c 100644 --- a/configs/T4240QDS_SECURE_BOOT_defconfig +++ b/configs/T4240QDS_SECURE_BOOT_defconfig @@ -6,7 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y diff --git a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig index 91cd3cf6ce..7e9b97e046 100644 --- a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig @@ -5,7 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" +CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set diff --git a/configs/T4240QDS_defconfig b/configs/T4240QDS_defconfig index a9c263e5bd..559da713f0 100644 --- a/configs/T4240QDS_defconfig +++ b/configs/T4240QDS_defconfig @@ -5,7 +5,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index 2104a95af5..ef299aa52f 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -12,7 +12,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index b688a575b5..bf357622fd 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -5,7 +5,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y diff --git a/doc/README.mpc85xx-sd-spi-boot b/doc/README.mpc85xx-sd-spi-boot index d5043ccb66..e3f580446a 100644 --- a/doc/README.mpc85xx-sd-spi-boot +++ b/doc/README.mpc85xx-sd-spi-boot @@ -57,23 +57,17 @@ Please see the SoC reference manual for more documentation. P1022DS config_sram_p1022ds.dat P2020DS config_sram_p2020ds.dat -P2010DS config_sram_p2020ds.dat P1020RDB config_ddr2_1g_p1020rdb_533M.dat P1020RDB config_ddr2_1g_p1020rdb_667M.dat P2020RDB config_ddr2_1g_p2020rdb_800M.dat P2020RDB config_ddr2_1g_p2020rdb_667M.dat P2020RDB config_ddr3_1gb_64bit_p2020rdb_pc.dat -P2010RDB config_ddr3_1gb_64bit_p2020rdb_pc.dat P1020RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat P1011RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat P1010RDB config_ddr3_1gb_p1010rdb_800M.dat -P1014RDB config_ddr3_1gb_p1014rdb_800M.dat P1021RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat -P1012RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat P1022DS config_ddr3_2gb_p1022ds.dat -P1013DS config_ddr3_2gb_p1022ds.dat P1024RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat -P1013RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat P1025RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat P1016RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat P1020UTM config_ddr3_1gb_p1_p2_rdb_pc_800M.dat diff --git a/doc/README.mpc85xxads b/doc/README.mpc85xxads index ef92739756..9b35fb2016 100644 --- a/doc/README.mpc85xxads +++ b/doc/README.mpc85xxads @@ -136,9 +136,7 @@ Updated 13-July-2004 Jon Loeliger CONFIG_BOOKE BOOKE(e.g. Motorola MPC85xx, AMCC 440, etc) CONFIG_E500 BOOKE e500 family(Motorola) CONFIG_MPC85xx MPC8540,MPC8560 and their derivatives - CONFIG_MPC8540 MPC8540 specific - CONFIG_MPC8540ADS MPC8540ADS board specific - CONFIG_MPC8560ADS MPC8560ADS board specific + CONFIG_ARCH_MPC8540 MPC8540 specific CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet for networking CONFIG_SPD_EEPROM Use SPD EEPROM for DDR auto configuration, you can also manual config the DDR after undef this diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 4a8cc3295a..1b882291e4 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -21,7 +21,7 @@ uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = { 0, -#if defined(CONFIG_PPC_C29X) +#if defined(CONFIG_ARCH_C29X) CONFIG_SYS_FSL_SEC_IDX_OFFSET, 2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET #endif diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 24fd36602d..32b09679e2 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -1831,7 +1831,7 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int clk_adjust; /* Clock adjust */ unsigned int ss_en = 0; /* Source synchronous enable */ -#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) /* Per FSL Application Note: AN2805 */ ss_en = 1; #endif diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c index c27288dda2..c005f5294c 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c @@ -47,7 +47,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); -#if defined(CONFIG_MPC8555) || defined(CONFIG_MPC8541) +#if defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8541) out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); #endif diff --git a/drivers/input/keyboard.c b/drivers/input/keyboard.c index 48255bd87b..7af5868dea 100644 --- a/drivers/input/keyboard.c +++ b/drivers/input/keyboard.c @@ -20,8 +20,8 @@ static struct input_config config; static int kbd_read_keys(struct input_config *config) { -#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || \ - defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#if defined(CONFIG_MPC5xxx) || defined(CONFIG_ARCH_MPC8540) || \ + defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) /* no ISR is used, so received chars must be polled */ ps2ser_check(); #endif diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index 316fef485d..08b3f27601 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -17,26 +17,24 @@ obj-$(CONFIG_SYS_FMAN_V3) += memac_phy.o obj-$(CONFIG_SYS_FMAN_V3) += memac.o # SoC specific SERDES support -obj-$(CONFIG_P1017) += p1023.o -obj-$(CONFIG_P1023) += p1023.o +obj-$(CONFIG_ARCH_P1023) += p1023.o # The P204x, P304x, and P5020 are the same -obj-$(CONFIG_PPC_P2041) += p5020.o -obj-$(CONFIG_PPC_P3041) += p5020.o -obj-$(CONFIG_PPC_P4080) += p4080.o -obj-$(CONFIG_PPC_P5020) += p5020.o -obj-$(CONFIG_PPC_P5040) += p5040.o -obj-$(CONFIG_PPC_T1040) += t1040.o -obj-$(CONFIG_PPC_T1042) += t1040.o +obj-$(CONFIG_ARCH_P2041) += p5020.o +obj-$(CONFIG_ARCH_P3041) += p5020.o +obj-$(CONFIG_ARCH_P4080) += p4080.o +obj-$(CONFIG_ARCH_P5020) += p5020.o +obj-$(CONFIG_ARCH_P5040) += p5040.o +obj-$(CONFIG_ARCH_T1040) += t1040.o +obj-$(CONFIG_ARCH_T1042) += t1040.o obj-$(CONFIG_PPC_T1020) += t1040.o obj-$(CONFIG_PPC_T1022) += t1040.o -obj-$(CONFIG_PPC_T1023) += t1024.o -obj-$(CONFIG_PPC_T1024) += t1024.o -obj-$(CONFIG_PPC_T2080) += t2080.o -obj-$(CONFIG_PPC_T2081) += t2080.o -obj-$(CONFIG_PPC_T4240) += t4240.o -obj-$(CONFIG_PPC_T4160) += t4240.o -obj-$(CONFIG_PPC_T4080) += t4240.o -obj-$(CONFIG_PPC_B4420) += b4860.o -obj-$(CONFIG_PPC_B4860) += b4860.o +obj-$(CONFIG_ARCH_T1023) += t1024.o +obj-$(CONFIG_ARCH_T1024) += t1024.o +obj-$(CONFIG_ARCH_T2080) += t2080.o +obj-$(CONFIG_ARCH_T2081) += t2080.o +obj-$(CONFIG_ARCH_T4240) += t4240.o +obj-$(CONFIG_ARCH_T4160) += t4240.o +obj-$(CONFIG_ARCH_B4420) += b4860.o +obj-$(CONFIG_ARCH_B4860) += b4860.o obj-$(CONFIG_LS1043A) += ls1043.o obj-$(CONFIG_ARCH_LS1046A) += ls1046.o diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c index eb058c9c3d..5aeeb87282 100644 --- a/drivers/net/fm/b4860.c +++ b/drivers/net/fm/b4860.c @@ -47,7 +47,7 @@ void fman_enable_port(enum fm_port port) phy_interface_t fman_port_enet_if(enum fm_port port) { -#if defined(CONFIG_B4860QDS) +#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS) u32 serdes2_prtcl; char buffer[HWCONFIG_BUFFER_SIZE]; char *buf = NULL; @@ -60,7 +60,8 @@ phy_interface_t fman_port_enet_if(enum fm_port port) /*B4860 has two 10Gig Mac*/ if ((port == FM1_10GEC1 || port == FM1_10GEC2) && ((is_serdes_configured(XAUI_FM1_MAC9)) || - #if !defined(CONFIG_B4860QDS) + #if (!defined(CONFIG_TARGET_B4860QDS) && \ + !defined(CONFIG_TARGET_B4R420QDS)) (is_serdes_configured(XFI_FM1_MAC9)) || (is_serdes_configured(XFI_FM1_MAC10)) || #endif @@ -68,7 +69,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) )) return PHY_INTERFACE_MODE_XGMII; -#if defined(CONFIG_B4860QDS) +#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS) serdes2_prtcl = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h index fa9bc9f42d..64cc9718d0 100644 --- a/drivers/net/fm/fm.h +++ b/drivers/net/fm/fm.h @@ -88,7 +88,7 @@ struct fm_port_global_pram { #define PRAM_MODE_GLOBAL 0x20000000 #define PRAM_MODE_GRACEFUL_STOP 0x00800000 -#if defined(CONFIG_P1017) || defined(CONFIG_P1023) +#if defined(CONFIG_ARCH_P1023) #define FM_FREE_POOL_SIZE 0x2000 /* 8K bytes */ #else #define FM_FREE_POOL_SIZE 0x20000 /* 128K bytes */ diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 5fd956adce..b3af707a3d 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -567,7 +567,7 @@ static void phy_change(struct eth_device *dev) { uec_private_t *uec = (uec_private_t *)dev->priv; -#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); /* QE9 and QE12 need to be set for enabling QE MII managment signals */ @@ -578,7 +578,7 @@ static void phy_change(struct eth_device *dev) /* Update the link, speed, duplex */ uec->mii_info->phyinfo->read_status(uec->mii_info); -#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) /* * QE12 is muxed with LBCTL, it needs to be released for enabling * LBCTL signal for LBC usage. @@ -1193,14 +1193,14 @@ static int uec_init(struct eth_device* dev, bd_t *bd) uec_private_t *uec; int err, i; struct phy_info *curphy; -#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif uec = (uec_private_t *)dev->priv; if (uec->the_first_run == 0) { -#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) /* QE9 and QE12 need to be set for enabling QE MII managment signals */ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); @@ -1232,7 +1232,7 @@ static int uec_init(struct eth_device* dev, bd_t *bd) udelay(100000); } while (1); -#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) /* QE12 needs to be released for enabling LBCTL signal*/ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); #endif diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 5f8b99e28a..cd4333f2f1 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -10,8 +10,6 @@ /* * B4860 QDS board configuration file */ -#define CONFIG_B4860QDS - #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg @@ -75,7 +73,7 @@ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#ifndef CONFIG_PPC_B4420 +#ifndef CONFIG_ARCH_B4420 #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ @@ -790,7 +788,7 @@ unsigned long get_board_ddr_clk(void); #define __USB_PHY_TYPE ulpi -#ifdef CONFIG_PPC_B4860 +#ifdef CONFIG_ARCH_B4860 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ "bank_intlv=cs0_cs1;" \ "en_cpc:cpc2;" diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 86419eb8f3..aaf7106416 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -11,10 +11,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifdef CONFIG_BSC9131RDB -#define CONFIG_BSC9131 #define CONFIG_NAND_FSL_IFC -#endif #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 0e0eefb8b9..8eee7384cc 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -11,10 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifdef CONFIG_BSC9132QDS -#define CONFIG_BSC9132 -#endif - #define CONFIG_MISC_INIT_R #ifdef CONFIG_SDCARD diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 41dde8213f..39eefb441c 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -11,10 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifdef CONFIG_C29XPCIE -#define CONFIG_PPC_C29X -#endif - #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_SYS_TEXT_BASE 0x11000000 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 0f29863a96..446303d18b 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -40,8 +40,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8536 1 -#define CONFIG_MPC8536DS 1 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index af3e85e984..54932fd622 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -21,8 +21,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8540 1 /* MPC8540 specific */ -#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ /* * default CCARBAR is at 0xff700000 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 134add5a5d..29bca4c1f6 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -17,8 +17,6 @@ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_MPC8541 1 /* MPC8541 specific */ -#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */ #define CONFIG_SYS_TEXT_BASE 0xfff80000 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index d868ce2315..6c17a3be5c 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -14,8 +14,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8544 1 -#define CONFIG_MPC8544DS 1 #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xfff80000 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index fa114b3f15..310c070e50 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -16,8 +16,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8548 1 /* MPC8548 specific */ -#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xfff80000 diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 908b7eddd3..3cf8d97b41 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -17,8 +17,6 @@ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_MPC8555 1 /* MPC8555 specific */ -#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */ #define CONFIG_SYS_TEXT_BASE 0xfff80000 diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 25227e5bcb..641521cf6a 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -22,8 +22,6 @@ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ -#define CONFIG_MPC8560 1 /* * default CCARBAR is at 0xff700000 diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 62f06db3f3..e7adb17956 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -13,8 +13,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8568 1 /* MPC8568 specific */ -#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ #define CONFIG_SYS_TEXT_BASE 0xfff80000 diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index a2ec52b730..91f0104f96 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -13,8 +13,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8569 1 /* MPC8569 specific */ -#define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */ #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index d4be14007f..e134560978 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -28,8 +28,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8572 1 -#define CONFIG_MPC8572DS 1 #define CONFIG_MP 1 /* support multiple processors */ #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 2529d8a71e..75693a0423 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -12,8 +12,6 @@ #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_MPC8610 1 /* MPC8610 specific */ -#define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ #define CONFIG_SYS_TEXT_BASE 0xfff00000 diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index b35bbd4eb8..c94b3296d4 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -17,8 +17,6 @@ #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_MPC8641 1 /* MPC8641 specific */ -#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ #define CONFIG_MP 1 /* support multiple processors */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ #define CONFIG_ADDR_MAP 1 /* Use addr map */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index c45b091227..3ced88d415 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -11,7 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_P1010 #define CONFIG_E500 /* BOOKE e500 family */ #include <asm/config_mpc85xx.h> #define CONFIG_NAND_FSL_IFC @@ -175,9 +174,9 @@ #endif /* controller 2, Slot 2, tgtid 2, Base address 9000 */ -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" #endif #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 @@ -379,7 +378,7 @@ extern unsigned long get_sdram_size(void); | CSPR_V) #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ @@ -389,7 +388,7 @@ extern unsigned long get_sdram_size(void); | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ @@ -405,7 +404,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_CMD_NAND -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) /* NAND Flash Timing Params */ #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ FTIM0_NAND_TWP(0x0C) | \ @@ -420,7 +419,7 @@ extern unsigned long get_sdram_size(void); FTIM2_NAND_TWHRE(0x0f) #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ /* ONFI NAND Flash mode0 Timing Params */ #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ @@ -593,7 +592,7 @@ extern unsigned long get_sdram_size(void); #define I2C_PCA9557_BUS_NUM 0 /* I2C EEPROM */ -#if defined(CONFIG_P1010RDB_PB) +#if defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_ID_EEPROM #ifdef CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID @@ -719,10 +718,10 @@ extern unsigned long get_sdram_size(void); #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) #else -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_ENV_SIZE (16 * 1024) #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ #endif @@ -843,7 +842,7 @@ extern unsigned long get_sdram_size(void); "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ CONFIG_BOOTMODE -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_BOOTMODE \ "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ @@ -852,7 +851,7 @@ extern unsigned long get_sdram_size(void); "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_BOOTMODE \ "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 6a4937bf1e..6f07080a87 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -90,8 +90,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_P1022 -#define CONFIG_P1022DS #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index eba66ec932..5061286c3f 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -25,7 +25,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_P1023 #define CONFIG_MP /* support multiple processors */ #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 350756b6df..417bfd36b1 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -11,9 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_P2041RDB -#define CONFIG_PPC_P2041 - #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index c901fe28cb..52ef4321d6 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -8,9 +8,6 @@ * P3041 DS board configuration file * */ -#define CONFIG_P3041DS -#define CONFIG_PPC_P3041 - #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ #define CONFIG_MMC diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 0d44c008aa..65ec8f704d 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -8,9 +8,6 @@ * P4080 DS board configuration file * Also supports P4040 DS */ -#define CONFIG_P4080DS -#define CONFIG_PPC_P4080 - #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ #define CONFIG_MMC diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index d2cedfe860..17e941e4e7 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -8,9 +8,6 @@ * P5020 DS board configuration file * Also supports P5010 DS */ -#define CONFIG_P5020DS -#define CONFIG_PPC_P5020 - #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ #define CONFIG_MMC diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h index dc827210d2..078e60c4c2 100644 --- a/include/configs/P5040DS.h +++ b/include/configs/P5040DS.h @@ -8,9 +8,6 @@ * P5040 DS board configuration file * */ -#define CONFIG_P5040DS -#define CONFIG_PPC_P5040 - #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ #define CONFIG_MMC diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index c290101101..3c0a0c95a7 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -497,7 +497,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* Video */ -#ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */ +#ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */ #define CONFIG_FSL_DIU_FB #ifdef CONFIG_FSL_DIU_FB #define CONFIG_FSL_DIU_CH7301 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 5b233bc70f..e2aea8bf9e 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -34,7 +34,7 @@ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ /* support deep sleep */ -#ifdef CONFIG_PPC_T1024 +#ifdef CONFIG_ARCH_T1024 #define CONFIG_DEEP_SLEEP #endif #if defined(CONFIG_DEEP_SLEEP) @@ -556,7 +556,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#ifdef CONFIG_PPC_T1040 +#ifdef CONFIG_ARCH_T1040 #define CONFIG_PCIE4 /* PCIE controller 4 */ #endif #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ @@ -858,7 +858,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BAUDRATE 115200 #define __USB_PHY_TYPE utmi -#ifdef CONFIG_PPC_T1024 +#ifdef CONFIG_ARCH_T1024 #define CONFIG_BOARDNAME t1024rdb #define BANK_INTLV cs0_cs1 #else diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 77318091df..ed568f3377 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -10,8 +10,6 @@ /* * T104x RDB board configuration file */ -#define CONFIG_T104xRDB - #define CONFIG_E500 /* BOOKE e500 family */ #include <asm/config_mpc85xx.h> @@ -56,23 +54,23 @@ #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -#ifdef CONFIG_T1040RDB +#ifdef CONFIG_TARGET_T1040RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg #endif -#ifdef CONFIG_T1042RDB_PI +#ifdef CONFIG_TARGET_T1042RDB_PI #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg #endif -#ifdef CONFIG_T1042RDB +#ifdef CONFIG_TARGET_T1042RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg #endif -#ifdef CONFIG_T1040D4RDB +#ifdef CONFIG_TARGET_T1040D4RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg #endif -#ifdef CONFIG_T1042D4RDB +#ifdef CONFIG_TARGET_T1042D4RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg #endif @@ -90,23 +88,23 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#ifdef CONFIG_T1040RDB +#ifdef CONFIG_TARGET_T1040RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg #endif -#ifdef CONFIG_T1042RDB_PI +#ifdef CONFIG_TARGET_T1042RDB_PI #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg #endif -#ifdef CONFIG_T1042RDB +#ifdef CONFIG_TARGET_T1042RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg #endif -#ifdef CONFIG_T1040D4RDB +#ifdef CONFIG_TARGET_T1040D4RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg #endif -#ifdef CONFIG_T1042D4RDB +#ifdef CONFIG_TARGET_T1042D4RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg #endif @@ -124,23 +122,23 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#ifdef CONFIG_T1040RDB +#ifdef CONFIG_TARGET_T1040RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg #endif -#ifdef CONFIG_T1042RDB_PI +#ifdef CONFIG_TARGET_T1042RDB_PI #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg #endif -#ifdef CONFIG_T1042RDB +#ifdef CONFIG_TARGET_T1042RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg #endif -#ifdef CONFIG_T1040D4RDB +#ifdef CONFIG_TARGET_T1040D4RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg #endif -#ifdef CONFIG_T1042D4RDB +#ifdef CONFIG_TARGET_T1042D4RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #endif @@ -342,13 +340,13 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_SHIFT 0x03 -#if defined(CONFIG_T1042RDB_PI) +#if defined(CONFIG_TARGET_T1042RDB_PI) #define CPLD_DIU_SEL_DFP 0x80 -#elif defined(CONFIG_T1042D4RDB) +#elif defined(CONFIG_TARGET_T1042D4RDB) #define CPLD_DIU_SEL_DFP 0xc0 #endif -#if defined(CONFIG_T1040D4RDB) +#if defined(CONFIG_TARGET_T1040D4RDB) #define CPLD_INT_MASK_ALL 0xFF #define CPLD_INT_MASK_THERM 0x80 #define CPLD_INT_MASK_DVI_DFP 0x40 @@ -516,7 +514,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) -#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB) +#if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) /* Video */ #define CONFIG_FSL_DIU_FB @@ -547,11 +545,11 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 -#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #define I2C_MUX_CH_DEFAULT 0x8 -#endif -#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) +#if defined(CONFIG_TARGET_T1042RDB_PI) || \ + defined(CONFIG_TARGET_T1040D4RDB) || \ + defined(CONFIG_TARGET_T1042D4RDB) /* LDI/DVI Encoder for display */ #define CONFIG_SYS_I2C_LDI_ADDR 0x38 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 @@ -706,10 +704,8 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME -#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #define CONFIG_QE #define CONFIG_U_QE -#endif /* Default address of microcode for the Linux Fman driver */ #if defined(CONFIG_SPIFLASH) @@ -735,7 +731,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif -#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_QE_FW_ADDR 0x130000 #elif defined(CONFIG_SDCARD) @@ -745,7 +740,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #else #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 #endif -#endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) @@ -758,17 +752,17 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #endif #ifdef CONFIG_FMAN_ENET -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 -#elif defined(CONFIG_T1040D4RDB) +#elif defined(CONFIG_TARGET_T1040D4RDB) #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 -#elif defined(CONFIG_T1042D4RDB) +#elif defined(CONFIG_TARGET_T1042D4RDB) #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 #endif -#ifdef CONFIG_T104XD4RDB +#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 #else @@ -777,10 +771,10 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #endif /* Enable VSC9953 L2 Switch driver on T1040 SoC */ -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) +#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) #define CONFIG_VSC9953 #define CONFIG_CMD_ETHSW -#ifdef CONFIG_T1040RDB +#ifdef CONFIG_TARGET_T1040RDB #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 #else @@ -803,7 +797,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg /* * Command line configuration. */ -#ifdef CONFIG_T1042RDB_PI +#ifdef CONFIG_TARGET_T1042RDB_PI #define CONFIG_CMD_DATE #endif #define CONFIG_CMD_ERRATA @@ -881,15 +875,15 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define __USB_PHY_TYPE utmi #define RAMDISKFILE "t104xrdb/ramdisk.uboot" -#ifdef CONFIG_T1040RDB +#ifdef CONFIG_TARGET_T1040RDB #define FDTFILE "t1040rdb/t1040rdb.dtb" -#elif defined(CONFIG_T1042RDB_PI) +#elif defined(CONFIG_TARGET_T1042RDB_PI) #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" -#elif defined(CONFIG_T1042RDB) +#elif defined(CONFIG_TARGET_T1042RDB) #define FDTFILE "t1042rdb/t1042rdb.dtb" -#elif defined(CONFIG_T1040D4RDB) +#elif defined(CONFIG_TARGET_T1040D4RDB) #define FDTFILE "t1042rdb/t1040d4rdb.dtb" -#elif defined(CONFIG_T1042D4RDB) +#elif defined(CONFIG_TARGET_T1042D4RDB) #define FDTFILE "t1042rdb/t1042d4rdb.dtb" #endif diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 8702a4512c..17176f46c5 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -14,13 +14,13 @@ #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #define CONFIG_MMC #define CONFIG_USB_EHCI -#if defined(CONFIG_PPC_T2080) +#if defined(CONFIG_ARCH_T2080) #define CONFIG_T2080QDS #define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ -#elif defined(CONFIG_PPC_T2081) +#elif defined(CONFIG_ARCH_T2081) #define CONFIG_T2081QDS #endif @@ -69,9 +69,9 @@ #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -#if defined(CONFIG_PPC_T2080) +#if defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg -#elif defined(CONFIG_PPC_T2081) +#elif defined(CONFIG_ARCH_T2081) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg #endif #define CONFIG_SPL_NAND_BOOT @@ -88,9 +88,9 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#if defined(CONFIG_PPC_T2080) +#if defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg -#elif defined(CONFIG_PPC_T2081) +#elif defined(CONFIG_ARCH_T2081) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg #endif #define CONFIG_SPL_SPI_BOOT @@ -107,9 +107,9 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#if defined(CONFIG_PPC_T2080) +#if defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg -#elif defined(CONFIG_PPC_T2081) +#elif defined(CONFIG_ARCH_T2081) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg #endif #define CONFIG_SPL_MMC_BOOT diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 6ba2a03f0c..1d18316a41 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_T4240QDS - #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE4 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ @@ -544,7 +542,7 @@ unsigned long get_board_ddr_clk(void); * interleaving. It can be cacheline, page, bank, superbank. * See doc/README.fsl-ddr for details. */ -#ifdef CONFIG_PPC_T4240 +#ifdef CONFIG_ARCH_T4240 #define CTRL_INTLV_PREFERED 3way_4KB #else #define CTRL_INTLV_PREFERED cacheline diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 2fac19fc22..6c743e3ccc 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_T4240RDB - #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE4 @@ -734,7 +732,7 @@ unsigned long get_board_ddr_clk(void); * interleaving. It can be cacheline, page, bank, superbank. * See doc/README.fsl-ddr for details. */ -#ifdef CONFIG_PPC_T4240 +#ifdef CONFIG_ARCH_T4240 #define CTRL_INTLV_PREFERED 3way_4KB #else #define CTRL_INTLV_PREFERED cacheline diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index ce1cf97cf0..1163b0dbd2 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -27,7 +27,6 @@ #define CONFIG_UCP1020_REV_1_3 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1" -#define CONFIG_P1020 #define CONFIG_TSEC_ENET #define CONFIG_TSEC1 @@ -59,7 +58,6 @@ #define CONFIG_UCP1020_REV_1_3 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" -#define CONFIG_P1020 #define CONFIG_TSEC_ENET #define CONFIG_TSEC1 diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 5e1f1b0139..b824e3bd23 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -37,7 +37,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_P1022 #define CONFIG_CONTROLCENTERD #define CONFIG_MP /* support multiple processors */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 3807d456c7..67a503482d 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -24,13 +24,13 @@ #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg -#if defined(CONFIG_P3041DS) +#if defined(CONFIG_TARGET_P3041DS) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg -#elif defined(CONFIG_P4080DS) +#elif defined(CONFIG_TARGET_P4080DS) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg -#elif defined(CONFIG_P5020DS) +#elif defined(CONFIG_TARGET_P5020DS) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg -#elif defined(CONFIG_P5040DS) +#elif defined(CONFIG_TARGET_P5040DS) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg #endif #endif @@ -680,7 +680,7 @@ #define CONFIG_BAUDRATE 115200 -#ifdef CONFIG_P4080DS +#ifdef CONFIG_TARGET_P4080DS #define __USB_PHY_TYPE ulpi #else #define __USB_PHY_TYPE utmi diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 4a11092687..13e4690bc9 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -9,7 +9,7 @@ #define CONFIG_CYRUS -#if !defined(CONFIG_PPC_P5020) && !defined(CONFIG_PPC_P5040) +#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040) #error Must call Cyrus CONFIG with a specific CPU enabled. #endif @@ -18,7 +18,7 @@ #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE3 #define CONFIG_PCIE4 -#ifdef CONFIG_PPC_P5020 +#ifdef CONFIG_ARCH_P5020 #define CONFIG_SYS_FSL_RAID_ENGINE #define CONFIG_SYS_DPAA_RMAN #endif @@ -30,10 +30,10 @@ #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg -#if defined(CONFIG_PPC_P5020) +#if defined(CONFIG_ARCH_P5020) #define CONFIG_SYS_CLK_FREQ 133000000 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg -#elif defined(CONFIG_PPC_P5040) +#elif defined(CONFIG_ARCH_P5040) #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg #endif diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index f557ee2117..fad8865353 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -8,8 +8,6 @@ #ifndef _CONFIG_KMP204X_H #define _CONFIG_KMP204X_H -#define CONFIG_PPC_P2041 - #define CONFIG_SYS_TEXT_BASE 0xfff40000 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 523af5265f..77f3d81593 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -10,9 +10,8 @@ #ifndef __CONFIG_H #define __CONFIG_H -#if defined(CONFIG_P1020MBG) +#if defined(CONFIG_TARGET_P1020MBG) #define CONFIG_BOARDNAME "P1020MBG-PC" -#define CONFIG_P1020 #define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 @@ -21,19 +20,17 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P1020UTM) +#if defined(CONFIG_TARGET_P1020UTM) #define CONFIG_BOARDNAME "P1020UTM-PC" -#define CONFIG_P1020 #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xe0 #define __SW_BOOT_SD 0x50 #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P1020RDB_PC) +#if defined(CONFIG_TARGET_P1020RDB_PC) #define CONFIG_BOARDNAME "P1020RDB-PC" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1020 #define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 @@ -58,10 +55,9 @@ * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off */ -#if defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_BOARDNAME "P1020RDB-PD" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1020 #define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 @@ -83,10 +79,9 @@ "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" #endif -#if defined(CONFIG_P1021RDB) +#if defined(CONFIG_TARGET_P1021RDB) #define CONFIG_BOARDNAME "P1021RDB-PC" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1021 #define CONFIG_QE #define CONFIG_VSC7385_ENET #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of @@ -118,10 +113,9 @@ #endif #endif -#if defined(CONFIG_P1024RDB) +#if defined(CONFIG_TARGET_P1024RDB) #define CONFIG_BOARDNAME "P1024RDB" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1024 #define CONFIG_SLIC #define __SW_BOOT_MASK 0xf3 #define __SW_BOOT_NOR 0x00 @@ -131,10 +125,9 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P1025RDB) +#if defined(CONFIG_TARGET_P1025RDB) #define CONFIG_BOARDNAME "P1025RDB" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1025 #define CONFIG_QE #define CONFIG_SLIC @@ -148,10 +141,9 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P2020RDB) -#define CONFIG_BOARDNAME "P2020RDB-PCA" +#if defined(CONFIG_TARGET_P2020RDB) +#define CONFIG_BOARDNAME "P2020RDB-PC" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P2020 #define CONFIG_VSC7385_ENET #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xc8 @@ -292,7 +284,7 @@ #define CONFIG_LIBATA #define CONFIG_LBA48 -#if defined(CONFIG_P2020RDB) +#if defined(CONFIG_TARGET_P2020RDB) #define CONFIG_SYS_CLK_FREQ 100000000 #else #define CONFIG_SYS_CLK_FREQ 66666666 @@ -336,7 +328,7 @@ #define SPD_EEPROM_ADDRESS 0x52 #undef CONFIG_FSL_DDR_INTERACTIVE -#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) +#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G #define CONFIG_CHIP_SELECTS_PER_CTRL 2 #else @@ -351,7 +343,7 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Default settings for DDR3 */ -#ifndef CONFIG_P2020RDB +#ifndef CONFIG_TARGET_P2020RDB #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 @@ -406,10 +398,10 @@ /* * Local Bus Definitions */ -#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) +#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ #define CONFIG_SYS_FLASH_BASE 0xec000000 -#elif defined(CONFIG_P1020UTM) +#elif defined(CONFIG_TARGET_P1020UTM) #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ #define CONFIG_SYS_FLASH_BASE 0xee000000 #else @@ -455,7 +447,7 @@ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_CMD_NAND -#if defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) #else #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) @@ -466,7 +458,7 @@ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#if defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ | OR_FCM_PGS /* Large Page*/ \ | OR_FCM_CSCT \ @@ -584,7 +576,7 @@ #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) -#if defined(CONFIG_P2020RDB) +#if defined(CONFIG_TARGET_P2020RDB) #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) #else #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) @@ -755,7 +747,7 @@ #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #endif /* CONFIG_QE */ -#ifdef CONFIG_P1025RDB +#ifdef CONFIG_TARGET_P1025RDB /* * QE UEC ethernet configuration */ @@ -789,7 +781,7 @@ #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 #endif /* CONFIG_UEC_ETH5 */ -#endif /* CONFIG_P1025RDB */ +#endif /* CONFIG_TARGET_P1025RDB */ /* * Environment @@ -853,7 +845,7 @@ #endif #endif -#if defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index ef32181277..c122f8e0d8 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -12,7 +12,6 @@ #if defined(CONFIG_TWR_P1025) #define CONFIG_BOARDNAME "TWR-P1025" -#define CONFIG_P1025 #define CONFIG_PHY_ATHEROS #define CONFIG_QE #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index a7f2a9dc9c..2c85f65fc8 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -15,7 +15,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_QEMU_E500 #undef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xf01000 /* 15 MB */ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index e9f9d30d52..008781ee35 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -38,7 +38,6 @@ */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8548 1 /* MPC8548 specific */ #define CONFIG_SBC8548 1 /* SBC8548 board specific */ /* diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 361c96c0fb..2bd89f40fe 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -21,7 +21,6 @@ #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_SBC8641D 1 /* SBC8641D board specific */ #define CONFIG_MP 1 /* support multiple processors */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 753ccfb01e..c697f63162 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -20,7 +20,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8544 1 #define CONFIG_SOCRATES 1 #define CONFIG_SYS_TEXT_BASE 0xfff80000 diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 027440ae93..6d957896e6 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -14,7 +14,6 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */ #define CONFIG_SYS_BOARD_NAME "XPedite5170" #define CONFIG_SYS_FORM_3U_VPX 1 diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index d980c1515e..7f6927bcb8 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -16,7 +16,6 @@ */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8548 1 #define CONFIG_XPEDITE5200 1 #define CONFIG_SYS_BOARD_NAME "XPedite5200" #define CONFIG_SYS_FORM_PMC_XMC 1 diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index a82eef5b32..a6bdffc582 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -16,8 +16,6 @@ */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8572 1 -#define CONFIG_XPEDITE5370 1 #define CONFIG_SYS_BOARD_NAME "XPedite5370" #define CONFIG_SYS_FORM_3U_VPX 1 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 973089b5a9..f12f8fe1d0 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -16,7 +16,6 @@ */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_P2020 1 #define CONFIG_XPEDITE550X 1 #define CONFIG_SYS_BOARD_NAME "XPedite5500" #define CONFIG_SYS_FORM_PMC_XMC 1 diff --git a/include/fsl_sec.h b/include/fsl_sec.h index bffabc89b9..e6080d4ff0 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -303,7 +303,7 @@ struct sg_entry { */ int blob_dek(const u8 *src, u8 *dst, u8 len); -#if defined(CONFIG_PPC_C29X) +#if defined(CONFIG_ARCH_C29X) int sec_init_idx(uint8_t); #endif int sec_init(void); diff --git a/include/keyboard.h b/include/keyboard.h index 6725e487bc..5cbd9f8ba8 100644 --- a/include/keyboard.h +++ b/include/keyboard.h @@ -98,8 +98,8 @@ extern int kbd_init_hw(void); extern void pckbd_leds(unsigned char leds); #endif /* !CONFIG_DM_KEYBOARD */ -#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || \ - defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#if defined(CONFIG_MPC5xxx) || defined(CONFIG_ARCH_MPC8540) || \ + defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) int ps2ser_check(void); #endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index d0b5e7f3e4..b3ed48b82f 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -291,7 +291,6 @@ CONFIG_AUTOCALIB CONFIG_AUTONEG_TIMEOUT CONFIG_AUTO_COMPLETE CONFIG_AUTO_ZRELADDR -CONFIG_B4860QDS CONFIG_BACKSIDE_L2_CACHE CONFIG_BAMBOO CONFIG_BAMBOO_NAND @@ -451,10 +450,6 @@ CONFIG_BOOT_RETRY_MIN CONFIG_BOOT_RETRY_TIME CONFIG_BOUNCE_BUFFER CONFIG_BPTR_VIRT_ADDR -CONFIG_BSC9131 -CONFIG_BSC9131RDB -CONFIG_BSC9132 -CONFIG_BSC9132QDS CONFIG_BSEIP CONFIG_BS_ADDR_DEVICE CONFIG_BS_ADDR_RAM @@ -471,7 +466,6 @@ CONFIG_BUILD_ENVCRC CONFIG_BUILD_TARGET CONFIG_BUS_WIDTH CONFIG_BZIP2 -CONFIG_C29XPCIE CONFIG_CACHELINE_ALIGNED_L1 CONFIG_CADDY2 CONFIG_CALXEDA_XGMAC @@ -3145,38 +3139,14 @@ CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN CONFIG_MPC83XX_GPIO_1_INIT_VALUE CONFIG_MPC83XX_PCI2 CONFIG_MPC850 -CONFIG_MPC8536 -CONFIG_MPC8536DS -CONFIG_MPC8540 -CONFIG_MPC8540ADS -CONFIG_MPC8541 -CONFIG_MPC8541CDS -CONFIG_MPC8544 -CONFIG_MPC8544DS -CONFIG_MPC8548 -CONFIG_MPC8548CDS CONFIG_MPC855 -CONFIG_MPC8555 -CONFIG_MPC8555CDS -CONFIG_MPC8560 -CONFIG_MPC8560ADS -CONFIG_MPC8568 -CONFIG_MPC8568MDS -CONFIG_MPC8569 -CONFIG_MPC8569MDS CONFIG_MPC857 -CONFIG_MPC8572 -CONFIG_MPC8572DS CONFIG_MPC85XX_FEC CONFIG_MPC85XX_FEC_NAME CONFIG_MPC85XX_PCI2 CONFIG_MPC860 CONFIG_MPC860T -CONFIG_MPC8610 -CONFIG_MPC8610HPCD CONFIG_MPC862 -CONFIG_MPC8641 -CONFIG_MPC8641HPCN CONFIG_MPC866 CONFIG_MPC866_FAMILY CONFIG_MPC86x @@ -3408,30 +3378,6 @@ CONFIG_OS2_ENV_ADDR CONFIG_OS_ENV_ADDR CONFIG_OTHBOOTARGS CONFIG_OVERWRITE_ETHADDR_ONCE -CONFIG_P1010 -CONFIG_P1010RDB_PA -CONFIG_P1010RDB_PB -CONFIG_P1020 -CONFIG_P1020MBG -CONFIG_P1020RDB_PC -CONFIG_P1020RDB_PD -CONFIG_P1020UTM -CONFIG_P1021 -CONFIG_P1021RDB -CONFIG_P1022 -CONFIG_P1022DS -CONFIG_P1023 -CONFIG_P1024 -CONFIG_P1024RDB -CONFIG_P1025 -CONFIG_P1025RDB -CONFIG_P2020 -CONFIG_P2020RDB -CONFIG_P2041RDB -CONFIG_P3041DS -CONFIG_P4080DS -CONFIG_P5020DS -CONFIG_P5040DS CONFIG_PAGE_CNT_MASK CONFIG_PAGE_CNT_SHIFT CONFIG_PALMAS_AUDPWR @@ -3688,24 +3634,8 @@ CONFIG_PPC4xx_DDR_AUTOCALIBRATION CONFIG_PPC4xx_DDR_METHOD_A CONFIG_PPC4xx_EMAC CONFIG_PPC64BRIDGE -CONFIG_PPC_B4420 -CONFIG_PPC_B4860 -CONFIG_PPC_C29X CONFIG_PPC_CLUSTER_START -CONFIG_PPC_P2041 -CONFIG_PPC_P3041 -CONFIG_PPC_P4080 -CONFIG_PPC_P5020 -CONFIG_PPC_P5040 CONFIG_PPC_SPINTABLE_COMPATIBLE -CONFIG_PPC_T1023 -CONFIG_PPC_T1024 -CONFIG_PPC_T1040 -CONFIG_PPC_T1042 -CONFIG_PPC_T2080 -CONFIG_PPC_T2081 -CONFIG_PPC_T4160 -CONFIG_PPC_T4240 CONFIG_PQ_MDS_PIB CONFIG_PQ_MDS_PIB_ATM CONFIG_PRAM @@ -3746,7 +3676,6 @@ CONFIG_PXA_VIDEO CONFIG_P_CLK_FREQ CONFIG_QBMAN_CLK_DIV CONFIG_QE -CONFIG_QEMU_E500 CONFIG_QEMU_MIPS CONFIG_QIXIS_I2C_ACCESS CONFIG_QSPI @@ -7887,19 +7816,10 @@ CONFIG_SYS_ZYNQ_SPI_WAIT CONFIG_SYS_i2C_FSL CONFIG_T1023RDB CONFIG_T1024RDB -CONFIG_T1040D4RDB CONFIG_T1040QDS -CONFIG_T1040RDB -CONFIG_T1042D4RDB -CONFIG_T1042RDB -CONFIG_T1042RDB_PI -CONFIG_T104XD4RDB -CONFIG_T104xRDB CONFIG_T2080QDS CONFIG_T2080RDB CONFIG_T2081QDS -CONFIG_T4240QDS -CONFIG_T4240RDB CONFIG_TAM3517_SETTINGS CONFIG_TAM3517_SW3_SETTINGS CONFIG_TCA642X @@ -8311,7 +8231,6 @@ CONFIG_XILINX_TB_WATCHDOG CONFIG_XPEDITE1000 CONFIG_XPEDITE5140 CONFIG_XPEDITE5200 -CONFIG_XPEDITE5370 CONFIG_XPEDITE550X CONFIG_XR16L2751 CONFIG_XSENGINE diff --git a/tools/envcrc.c b/tools/envcrc.c index a9d9b48c76..e9fd088ff2 100644 --- a/tools/envcrc.c +++ b/tools/envcrc.c @@ -12,6 +12,8 @@ #include <string.h> #include <unistd.h> +#include <linux/kconfig.h> + #ifndef __ASSEMBLY__ #define __ASSEMBLY__ /* Dirty trick to get only #defines */ #endif |