diff options
| author | Tom Rini <trini@konsulko.com> | 2017-12-11 17:05:43 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-12-11 17:05:43 -0500 |
| commit | 6f1ee8a4bf72d4824cea25849f775ab487ddd579 (patch) | |
| tree | 9d4f6ad7ca865c4b7a01f3b0ebd19c047cf6230d /arch/arc | |
| parent | 335f7b1290ce24a729a9689a1db834c743226ca8 (diff) | |
| parent | e80dac0ab83ccb1d54e2d91b93d27b54a7f6544f (diff) | |
Merge git://git.denx.de/u-boot-arc
Diffstat (limited to 'arch/arc')
| -rw-r--r-- | arch/arc/include/asm/arcregs.h | 9 | ||||
| -rw-r--r-- | arch/arc/include/asm/gpio.h | 1 | ||||
| -rw-r--r-- | arch/arc/lib/cache.c | 16 |
3 files changed, 18 insertions, 8 deletions
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 54a9b00d4c..ba1f7bac77 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -27,6 +27,12 @@ #define ARC_AUX_IC_PTAG 0x1E #endif #define ARC_BCR_IC_BUILD 0x77 +#define AUX_AUX_CACHE_LIMIT 0x5D +#define ARC_AUX_NON_VOLATILE_LIMIT 0x5E + +/* ICCM and DCCM auxiliary registers */ +#define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */ +#define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */ /* Timer related auxiliary registers */ #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ @@ -72,6 +78,9 @@ /* gcc builtin sr needs reg param to be long immediate */ #define write_aux_reg(reg_immed, val) \ __builtin_arc_sr((unsigned int)val, reg_immed) + +/* ARCNUM [15:8] - field to identify each core in a multi-core system */ +#define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8) #endif /* __ASSEMBLY__ */ #endif /* _ASM_ARC_ARCREGS_H */ diff --git a/arch/arc/include/asm/gpio.h b/arch/arc/include/asm/gpio.h new file mode 100644 index 0000000000..306ab4c9f2 --- /dev/null +++ b/arch/arc/include/asm/gpio.h @@ -0,0 +1 @@ +#include <asm-generic/gpio.h> diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index d8741fe959..1073e1570f 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -32,15 +32,15 @@ * relocation but will be used after being zeroed. */ int l1_line_sz __section(".data"); -int dcache_exists __section(".data"); -int icache_exists __section(".data"); +bool dcache_exists __section(".data") = false; +bool icache_exists __section(".data") = false; #define CACHE_LINE_MASK (~(l1_line_sz - 1)) #ifdef CONFIG_ISA_ARCV2 int slc_line_sz __section(".data"); -int slc_exists __section(".data"); -int ioc_exists __section(".data"); +bool slc_exists __section(".data") = false; +bool ioc_exists __section(".data") = false; static unsigned int __before_slc_op(const int op) { @@ -152,7 +152,7 @@ static void read_decode_cache_bcr_arcv2(void) sbcr.word = read_aux_reg(ARC_BCR_SLC); if (sbcr.fields.ver) { slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); - slc_exists = 1; + slc_exists = true; slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; } @@ -169,7 +169,7 @@ static void read_decode_cache_bcr_arcv2(void) cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); if (cbcr.fields.c) - ioc_exists = 1; + ioc_exists = true; } #endif @@ -190,7 +190,7 @@ void read_decode_cache_bcr(void) ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); if (ibcr.fields.ver) { - icache_exists = 1; + icache_exists = true; l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; if (!ic_line_sz) panic("Instruction exists but line length is 0\n"); @@ -198,7 +198,7 @@ void read_decode_cache_bcr(void) dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); if (dbcr.fields.ver){ - dcache_exists = 1; + dcache_exists = true; l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; if (!dc_line_sz) panic("Data cache exists but line length is 0\n"); |