diff options
| author | Mingkai Hu <mingkai.hu@nxp.com> | 2016-09-07 17:56:08 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-09-14 14:10:02 -0700 |
| commit | 13f7988067856845ef593795003160db5ccf43cd (patch) | |
| tree | a5bc36d5777e7938a0c7198fd9e94b3d9174f70e /arch/arm/cpu/arm946es/cpu.c | |
| parent | 9578c4273d4b9d24403bf4e03d7729f381527cd8 (diff) | |
armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latency
According to design specification, the L2 cache operates at the same
frequency as the A72 CPUs in the cluster with a 3-cycle latency, so
increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else,
will run into different call trace issues.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/arm946es/cpu.c')
0 files changed, 0 insertions, 0 deletions