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authorTom Rini <trini@ti.com>2014-11-24 12:02:12 -0500
committerTom Rini <trini@ti.com>2014-11-24 12:02:12 -0500
commitdee332ffb735f65ab922118791a583c17bb0b795 (patch)
treed07bc0821792831aa4baeb27868252c2d32c7738 /arch/arm/cpu/armv7/mx6/clock.c
parent1739564e753bc3a8097f8937a3cbe738bdaaed5d (diff)
parente7eb277dced570f177d75d56f40219d9dc599ed1 (diff)
Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Diffstat (limited to 'arch/arm/cpu/armv7/mx6/clock.c')
-rw-r--r--arch/arm/cpu/armv7/mx6/clock.c38
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 6c9c78c11a..ab7ac3d703 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -596,6 +596,14 @@ int enable_sata_clock(void)
ungate_sata_clock();
return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
}
+
+void disable_sata_clock(void)
+{
+ struct mxc_ccm_reg *const imx_ccm =
+ (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
+}
#endif
int enable_pcie_clock(void)
@@ -673,6 +681,36 @@ void hab_caam_clock_enable(unsigned char enable)
}
#endif
+static void enable_pll3(void)
+{
+ struct anatop_regs __iomem *anatop =
+ (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+
+ /* make sure pll3 is enabled */
+ if ((readl(&anatop->usb1_pll_480_ctrl) &
+ BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
+ /* enable pll's power */
+ writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
+ &anatop->usb1_pll_480_ctrl_set);
+ writel(0x80, &anatop->ana_misc2_clr);
+ /* wait for pll lock */
+ while ((readl(&anatop->usb1_pll_480_ctrl) &
+ BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
+ ;
+ /* disable bypass */
+ writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
+ &anatop->usb1_pll_480_ctrl_clr);
+ /* enable pll output */
+ writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
+ &anatop->usb1_pll_480_ctrl_set);
+ }
+}
+
+void enable_thermal_clk(void)
+{
+ enable_pll3();
+}
+
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {