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| author | Chuanhua Han <chuanhua.han@nxp.com> | 2019-08-08 17:04:58 +0800 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2019-09-12 16:15:42 +0530 |
| commit | 2f2a19757b4d74cb7af1f5d35dac05a9ac04acc7 (patch) | |
| tree | a6676cd268746df89340f6ace9cec6a3282d9031 /arch/arm/dts/zynqmp-zc1232-revA.dts | |
| parent | 412e25ab5faafcfe8bca263b44e347566075317e (diff) | |
armv8: fsl-layerscape: Update I2C clock divider
By default, i2c input clock is programmed at
platform clk / 2 in u-boot, but this is not
correct for all the platforms,
Update I2C clock divider's default values as per
SoC (LS1012A, LS1028A, LX2160A and LS1088A).
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch/arm/dts/zynqmp-zc1232-revA.dts')
0 files changed, 0 insertions, 0 deletions