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authorTom Rini <trini@konsulko.com>2020-04-13 11:27:00 -0400
committerTom Rini <trini@konsulko.com>2020-04-13 11:27:00 -0400
commit891483186052b259852f3f48926ff307763f4eb0 (patch)
tree019e4a490e40ad5459f7dd3d4129021be696c495 /arch/arm/dts/zynqmp-zcu102-revA.dts
parent36fec02b1f90b92cf51ec531564f9284eae27ab4 (diff)
parent67bbc1ecd311c78b06e845a3fd4e333806782367 (diff)
Merge branch 'next'
Pull in changes that have been pending in our 'next' branch. This includes: - A large number of CI improvements including moving to gcc-9.2 for all platforms. - amlogic, xilinx, stm32, TI SoC updates - USB and i2c subsystem updtaes - Re-sync Kbuild/etc logic with v4.19 of the Linux kernel. - RSA key handling improvements
Diffstat (limited to 'arch/arm/dts/zynqmp-zcu102-revA.dts')
-rw-r--r--arch/arm/dts/zynqmp-zcu102-revA.dts36
1 files changed, 15 insertions, 21 deletions
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index b580f9263d..d250681600 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU102 RevA
*
- * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ * (C) Copyright 2015 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@@ -614,19 +614,19 @@
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
- partition@qspi-fsbl-uboot { /* for testing purpose */
+ partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
- partition@qspi-linux { /* for testing purpose */
+ partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
- partition@qspi-device-tree { /* for testing purpose */
+ partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
- partition@qspi-rootfs { /* for testing purpose */
+ partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};
@@ -655,7 +655,11 @@
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
- no-1-8-v; /* for 1.0 silicon */
+ /*
+ * 1.0 revision has level shifter and this property should be
+ * removed for supporting UHS mode
+ */
+ no-1-8-v;
xlnx,mio_bank = <1>;
};
@@ -701,33 +705,23 @@
status = "okay";
};
-&xilinx_drm {
+&zynqmp_dpsub {
status = "okay";
- clocks = <&si570_1>;
};
-&xlnx_dp {
+&zynqmp_dp_snd_codec0 {
status = "okay";
};
-&xlnx_dp_sub {
+&zynqmp_dp_snd_pcm0 {
status = "okay";
- xlnx,vid-clk-pl;
};
-&xlnx_dp_snd_pcm0 {
+&zynqmp_dp_snd_pcm1 {
status = "okay";
};
-&xlnx_dp_snd_pcm1 {
- status = "okay";
-};
-
-&xlnx_dp_snd_card {
- status = "okay";
-};
-
-&xlnx_dp_snd_codec0 {
+&zynqmp_dp_snd_card0 {
status = "okay";
};