diff options
| author | Stefano Babic <sbabic@denx.de> | 2016-11-29 16:28:28 +0100 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-11-29 16:28:28 +0100 |
| commit | 2d221489df021393654805536be7effcb9d39702 (patch) | |
| tree | 1b636f10b4ccde42624ec665df13288408b59b7f /arch/arm/dts | |
| parent | 45a3ad81fafe3090f7f89b458f6bd9f547a453df (diff) | |
| parent | e94793c844a40606252f2e3f6428063e057b3fd2 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/dts')
35 files changed, 1362 insertions, 162 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 836a8c4d1e..ae47d8127c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -28,14 +28,16 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5422-odroidxu3.dtb dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ + rk3036-sdk.dtb \ rk3288-firefly.dtb \ - rk3288-jerry.dtb \ + rk3288-veyron-jerry.dtb \ + rk3288-veyron-mickey.dtb \ + rk3288-veyron-minnie.dtb \ rk3288-rock2-square.dtb \ rk3288-evb.dtb \ rk3288-fennec.dtb \ rk3288-miniarm.dtb \ rk3288-popmetal.dtb \ - rk3036-sdk.dtb \ rk3399-evb.dtb dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-odroidc2.dtb @@ -97,6 +99,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-zybo.dtb \ zynq-microzed.dtb \ zynq-picozed.dtb \ + zynq-topic-miami.dtb \ + zynq-topic-miamiplus.dtb \ zynq-zc770-xm010.dtb \ zynq-zc770-xm011.dtb \ zynq-zc770-xm012.dtb \ @@ -141,13 +145,15 @@ dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb dtb-$(CONFIG_LS102XA) += ls1021a-qds-duart.dtb \ ls1021a-qds-lpuart.dtb \ - ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb + ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ + ls1021a-iot-duart.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2080a-rdb.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ fsl-ls1046a-qds-duart.dtb \ + fsl-ls1046a-qds-lpuart.dtb \ fsl-ls1046a-rdb.dtb \ fsl-ls1012a-qds.dtb \ fsl-ls1012a-rdb.dtb \ @@ -254,6 +260,7 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \ sun8i-a33-olinuxino.dtb \ sun8i-a33-q8-tablet.dtb \ sun8i-a33-sinlinx-sina33.dtb \ + sun8i-r16-nintendo-nes-classic-edition.dtb \ sun8i-r16-parrot.dtb dtb-$(CONFIG_MACH_SUN8I_A83T) += \ sun8i-a83t-allwinner-h8homlet-v2.dtb \ diff --git a/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts new file mode 100644 index 0000000000..21243d0766 --- /dev/null +++ b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts @@ -0,0 +1,16 @@ +/* + * Device Tree file for Freescale Layerscape-1046A family SoC. + * + * Copyright (C) 2016, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "fsl-ls1046a-qds.dtsi" + +/ { + chosen { + stdout-path = &lpuart0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi index c5122930fe..a49ca08d88 100644 --- a/arch/arm/dts/fsl-ls1046a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi @@ -75,3 +75,7 @@ &duart1 { status = "okay"; }; + +&lpuart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 87dd9976d1..359a9d13bf 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -151,6 +151,60 @@ clocks = <&clockgen 4 0>; }; + lpuart0: serial@2950000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2950000 0x0 0x1000>; + interrupts = <0 48 0x4>; + clocks = <&clockgen 4 0>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart1: serial@2960000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2960000 0x0 0x1000>; + interrupts = <0 49 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@2970000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2970000 0x0 0x1000>; + interrupts = <0 50 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart3: serial@2980000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2980000 0x0 0x1000>; + interrupts = <0 51 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart4: serial@2990000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2990000 0x0 0x1000>; + interrupts = <0 52 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@29a0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x29a0000 0x0 0x1000>; + interrupts = <0 53 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + qspi: quadspi@1550000 { compatible = "fsl,vf610-qspi"; #address-cells = <1>; diff --git a/arch/arm/dts/ls1021a-iot-duart.dts b/arch/arm/dts/ls1021a-iot-duart.dts new file mode 100644 index 0000000000..62e4c67040 --- /dev/null +++ b/arch/arm/dts/ls1021a-iot-duart.dts @@ -0,0 +1,16 @@ +/* + * Freescale ls1021a IOT board device tree source + * + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "ls1021a-iot.dtsi" + +/ { + chosen { + stdout-path = &uart0; + }; +}; diff --git a/arch/arm/dts/ls1021a-iot.dtsi b/arch/arm/dts/ls1021a-iot.dtsi new file mode 100644 index 0000000000..1817c62c04 --- /dev/null +++ b/arch/arm/dts/ls1021a-iot.dtsi @@ -0,0 +1,103 @@ +/* + * Freescale ls1021a IOT board device tree source + * + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include "ls1021a.dtsi" + +/ { + model = "LS1021A IOT Board"; + + aliases { + enet2_rgmii_phy = &rgmii_phy1; + enet0_sgmii_phy = &sgmii_phy2; + enet1_sgmii_phy = &sgmii_phy0; + spi0 = &qspi; + spi1 = &dspi1; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: n25q128a13@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&dspi1 { + bus-num = <0>; + status = "okay"; + + dspiflash: at26df081a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <16000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR Flash on board */ + ranges = <0x0 0x0 0x60000000 0x08000000>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; +}; + +&lpuart0 { + status = "okay"; +}; + +&mdio0 { + sgmii_phy0: ethernet-phy@0 { + reg = <0x0>; + }; + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + sgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + tbi1: tbi-phy@1f { + reg = <0x1f>; + device_type = "tbi-phy"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3036-sdk.dts b/arch/arm/dts/rk3036-sdk.dts index 1c9ddf9856..bdc7b980b0 100644 --- a/arch/arm/dts/rk3036-sdk.dts +++ b/arch/arm/dts/rk3036-sdk.dts @@ -16,10 +16,25 @@ stdout-path = &uart2; }; - usb_control { - compatible = "rockchip,rk3036-usb-control"; - host_drv_gpio = <&gpio2 23 GPIO_ACTIVE_LOW>; - otg_drv_gpio = <&gpio0 26 GPIO_ACTIVE_LOW>; + vcc5v0_otg: vcc5v0-otg-drv { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_host: vcc5v0-host-drv { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; }; }; @@ -42,3 +57,17 @@ &usb_otg { status = "okay"; }; + +&pinctrl { + usb_otg { + otg_vbus_drv: host-vbus-drv { + rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_host { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/dts/rk3288-veyron-chromebook.dtsi index bbbc2f408d..f88a8680bf 100644 --- a/arch/arm/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/dts/rk3288-veyron-chromebook.dtsi @@ -13,6 +13,8 @@ / { aliases { i2c20 = &i2c_tunnel; + video0 = &vopl; + video1 = &vopb; }; gpio_keys: gpio-keys { diff --git a/arch/arm/dts/rk3288-jerry.dts b/arch/arm/dts/rk3288-veyron-jerry.dts index 2aa3b9f971..8aab607cc5 100644 --- a/arch/arm/dts/rk3288-jerry.dts +++ b/arch/arm/dts/rk3288-veyron-jerry.dts @@ -55,6 +55,17 @@ }; }; +&dmc { + rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; +}; + &gpio_keys { power { gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; @@ -108,11 +119,6 @@ pinctrl-0 = <&vcc50_hdmi_en>; }; -&vopb { - /* Disable this so that we use vopl */ - status = "disabled"; -}; - &edp { pinctrl-names = "default"; pinctrl-0 = <&edp_hpd>; diff --git a/arch/arm/dts/rk3288-veyron-mickey.dts b/arch/arm/dts/rk3288-veyron-mickey.dts new file mode 100644 index 0000000000..e0dc362061 --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-mickey.dts @@ -0,0 +1,277 @@ +/* + * Google Veyron Mickey Rev 0 board device tree source + * + * Copyright 2015 Google, Inc + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3288-veyron-chromebook.dtsi" + +/ { + model = "Google Mickey"; + compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7", + "google,veyron-mickey-rev6", "google,veyron-mickey-rev5", + "google,veyron-mickey-rev4", "google,veyron-mickey-rev3", + "google,veyron-mickey-rev2", "google,veyron-mickey-rev1", + "google,veyron-mickey-rev0", "google,veyron-mickey", + "google,veyron", "rockchip,rk3288"; + + vcc_5v: vcc-5v { + vin-supply = <&vcc33_sys>; + }; + + vcc33_io: vcc33_io { + compatible = "regulator-fixed"; + regulator-name = "vcc33_io"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc33_sys>; + }; +}; + +&cpu_thermal { + /delete-node/ trips; + /delete-node/ cooling-maps; + + trips { + cpu_alert_almost_warm: cpu_alert_almost_warm { + temperature = <63000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert_warm: cpu_alert_warm { + temperature = <65000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert_almost_hot: cpu_alert_almost_hot { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert_hot: cpu_alert_hot { + temperature = <82000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert_hotter: cpu_alert_hotter { + temperature = <84000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert_very_hot: cpu_alert_very_hot { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + /* + * After 1st level, throttle the CPU down to as low as 1.4 GHz + * and don't let the GPU go faster than 400 MHz. Note that we + * won't throttle the GPU lower than 400 MHz due to CPU + * heat--we'll let the GPU do the rest itself. + */ + cpu_warm_limit_cpu { + trip = <&cpu_alert_warm>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT 4>; + }; + + /* + * Add some discrete steps to help throttling system deal + * with the fact that there are two passive cooling devices: + * the CPU and the GPU. + * + * - 1.2 GHz - 1.0 GHz (almost hot) + * - 800 MHz (hot) + * - 800 MHz - 696 MHz (hotter) + * - 696 MHz - min (very hot) + * + * Note: + * - 800 MHz appears to be a "sweet spot" for me. I can run + * some pretty serious workload here and be happy. + * - After 696 MHz we stop lowering voltage, so throttling + * past there is less effective. + */ + cpu_almost_hot_limit_cpu { + trip = <&cpu_alert_almost_hot>; + cooling-device = + <&cpu0 5 6>; + }; + cpu_hot_limit_cpu { + trip = <&cpu_alert_hot>; + cooling-device = + <&cpu0 7 7>; + }; + cpu_hotter_limit_cpu { + trip = <&cpu_alert_hotter>; + cooling-device = + <&cpu0 7 8>; + }; + cpu_very_hot_limit_cpu { + trip = <&cpu_alert_very_hot>; + cooling-device = + <&cpu0 8 THERMAL_NO_LIMIT>; + }; + }; +}; + +&dmc { + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x2>; + rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 1>; +}; + +&emmc { + /delete-property/mmc-hs200-1_8v; +}; + +&i2c2 { + status = "disabled"; +}; + +&i2c4 { + status = "disabled"; +}; + +&i2s { + status = "okay"; + clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out"; + clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>; +}; + +&rk808 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; + dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>, + <&gpio7 15 GPIO_ACTIVE_HIGH>; + + /delete-property/ vcc6-supply; + /delete-property/ vcc12-supply; + + vcc11-supply = <&vcc33_sys>; + + regulators { + /* vcc33_io is sourced directly from vcc33_sys */ + /delete-node/ LDO_REG1; + /delete-node/ LDO_REG7; + + /* This is not a pwren anymore, but the real power supply */ + vdd10_lcd: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-suspend-mem-disabled; + }; + + vcc18_lcd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-suspend-mem-disabled; + }; + }; +}; + +&pinctrl { + hdmi { + power_hdmi_on: power-hdmi-on { + rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&sdmmc { + status = "disabled"; +}; + +&sdio0 { + status = "disabled"; +}; + +&sdmmc { + status = "disabled"; +}; + +&spi0 { + status = "disabled"; +}; + +&usb_host0_ehci { + status = "disabled"; +}; + +&usb_host1 { + status = "disabled"; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&power_hdmi_on>; +}; diff --git a/arch/arm/dts/rk3288-veyron-minnie.dts b/arch/arm/dts/rk3288-veyron-minnie.dts new file mode 100644 index 0000000000..0a2915fba0 --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-minnie.dts @@ -0,0 +1,301 @@ +/* + * Google Veyron Minnie Rev 0+ board device tree source + * + * Copyright 2015 Google, Inc + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3288-veyron-chromebook.dtsi" + +/ { + model = "Google Minnie"; + compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3", + "google,veyron-minnie-rev2", "google,veyron-minnie-rev1", + "google,veyron-minnie-rev0", "google,veyron-minnie", + "google,veyron", "rockchip,rk3288"; + + backlight_regulator: backlight-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_pwr_en>; + regulator-name = "backlight_regulator"; + vin-supply = <&vcc33_sys>; + startup-delay-us = <15000>; + }; + + panel_regulator: panel-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_h>; + regulator-name = "panel_regulator"; + startup-delay-us = <100000>; + vin-supply = <&vcc33_sys>; + }; + + vcc18_lcd: vcc18-lcd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&avdd_1v8_disp_en>; + regulator-name = "vcc18_lcd"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc18_wl>; + }; +}; + +&backlight { + /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */ + brightness-levels = < + 0 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + power-supply = <&backlight_regulator>; +}; + +&dmc { + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x1>; + rockchip,sdram-params = <0x20d266a4 0x5b6 6 533000000 6 13 0>; +}; + +&emmc { + /delete-property/mmc-hs200-1_8v; +}; + +&gpio_keys { + pinctrl-0 = <&pwr_key_h &ap_lid_int_l &volum_down_l &volum_up_l>; + + volum_down { + label = "Volum_down"; + gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <100>; + }; + + volum_up { + label = "Volum_up"; + gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <100>; + }; +}; + +&i2c_tunnel { + battery: bq27500@55 { + compatible = "ti,bq27500"; + reg = <0x55>; + }; +}; + +&i2c3 { + status = "okay"; + + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + interrupt-parent = <&gpio2>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_int &touch_rst>; + reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; + vcc33-supply = <&vcc33_touch>; + vccio-supply = <&vcc33_touch>; + }; +}; + +&panel { + compatible = "auo,b101ean01", "simple-panel"; + power-supply= <&panel_regulator>; +}; + +&rk808 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; + + regulators { + vcc33_touch: LDO_REG2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc33_touch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v_touch: SWITCH_REG2 { + regulator-name = "vcc5v_touch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; +}; + +&sdmmc { + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + &sdmmc_bus4>; +}; + +&vcc_5v { + enable-active-high; + gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&drv_5v>; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc50_hdmi_en>; +}; + +&pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { + rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buck-5v { + drv_5v: drv-5v { + rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + volum_down_l: volum-down-l { + rockchip,pins = <5 11 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + volum_up_l: volum-up-l { + rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { + rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_enable_h: lcd-en { + rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + avdd_1v8_disp_en: avdd-1v8-disp-en { + rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + prochot { + gpio_prochot: gpio-prochot { + rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touchscreen { + touch_int: touch-int { + rockchip,pins = <2 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + touch_rst: touch-rst { + rockchip,pins = <2 15 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi index 2ffe39cbf7..a314058750 100644 --- a/arch/arm/dts/rk3288-veyron.dtsi +++ b/arch/arm/dts/rk3288-veyron.dtsi @@ -245,14 +245,6 @@ 533000 1150000 666000 1200000 >; - rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 - 0x5 0x0>; - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 - 0xa60 0x40 0x10 0x0>; - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; }; &efuse { diff --git a/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts b/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts new file mode 100644 index 0000000000..dce688ec8e --- /dev/null +++ b/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2016 FUKAUMI Naoki <naobsd@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" + +/ { + model = "Nintendo NES Classic Edition"; + compatible = "nintendo,nes-classic-edition", "allwinner,sun8i-a33"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index b618a3f484..6df0329cfc 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -6,9 +6,10 @@ * * SPDX-License-Identifier: GPL-2.0+ */ -/include/ "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; compatible = "xlnx,zynq-7000"; cpus { @@ -37,14 +38,14 @@ }; }; - pmu { + pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; - regulator_vccpint: fixedregulator@0 { + regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts index cb238cd5e7..2d07b92e9c 100644 --- a/arch/arm/dts/zynq-microzed.dts +++ b/arch/arm/dts/zynq-microzed.dts @@ -18,7 +18,7 @@ mmc0 = &sdhci0; }; - memory { + memory@0 { device_type = "memory"; reg = <0 0x40000000>; }; diff --git a/arch/arm/dts/zynq-picozed.dts b/arch/arm/dts/zynq-picozed.dts index 3408df8b8b..fea04ab45a 100644 --- a/arch/arm/dts/zynq-picozed.dts +++ b/arch/arm/dts/zynq-picozed.dts @@ -16,7 +16,7 @@ serial0 = &uart1; }; - memory { + memory@0 { device_type = "memory"; reg = <0 0x40000000>; }; diff --git a/arch/arm/dts/zynq-topic-miami.dts b/arch/arm/dts/zynq-topic-miami.dts new file mode 100644 index 0000000000..aa05c4d368 --- /dev/null +++ b/arch/arm/dts/zynq-topic-miami.dts @@ -0,0 +1,97 @@ +/* + * Topic Miami board DTS + * + * Copyright (C) 2014-2016 Topic Embedded Products + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Topic Miami Zynq Board"; + compatible = "topic,miami", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart0; + spi0 = &qspi; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&qspi { + u-boot,dm-pre-reloc; + status = "okay"; + is-dual = <0>; + num-cs = <1>; + flash@0 { + compatible = "st,m25p80", "n25q256a"; + m25p,fast-read; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <100000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@qspi-u-boot-spl { + label = "qspi-u-boot-spl"; + reg = <0x00000 0x10000>; + }; + partition@qspi-u-boot-img { + label = "qspi-u-boot-img"; + reg = <0x10000 0x60000>; + }; + partition@qspi-device-tree { + label = "qspi-device-tree"; + reg = <0x70000 0x10000>; + }; + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x80000 0x400000>; + }; + partition@qspi-rootfs { + label = "qspi-rootfs"; + reg = <0x480000 0x1b80000>; + }; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&sdhci0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynq-topic-miamiplus.dts b/arch/arm/dts/zynq-topic-miamiplus.dts new file mode 100644 index 0000000000..3036f6ea9c --- /dev/null +++ b/arch/arm/dts/zynq-topic-miamiplus.dts @@ -0,0 +1,17 @@ +/* + * Topic Miami Plus board DTS + * + * Copyright (C) 2016 Topic Embedded Products + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include "zynq-topic-miami.dts" + +/ { + model = "Topic Miami+ Zynq Board"; + compatible = "topic,miamiplus", "xlnx,zynq-7000"; +}; + +&qspi { + is-dual = <1>; +}; diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 6585010f4b..478e9fd4ef 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -21,7 +21,7 @@ mmc0 = &sdhci0; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x40000000>; }; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index d04880a2cd..8b0177bc51 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -21,7 +21,7 @@ mmc0 = &sdhci0; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x40000000>; }; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index 33524cb6de..42af313c13 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -25,7 +25,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x40000000>; }; diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index 463b14b5ea..7f08961491 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -23,7 +23,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x40000000>; }; diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index 6cab832667..699cd2c0fb 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -24,7 +24,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x40000000>; }; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index d5bb4efcc5..07e92b88fb 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -25,7 +25,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x40000000>; }; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 4363a4fcac..0ac7532300 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -20,7 +20,7 @@ mmc0 = &sdhci0; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x20000000>; }; diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts index f8dcf1d699..d59a383135 100644 --- a/arch/arm/dts/zynq-zybo.dts +++ b/arch/arm/dts/zynq-zybo.dts @@ -20,7 +20,7 @@ mmc0 = &sdhci0; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x20000000>; }; diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi index 0918c686d7..aa848c8646 100644 --- a/arch/arm/dts/zynqmp-clk.dtsi +++ b/arch/arm/dts/zynqmp-clk.dtsi @@ -114,6 +114,38 @@ clocks = <&clk600>, <&clk100>; }; +&lpd_dma_chan1 { + clocks = <&clk600>, <&clk100>; +}; + +&lpd_dma_chan2 { + clocks = <&clk600>, <&clk100>; +}; + +&lpd_dma_chan3 { + clocks = <&clk600>, <&clk100>; +}; + +&lpd_dma_chan4 { + clocks = <&clk600>, <&clk100>; +}; + +&lpd_dma_chan5 { + clocks = <&clk600>, <&clk100>; +}; + +&lpd_dma_chan6 { + clocks = <&clk600>, <&clk100>; +}; + +&lpd_dma_chan7 { + clocks = <&clk600>, <&clk100>; +}; + +&lpd_dma_chan8 { + clocks = <&clk600>, <&clk100>; +}; + &nand0 { clocks = <&clk100 &clk100>; }; diff --git a/arch/arm/dts/zynqmp-ep108-clk.dtsi b/arch/arm/dts/zynqmp-ep108-clk.dtsi index b3ce0de549..1c2efe459d 100644 --- a/arch/arm/dts/zynqmp-ep108-clk.dtsi +++ b/arch/arm/dts/zynqmp-ep108-clk.dtsi @@ -35,6 +35,18 @@ clock-accuracy = <100>; }; + clk100: clk100 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + clk600: clk600 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + }; + dp_aud_clk: clock1 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -47,6 +59,42 @@ clocks = <&misc_clk &misc_clk>; }; +&can1 { + clocks = <&misc_clk &misc_clk>; +}; + +&fpd_dma_chan1 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan2 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan3 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan4 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan5 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan6 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan7 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan8 { + clocks = <&clk600>, <&clk100>; +}; + &gem0 { clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>; }; diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index 0bbf9a7597..2483180d38 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -31,7 +31,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x40000000>; }; @@ -41,6 +41,10 @@ status = "okay"; }; +&can1 { + status = "okay"; +}; + &gem0 { status = "okay"; phy-handle = <&phy0>; @@ -150,10 +154,12 @@ &sdhci0 { status = "okay"; bus-width = <8>; + xlnx,mio_bank = <2>; }; &sdhci1 { status = "okay"; + xlnx,mio_bank = <1>; }; &spi0 { diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index c68a41bea7..b3f42977ab 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -34,7 +34,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; @@ -159,12 +159,14 @@ &sdhci0 { status = "okay"; bus-width = <8>; + xlnx,mio_bank = <0>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; /* for 1.0 silicon */ + xlnx,mio_bank = <1>; }; &uart0 { diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 3fdfcc8a11..09a114be16 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -36,7 +36,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 03f1ad7934..1f03a94820 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -41,7 +41,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index d754f9f904..698e72e0c5 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -32,7 +32,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; diff --git a/arch/arm/dts/zynqmp-zcu102.dts b/arch/arm/dts/zynqmp-zcu102.dts index de99602456..0e9150e6b1 100644 --- a/arch/arm/dts/zynqmp-zcu102.dts +++ b/arch/arm/dts/zynqmp-zcu102.dts @@ -12,6 +12,7 @@ #include "zynqmp.dtsi" #include "zynqmp-clk.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "ZynqMP ZCU102 RevA"; @@ -26,6 +27,7 @@ rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; + serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; @@ -35,16 +37,43 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + sw19 { + label = "sw19"; + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + linux,code = <108>; /* down */ + gpio-key,wakeup; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + heartbeat_led { + label = "heartbeat"; + gpios = <&gpio 23 0>; + linux,default-trigger = "heartbeat"; + }; + }; }; &can1 { status = "okay"; }; +&dcc { + status = "okay"; +}; + /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; @@ -365,7 +394,7 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o /* Bus 3 is not connected */ }; - /* FIXME PL connection - u55 , PMOD - j160 */ + /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; @@ -576,6 +605,7 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o &sdhci1 { status = "okay"; no-1-8-v; /* for 1.0 silicon */ + xlnx,mio_bank = <1>; }; &uart0 { diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 619450e1ba..ab5c243c61 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -45,6 +45,12 @@ }; }; + dcc: dcc { + compatible = "arm,dcc"; + status = "disabled"; + u-boot,dm-pre-reloc; + }; + power-domains { compatible = "xlnx,zynqmp-genpd"; @@ -184,34 +190,14 @@ pd-id = <0x30>; }; - pd_ddr: pd-ddr { - #power-domain-cells = <0x0>; - pd-id = <0x37>; - }; - - pd_apll: pd-apll { - #power-domain-cells = <0x0>; - pd-id = <0x32>; - }; - - pd_vpll: pd-vpll { + pd_pcie: pd-pcie { #power-domain-cells = <0x0>; - pd-id = <0x33>; + pd-id = <0x3b>; }; - pd_dpll: pd-dpll { + pd_gpu: pd-gpu { #power-domain-cells = <0x0>; - pd-id = <0x34>; - }; - - pd_rpll: pd-rpll { - #power-domain-cells = <0x0>; - pd-id = <0x35>; - }; - - pd_iopll: pd-iopll { - #power-domain-cells = <0x0>; - pd-id = <0x36>; + pd-id = <0x3a 0x14 0x15>; }; }; @@ -243,7 +229,15 @@ <1 10 0xf01>; }; - amba_apu: amba_apu { + edac { + compatible = "arm,cortex-a53-edac"; + }; + + pcap { + compatible = "xlnx,zynqmp-pcap-fpga"; + }; + + amba_apu: amba_apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; @@ -266,14 +260,14 @@ compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0 0xffffffff>; + #size-cells = <2>; + ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; - reg = <0x0 0xff060000 0x1000>; + reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; @@ -285,7 +279,7 @@ compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; - reg = <0x0 0xff070000 0x1000>; + reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; @@ -295,7 +289,7 @@ cci: cci@fd6e0000 { compatible = "arm,cci-400"; - reg = <0x0 0xfd6e0000 0x9000>; + reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; @@ -316,200 +310,228 @@ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd500000 0x1000>; + reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; - xlnx,id = <0>; xlnx,bus-width = <128>; + #stream-id-cells = <1>; + iommus = <&smmu 0x14e8>; power-domains = <&pd_gdma>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd510000 0x1000>; + reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; - xlnx,id = <1>; xlnx,bus-width = <128>; + #stream-id-cells = <1>; + iommus = <&smmu 0x14e9>; power-domains = <&pd_gdma>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd520000 0x1000>; + reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; - xlnx,id = <2>; xlnx,bus-width = <128>; + #stream-id-cells = <1>; + iommus = <&smmu 0x14ea>; power-domains = <&pd_gdma>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd530000 0x1000>; + reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; - xlnx,id = <3>; xlnx,bus-width = <128>; + #stream-id-cells = <1>; + iommus = <&smmu 0x14eb>; power-domains = <&pd_gdma>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd540000 0x1000>; + reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; - xlnx,id = <4>; xlnx,bus-width = <128>; + #stream-id-cells = <1>; + iommus = <&smmu 0x14ec>; power-domains = <&pd_gdma>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd550000 0x1000>; + reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; - xlnx,id = <5>; xlnx,bus-width = <128>; + #stream-id-cells = <1>; + iommus = <&smmu 0x14ed>; power-domains = <&pd_gdma>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd560000 0x1000>; + reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; - xlnx,id = <6>; xlnx,bus-width = <128>; + #stream-id-cells = <1>; + iommus = <&smmu 0x14ee>; power-domains = <&pd_gdma>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd570000 0x1000>; + reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; - xlnx,id = <7>; xlnx,bus-width = <128>; + #stream-id-cells = <1>; + iommus = <&smmu 0x14ef>; power-domains = <&pd_gdma>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; - reg = <0x0 0xfd4b0000 0x30000>; + reg = <0x0 0xfd4b0000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; + power-domains = <&pd_gpu>; }; - /* ADMA */ + /* LPDDMA default allows only secured access. inorder to enable + * These dma channels, Users should ensure that these dma + * Channels are allowed for non secure access. + */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffa80000 0x1000>; + clock-names = "clk_main", "clk_apb"; + reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; - xlnx,id = <0>; xlnx,bus-width = <64>; + #stream-id-cells = <1>; + iommus = <&smmu 0x868>; power-domains = <&pd_adma>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffa90000 0x1000>; + clock-names = "clk_main", "clk_apb"; + reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; - xlnx,id = <1>; xlnx,bus-width = <64>; + #stream-id-cells = <1>; + iommus = <&smmu 0x869>; power-domains = <&pd_adma>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffaa0000 0x1000>; + clock-names = "clk_main", "clk_apb"; + reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; - xlnx,id = <2>; xlnx,bus-width = <64>; + #stream-id-cells = <1>; + iommus = <&smmu 0x86a>; power-domains = <&pd_adma>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffab0000 0x1000>; + clock-names = "clk_main", "clk_apb"; + reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; - xlnx,id = <3>; xlnx,bus-width = <64>; + #stream-id-cells = <1>; + iommus = <&smmu 0x86b>; power-domains = <&pd_adma>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffac0000 0x1000>; + clock-names = "clk_main", "clk_apb"; + reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; - xlnx,id = <4>; xlnx,bus-width = <64>; + #stream-id-cells = <1>; + iommus = <&smmu 0x86c>; power-domains = <&pd_adma>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffad0000 0x1000>; + clock-names = "clk_main", "clk_apb"; + reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; - xlnx,id = <5>; xlnx,bus-width = <64>; + #stream-id-cells = <1>; + iommus = <&smmu 0x86d>; power-domains = <&pd_adma>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffae0000 0x1000>; + clock-names = "clk_main", "clk_apb"; + reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; - xlnx,id = <6>; xlnx,bus-width = <64>; + #stream-id-cells = <1>; + iommus = <&smmu 0x86e>; power-domains = <&pd_adma>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffaf0000 0x1000>; + clock-names = "clk_main", "clk_apb"; + reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; - xlnx,id = <7>; xlnx,bus-width = <64>; + #stream-id-cells = <1>; + iommus = <&smmu 0x86f>; power-domains = <&pd_adma>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; - reg = <0x0 0xfd070000 0x30000>; + reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; @@ -517,12 +539,14 @@ nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "disabled"; - reg = <0x0 0xff100000 0x1000>; + reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "clk_sys", "clk_flash"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <2>; #size-cells = <1>; + #stream-id-cells = <1>; + iommus = <&smmu 0x872>; power-domains = <&pd_nand>; }; @@ -531,11 +555,12 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; - reg = <0x0 0xff0b0000 0x1000>; + reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; + iommus = <&smmu 0x874>; power-domains = <&pd_eth0>; }; @@ -544,11 +569,12 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; - reg = <0x0 0xff0c0000 0x1000>; + reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; + iommus = <&smmu 0x875>; power-domains = <&pd_eth1>; }; @@ -557,11 +583,12 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; - reg = <0x0 0xff0d0000 0x1000>; + reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; + iommus = <&smmu 0x876>; power-domains = <&pd_eth2>; }; @@ -570,11 +597,12 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; - reg = <0x0 0xff0e0000 0x1000>; + reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; + iommus = <&smmu 0x877>; power-domains = <&pd_eth3>; }; @@ -582,11 +610,11 @@ compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; - #interrupt-cells = <2>; - interrupt-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; - reg = <0x0 0xff0a0000 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0xff0a0000 0x0 0x1000>; power-domains = <&pd_gpio>; }; @@ -595,7 +623,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; - reg = <0x0 0xff020000 0x1000>; + reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c0>; @@ -606,35 +634,47 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; - reg = <0x0 0xff030000 0x1000>; + reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c1>; }; + ocm: memory-controller@ff960000 { + compatible = "xlnx,zynqmp-ocmc-1.0"; + reg = <0x0 0xff960000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 10 4>; + }; + pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; + msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, + <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ - interrupt-names = "misc", "intx", "msi_1", "msi_0"; - reg = <0x0 0xfd0e0000 0x1000>, - <0x0 0xfd480000 0x1000>, - <0x0 0xe0000000 0x1000000>; + interrupt-names = "misc","dummy","intx", "msi1", "msi0"; + msi-parent = <&pcie>; + reg = <0x0 0xfd0e0000 0x0 0x1000>, + <0x0 0xfd480000 0x0 0x1000>, + <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; - ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>; + ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ + 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; + power-domains = <&pd_pcie>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; @@ -649,26 +689,51 @@ interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; - reg = <0x0 0xff0f0000 0x1000>, - <0x0 0xc0000000 0x8000000>; + reg = <0x0 0xff0f0000 0x0 0x1000>, + <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; + #stream-id-cells = <1>; + iommus = <&smmu 0x873>; power-domains = <&pd_qspi>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; - reg = <0x0 0xffa60000 0x100>; + reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; }; + serdes: zynqmp_phy@fd400000 { + compatible = "xlnx,zynqmp-psgtr"; + status = "disabled"; + reg = <0x0 0xfd400000 0x0 0x40000>, + <0x0 0xfd3d0000 0x0 0x1000>, + <0x0 0xfd1a0000 0x0 0x1000>, + <0x0 0xff5e0000 0x0 0x1000>; + reg-names = "serdes", "siou", "fpd", "lpd"; + xlnx,tx_termination_fix; + lane0: lane0 { + #phy-cells = <4>; + }; + lane1: lane1 { + #phy-cells = <4>; + }; + lane2: lane2 { + #phy-cells = <4>; + }; + lane3: lane3 { + #phy-cells = <4>; + }; + }; + sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; - reg = <0x0 0xfd0c0000 0x2000>; + reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&pd_sata>; @@ -676,31 +741,36 @@ sdhci0: sdhci@ff160000 { u-boot,dm-pre-reloc; - compatible = "arasan,sdhci-8.9a"; + compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; - reg = <0x0 0xff160000 0x1000>; + reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; - broken-tuning; + xlnx,device_id = <0>; + #stream-id-cells = <1>; + iommus = <&smmu 0x870>; power-domains = <&pd_sd0>; }; sdhci1: sdhci@ff170000 { u-boot,dm-pre-reloc; - compatible = "arasan,sdhci-8.9a"; + compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; - reg = <0x0 0xff170000 0x1000>; + reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; - broken-tuning; + xlnx,device_id = <1>; + #stream-id-cells = <1>; + iommus = <&smmu 0x871>; power-domains = <&pd_sd1>; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; - reg = <0x0 0xfd800000 0x20000>; + reg = <0x0 0xfd800000 0x0 0x20000>; + #iommu-cells = <1>; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, @@ -711,7 +781,29 @@ mmu-masters = < &gem0 0x874 &gem1 0x875 &gem2 0x876 - &gem3 0x877 >; + &gem3 0x877 + &usb0 0x860 + &usb1 0x861 + &qspi 0x873 + &lpd_dma_chan1 0x868 + &lpd_dma_chan2 0x869 + &lpd_dma_chan3 0x86a + &lpd_dma_chan4 0x86b + &lpd_dma_chan5 0x86c + &lpd_dma_chan6 0x86d + &lpd_dma_chan7 0x86e + &lpd_dma_chan8 0x86f + &fpd_dma_chan1 0x14e8 + &fpd_dma_chan2 0x14e9 + &fpd_dma_chan3 0x14ea + &fpd_dma_chan4 0x14eb + &fpd_dma_chan5 0x14ec + &fpd_dma_chan6 0x14ed + &fpd_dma_chan7 0x14ee + &fpd_dma_chan8 0x14ef + &sdhci0 0x870 + &sdhci1 0x871 + &nand0 0x872>; }; spi0: spi@ff040000 { @@ -719,7 +811,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; - reg = <0x0 0xff040000 0x1000>; + reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; @@ -731,7 +823,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; - reg = <0x0 0xff050000 0x1000>; + reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; @@ -743,7 +835,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; - reg = <0x0 0xff110000 0x1000>; + reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc0>; }; @@ -753,7 +845,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; - reg = <0x0 0xff120000 0x1000>; + reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc1>; }; @@ -763,7 +855,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; - reg = <0x0 0xff130000 0x1000>; + reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc2>; }; @@ -773,7 +865,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; - reg = <0x0 0xff140000 0x1000>; + reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc3>; }; @@ -784,7 +876,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; - reg = <0x0 0xff000000 0x1000>; + reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart0>; }; @@ -795,25 +887,27 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; - reg = <0x0 0xff010000 0x1000>; + reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart1>; }; - usb0: usb@fe200000 { + usb0: usb0 { #address-cells = <2>; - #size-cells = <1>; + #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125>, <&clk125>; + #stream-id-cells = <1>; + iommus = <&smmu 0x860>; power-domains = <&pd_usb0>; ranges; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; - reg = <0x0 0xfe200000 0x40000>; + reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 65 4>; /* snps,quirk-frame-length-adjustment = <0x20>; */ @@ -821,20 +915,22 @@ }; }; - usb1: usb@fe300000 { + usb1: usb1 { #address-cells = <2>; - #size-cells = <1>; + #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125>, <&clk125>; + #stream-id-cells = <1>; + iommus = <&smmu 0x861>; power-domains = <&pd_usb1>; ranges; dwc3_1: dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; - reg = <0x0 0xfe300000 0x40000>; + reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 70 4>; /* snps,quirk-frame-length-adjustment = <0x20>; */ @@ -847,7 +943,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; - reg = <0x0 0xfd4d0000 0x1000>; + reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; @@ -861,11 +957,13 @@ xlnx,pixel-format = "rgb565"; plane0 { dmas = <&xlnx_dpdma 3>; - dma-names = "dma"; + dma-names = "dma0"; }; plane1 { - dmas = <&xlnx_dpdma 0>; - dma-names = "dma"; + dmas = <&xlnx_dpdma 0>, + <&xlnx_dpdma 1>, + <&xlnx_dpdma 2>; + dma-names = "dma0", "dma1", "dma2"; }; }; }; @@ -873,8 +971,7 @@ xlnx_dp: dp@fd4a0000 { compatible = "xlnx,v-dp"; status = "disabled"; - reg = <0x0 0xfd4a0000 0x1000>, - <0x0 0xfd400000 0x20000>; + reg = <0x0 0xfd4a0000 0x0 0x1000>; interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "aclk", "aud_clk"; @@ -920,9 +1017,9 @@ xlnx_dp_sub: dp_sub@fd4aa000 { compatible = "xlnx,dp-sub"; status = "disabled"; - reg = <0x0 0xfd4aa000 0x1000>, - <0x0 0xfd4ab000 0x1000>, - <0x0 0xfd4ac000 0x1000>; + reg = <0x0 0xfd4aa000 0x0 0x1000>, + <0x0 0xfd4ab000 0x0 0x1000>, + <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "blend", "av_buf", "aud"; xlnx,output-fmt = "rgb"; xlnx,vid-fmt = "yuyv"; @@ -932,28 +1029,28 @@ xlnx_dpdma: dma@fd4c0000 { compatible = "xlnx,dpdma"; status = "disabled"; - reg = <0x0 0xfd4c0000 0x1000>; + reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; dma-channels = <6>; #dma-cells = <1>; - dma-video0channel@fd4c0000 { + dma-video0channel { compatible = "xlnx,video0"; }; - dma-video1channel@fd4c0000 { + dma-video1channel { compatible = "xlnx,video1"; }; - dma-video2channel@fd4c0000 { + dma-video2channel { compatible = "xlnx,video2"; }; - dma-graphicschannel@fd4c0000 { + dma-graphicschannel { compatible = "xlnx,graphics"; }; - dma-audio0channel@fd4c0000 { + dma-audio0channel { compatible = "xlnx,audio0"; }; - dma-audio1channel@fd4c0000 { + dma-audio1channel { compatible = "xlnx,audio1"; }; }; |