imx: reorganize IMX code as other SOCs

Change is consistent with other SOCs and it is in preparation
for adding SOMs. SOC's related files are moved from cpu/ to
mach-imx/<SOC>.

This change is also coherent with the structure in kernel.

Signed-off-by: Stefano Babic <sbabic@denx.de>

CC: Fabio Estevam <fabio.estevam@nxp.com>
CC: Akshay Bhat <akshaybhat@timesys.com>
CC: Ken Lin <Ken.Lin@advantech.com.tw>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Heiko Schocher <hs@denx.de>
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CC: Christian Gmeiner <christian.gmeiner@gmail.com>
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CC: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Nikita Kiryanov <nikita@compulab.co.il>
CC: Otavio Salvador <otavio@ossystems.com.br>
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CC: Jagan Teki <jagan@amarulasolutions.com>
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CC: Alison Wang <b18965@freescale.com>
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CC: "Łukasz Majewski" <l.majewski@samsung.com>
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CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Hans de Goede <hdegoede@redhat.com>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
CC: Stephen Warren <swarren@nvidia.com>
CC: Andre Przywara <andre.przywara@arm.com>
CC: "Álvaro Fernández Rojas" <noltari@gmail.com>
CC: York Sun <york.sun@nxp.com>
CC: Xiaoliang Yang <xiaoliang.yang@nxp.com>
CC: Chen-Yu Tsai <wens@csie.org>
CC: George McCollister <george.mccollister@gmail.com>
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CC: Petr Kulhavy <brain@jikos.cz>
CC: Eric Nelson <eric@nelint.com>
CC: Bai Ping <ping.bai@nxp.com>
CC: Anson Huang <Anson.Huang@nxp.com>
CC: Sanchayan Maity <maitysanchayan@gmail.com>
CC: Lokesh Vutla <lokeshvutla@ti.com>
CC: Patrick Delaunay <patrick.delaunay@st.com>
CC: Gary Bisson <gary.bisson@boundarydevices.com>
CC: Alexander Graf <agraf@suse.de>
CC: u-boot@lists.denx.de
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

1 files changed, 0 insertions, 139 deletions

diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
deleted file mode 100644
index 9b011147d6..0000000000
--- a/arch/arm/imx-common/timer.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <div64.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-
-/* General purpose timers registers */
-struct mxc_gpt {
-	unsigned int control;
-	unsigned int prescaler;
-	unsigned int status;
-	unsigned int nouse[6];
-	unsigned int counter;
-};
-
-static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR		(1 << 15)	/* Software reset */
-#define GPTCR_24MEN	    (1 << 10)	/* Enable 24MHz clock input */
-#define GPTCR_FRR		(1 << 9)	/* Freerun / restart */
-#define GPTCR_CLKSOURCE_32	(4 << 6)	/* Clock source 32khz */
-#define GPTCR_CLKSOURCE_OSC	(5 << 6)	/* Clock source OSC */
-#define GPTCR_CLKSOURCE_PRE	(1 << 6)	/* Clock source PRECLK */
-#define GPTCR_CLKSOURCE_MASK (0x7 << 6)
-#define GPTCR_TEN		1		/* Timer enable */
-
-#define GPTPR_PRESCALER24M_SHIFT 12
-#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static inline int gpt_has_clk_source_osc(void)
-{
-#if defined(CONFIG_MX6)
-	if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
-	    is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
-	    is_mx6ull() || is_mx6sll())
-		return 1;
-
-	return 0;
-#else
-	return 0;
-#endif
-}
-
-static inline ulong gpt_get_clk(void)
-{
-#ifdef CONFIG_MXC_GPT_HCLK
-	if (gpt_has_clk_source_osc())
-		return MXC_HCLK >> 3;
-	else
-		return mxc_get_clock(MXC_IPG_PERCLK);
-#else
-	return MXC_CLK32;
-#endif
-}
-
-int timer_init(void)
-{
-	int i;
-
-	/* setup GP Timer 1 */
-	__raw_writel(GPTCR_SWR, &cur_gpt->control);
-
-	/* We have no udelay by now */
-	for (i = 0; i < 100; i++)
-		__raw_writel(0, &cur_gpt->control);
-
-	i = __raw_readl(&cur_gpt->control);
-	i &= ~GPTCR_CLKSOURCE_MASK;
-
-#ifdef CONFIG_MXC_GPT_HCLK
-	if (gpt_has_clk_source_osc()) {
-		i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
-
-		/*
-		 * For DL/S, SX, UL, ULL, SLL set 24Mhz OSC
-		 * Enable bit and prescaler
-		 */
-		if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
-		    is_mx6sll()) {
-			i |= GPTCR_24MEN;
-
-			/* Produce 3Mhz clock */
-			__raw_writel((7 << GPTPR_PRESCALER24M_SHIFT),
-				     &cur_gpt->prescaler);
-		}
-	} else {
-		i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN;
-	}
-#else
-	__raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
-	i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
-#endif
-	__raw_writel(i, &cur_gpt->control);
-
-	return 0;
-}
-
-unsigned long timer_read_counter(void)
-{
-	return __raw_readl(&cur_gpt->counter); /* current tick value */
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return gpt_get_clk();
-}
-
-/*
- * This function is intended for SHORT delays only.
- * It will overflow at around 10 seconds @ 400MHz,
- * or 20 seconds @ 200MHz.
- */
-unsigned long usec2ticks(unsigned long _usec)
-{
-	unsigned long long usec = _usec;
-
-	usec *= get_tbclk();
-	usec += 999999;
-	do_div(usec, 1000000);
-
-	return usec;
-}