diff options
| author | Hao Zhang <hzhang@ti.com> | 2014-10-22 16:32:32 +0300 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-10-23 11:27:05 -0400 |
| commit | b66604fb66c3e8fee5d294ac548d6da52fd1fae1 (patch) | |
| tree | 5f46eae2a3a3051134a8932dbe7dc7a2757940b8 /arch/arm/include/asm/arch-keystone/hardware.h | |
| parent | 5ec66b140afff89c3ee5abde4a9eb4c0963c918c (diff) | |
keystone2: enable OSR clock domain for K2L SoC
This patches enables the On-chip Shared Ram clock domain for K2L SoC.
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-keystone/hardware.h')
| -rw-r--r-- | arch/arm/include/asm/arch-keystone/hardware.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index 295c6b0ea9..08a7c70038 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -142,6 +142,7 @@ typedef volatile unsigned int *dv_reg_p; /* MSMC control */ #define KS2_MSMC_CTRL_BASE 0x0bc00000 +#define KS2_MSMC_DATA_BASE 0x0c000000 #define KS2_MSMC_SEGMENT_TETRIS 8 #define KS2_MSMC_SEGMENT_NETCP 9 #define KS2_MSMC_SEGMENT_QM_PDSP 10 |