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authorTom Rini <trini@ti.com>2014-11-13 10:35:13 -0500
committerTom Rini <trini@ti.com>2014-11-13 10:35:13 -0500
commit0d485b9095328cdc81b2ee94ff59b988c69b9127 (patch)
tree93406f5dfe78b0b5670272a9de3f3eb3ee419785 /arch/arm/include/asm/arch-sunxi/clock_sun6i.h
parent3ad207a2bf1399a689233a97978e306f71729f77 (diff)
parent64a97599b79e277600bc6f1b22cf48aa04ee9bd0 (diff)
Merge branch 'master' of git://git.denx.de/u-boot-sunxi
Diffstat (limited to 'arch/arm/include/asm/arch-sunxi/clock_sun6i.h')
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun6i.h38
1 files changed, 37 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 1397b35889..e16a7647ed 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -170,7 +170,17 @@ struct sunxi_ccm_reg {
#define CPU_CLK_SRC_OSC24M 1
#define CPU_CLK_SRC_PLL1 2
-#define PLL1_CFG_DEFAULT 0x90011b21
+#define CCM_PLL1_CTRL_M(n) ((((n) - 1) & 0x3) << 0)
+#define CCM_PLL1_CTRL_K(n) ((((n) - 1) & 0x3) << 4)
+#define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8)
+#define CCM_PLL1_CTRL_MAGIC (0x1 << 16)
+#define CCM_PLL1_CTRL_EN (0x1 << 31)
+
+#define CCM_PLL5_CTRL_M(n) ((((n) - 1) & 0x3) << 0)
+#define CCM_PLL5_CTRL_K(n) ((((n) - 1) & 0x3) << 4)
+#define CCM_PLL5_CTRL_N(n) ((((n) - 1) & 0x1f) << 8)
+#define CCM_PLL5_CTRL_UPD (0x1 << 20)
+#define CCM_PLL5_CTRL_EN (0x1 << 31)
#define PLL6_CFG_DEFAULT 0x90041811
@@ -179,6 +189,15 @@ struct sunxi_ccm_reg {
#define CCM_PLL6_CTRL_K_SHIFT 4
#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
+#define AHB1_ABP1_DIV_DEFAULT 0x00002020
+
+#define AXI_GATE_OFFSET_DRAM 0
+
+#define AHB_GATE_OFFSET_USB_OHCI1 30
+#define AHB_GATE_OFFSET_USB_OHCI0 29
+#define AHB_GATE_OFFSET_USB_EHCI1 27
+#define AHB_GATE_OFFSET_USB_EHCI0 26
+#define AHB_GATE_OFFSET_MCTL 14
#define AHB_GATE_OFFSET_MMC3 11
#define AHB_GATE_OFFSET_MMC2 10
#define AHB_GATE_OFFSET_MMC1 9
@@ -190,6 +209,23 @@ struct sunxi_ccm_reg {
#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
+#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
+#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
+/* There is no global phy clk gate on sun6i, define as 0 */
+#define CCM_USB_CTRL_PHYGATE 0
+#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
+#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
+
+#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */
+
+#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8)
+#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8)
+#define CCM_DRAMCLK_CFG_UPD (0x1 << 16)
+#define CCM_DRAMCLK_CFG_RST (0x1 << 31)
+
+#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */
+
+#define AHB_RESET_OFFSET_MCTL 14
#define AHB_RESET_OFFSET_MMC3 11
#define AHB_RESET_OFFSET_MMC2 10
#define AHB_RESET_OFFSET_MMC1 9