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authorMarcel Ziswiler <marcel@ziswiler.com>2014-03-11 18:43:59 +0100
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-04-07 20:15:44 +0200
commit6c81a93db700021614c6ae150f8c1c995173201f (patch)
tree98c5a2fce5e994e33822e365caa284b4e1d12444 /arch/arm/include/asm/arch-vf610/imx-regs.h
parentc7098965e31b6faf1a861fcca77ef7112b9bf6e4 (diff)
arm: vf610: add enet1 support
This patch contains several changes required for second Ethernet (enet1/RMII1) port on vf610 - ANADIG PLL5 control definitions required for Ethernet RMII1 clock - Secondary Ethernet (enet1) MAC RMII1 base address definition - RMII1 iomux definitions - VF610_PAD_PTA6__RMII0_CLKOUT iomux definition required for internal (e.g. crystal-less) Ethernet clocking. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> [stefan@agner.ch: regrouped patch] Signed-off-by: Stefan Agner <stefan@agner.ch>
Diffstat (limited to 'arch/arm/include/asm/arch-vf610/imx-regs.h')
-rw-r--r--arch/arm/include/asm/arch-vf610/imx-regs.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index b8c877f939..c2f9761846 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -85,6 +85,7 @@
#define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000)
#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000)
+#define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000)
/* MUX mode and PAD ctrl are in one register */
#define CONFIG_IOMUX_SHARE_CONF_REG