diff options
| author | Tom Rini <trini@konsulko.com> | 2016-01-27 15:05:12 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-01-27 15:05:12 -0500 |
| commit | 19bde0316f2c58b3ab6357832790aee6ed7a4ad5 (patch) | |
| tree | 8216f416e21cf71745abaec2c5a42ab9824b290e /arch/arm/include/asm/arch-zynqmp | |
| parent | b20c38a973a51bf3f663bd298c63ad1b8e0de445 (diff) | |
| parent | f36919a8138ed7ecd3dbce4630e02936b13907da (diff) | |
Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze
Diffstat (limited to 'arch/arm/include/asm/arch-zynqmp')
| -rw-r--r-- | arch/arm/include/asm/arch-zynqmp/clk.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-zynqmp/hardware.h | 30 |
2 files changed, 26 insertions, 5 deletions
diff --git a/arch/arm/include/asm/arch-zynqmp/clk.h b/arch/arm/include/asm/arch-zynqmp/clk.h index d55bc31c43..b18333d1ca 100644 --- a/arch/arm/include/asm/arch-zynqmp/clk.h +++ b/arch/arm/include/asm/arch-zynqmp/clk.h @@ -9,5 +9,6 @@ #define _ASM_ARCH_CLK_H_ unsigned long get_uart_clk(int dev_id); +unsigned long zynqmp_get_system_timer_freq(void); #endif /* _ASM_ARCH_CLK_H_ */ diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index bbf89d9dd7..587938249e 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -41,11 +41,8 @@ struct crlapb_regs { #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) -#if defined(CONFIG_SECURE_IOU) -#define ZYNQMP_IOU_SCNTR 0xFF260000 -#else +#define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 #define ZYNQMP_IOU_SCNTR 0xFF250000 -#endif #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 @@ -57,9 +54,21 @@ struct iou_scntr { #define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR) +struct iou_scntr_secure { + u32 counter_control_register; + u32 reserved0[7]; + u32 base_frequency_id_register; +}; + +#define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE) + /* Bootmode setting values */ #define BOOT_MODES_MASK 0x0000000F -#define SD_MODE 0x00000003 +#define QSPI_MODE_24BIT 0x00000001 +#define QSPI_MODE_32BIT 0x00000002 +#define SD_MODE 0x00000003 /* sd 0 */ +#define SD_MODE1 0x00000005 /* sd 1 */ +#define NAND_MODE 0x00000004 #define EMMC_MODE 0x00000006 #define JTAG_MODE 0x00000000 @@ -106,9 +115,20 @@ struct apu_regs { #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) /* Board version value */ +#define ZYNQMP_CSU_BASEADDR 0xFFCA0000 #define ZYNQMP_CSU_VERSION_SILICON 0x0 #define ZYNQMP_CSU_VERSION_EP108 0x1 #define ZYNQMP_CSU_VERSION_VELOCE 0x2 #define ZYNQMP_CSU_VERSION_QEMU 0x3 +#define ZYNQMP_SILICON_VER_MASK 0xF000 +#define ZYNQMP_SILICON_VER_SHIFT 12 + +struct csu_regs { + u32 reserved0[17]; + u32 version; +}; + +#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR) + #endif /* _ASM_ARCH_HARDWARE_H */ |