diff options
| author | York Sun <york.sun@nxp.com> | 2017-09-08 09:33:49 -0700 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-09-11 08:02:13 -0700 |
| commit | 42f43aa25876d1c77002ee5f333ab36dcb01d719 (patch) | |
| tree | 5841dcef0e5745e02dd16b8f9c9fe89c541e2d92 /arch/arm/include/asm | |
| parent | 4950eb4a48623d8ad013c1f37097906ec52040d1 (diff) | |
armv8: fsl-layerscape: Add back L3 flushing for all exception levels
CCN-504 HPF registers were believed to be accessible only from EL3.
However, recent tests proved otherwise. Remove checking for exception
level to re-enable L3 cache flushing for all levels.
Signed-off-by: York Sun <york.sun@nxp.com>
Tested-by: Zhao Qiang <qiang.zhao@nxp.com>
Diffstat (limited to 'arch/arm/include/asm')
0 files changed, 0 insertions, 0 deletions