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authorTom Rini <trini@konsulko.com>2017-01-11 08:04:26 -0500
committerTom Rini <trini@konsulko.com>2017-01-11 08:04:26 -0500
commit5b30997fd26f0e13837e9ba3cd289a037b8353bd (patch)
treedf8233b2d73eff88fcdf5d0d5f62da02cf498fa1 /arch/arm/include
parentf401e907fcbc94adff1a8e8097c8f0a5b0aee580 (diff)
parent7364dfe7bfca8632bfe02de5c333a64472812ebe (diff)
Merge tag 'xilinx-for-v2017.03' of git://www.denx.de/git/u-boot-microblaze
Xilinx changes for v2017.03 - ATF handoff - DT syncups - gem: Use wait_for_bit(), add simple clk support - Simple clk driver for ZynqMP - Other small changes
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-zynqmp/hardware.h9
-rw-r--r--arch/arm/include/asm/arch-zynqmp/sys_proto.h4
2 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index 041b43cfe0..cf187f3111 100644
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -144,4 +144,13 @@ struct csu_regs {
#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR)
+#define ZYNQMP_PMU_BASEADDR 0xFFD80000
+
+struct pmu_regs {
+ u32 reserved[18];
+ u32 gen_storage6; /* 0x48 */
+};
+
+#define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR)
+
#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
index 1db2bd6a4f..8c54fcedf4 100644
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
@@ -8,10 +8,12 @@
#ifndef _ASM_ARCH_SYS_PROTO_H
#define _ASM_ARCH_SYS_PROTO_H
+#ifndef CONFIG_CLK_ZYNQMP
/* Setup clk for network */
static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
{
}
+#endif
int zynq_slcr_get_mio_pin_status(const char *periph);
@@ -19,4 +21,6 @@ unsigned int zynqmp_get_silicon_version(void);
void psu_init(void);
+void handoff_setup(void);
+
#endif /* _ASM_ARCH_SYS_PROTO_H */