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authorTom Rini <trini@konsulko.com>2018-01-26 07:46:34 -0500
committerTom Rini <trini@konsulko.com>2018-01-26 07:46:34 -0500
commit1d12a7c8cd4e58d5c3989bc239d5fa9577079dfd (patch)
tree00550f8c91498b648d95c0c1c9f642deb324c4a5 /arch/arm/mach-socfpga/clock_manager_arria10.c
parenta3f77c810b1a57853e4d5fee3014ac8cbbd03a9a (diff)
parent58c125b9e2b232ce73ed7b24ba7b1ca5ff41c5bd (diff)
Merge git://git.denx.de/u-boot-spi
Diffstat (limited to 'arch/arm/mach-socfpga/clock_manager_arria10.c')
-rw-r--r--arch/arm/mach-socfpga/clock_manager_arria10.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c
index 482b8543f4..623a266f80 100644
--- a/arch/arm/mach-socfpga/clock_manager_arria10.c
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <fdtdec.h>
#include <asm/io.h>
+#include <dm.h>
#include <asm/arch/clock_manager.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -1076,6 +1077,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB);
}
+/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
+int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+ *rate = cm_get_spi_controller_clk_hz();
+
+ return 0;
+}
+
void cm_print_clock_quick_summary(void)
{
printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);