diff options
| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2019-11-27 15:55:16 +0800 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2020-01-07 14:38:33 +0100 |
| commit | fd5374aa29cc00d5694b47256c0a7c820e3d0892 (patch) | |
| tree | f7722a3fcd9e0a1bb90b630837f207c12f5d1eb7 /arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h | |
| parent | 8b7962a34923d8eaa2459376b12f8cead7f3894a (diff) | |
arm: socfpga: Move Stratix10 and Agilex reset manager common code
Move Stratix10 and Agilex reset manager common code to
reset_manager_soc64.h. Changed macros to RSTMGR_SOC64_*.
Remove unused RSTMGR_XXX defines.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h')
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h new file mode 100644 index 0000000000..3f952bcc6e --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com> + */ + +#ifndef _RESET_MANAGER_SOC64_H_ +#define _RESET_MANAGER_SOC64_H_ + +void reset_deassert_peripherals_handoff(void); +int cpu_has_been_warmreset(void); +void socfpga_bridges_reset(int enable); + +#define RSTMGR_SOC64_STATUS 0x00 +#define RSTMGR_SOC64_MPUMODRST 0x20 +#define RSTMGR_SOC64_PER0MODRST 0x24 +#define RSTMGR_SOC64_PER1MODRST 0x28 +#define RSTMGR_SOC64_BRGMODRST 0x2c + +#define RSTMGR_MPUMODRST_CORE0 0 +#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 +#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 +#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004 + +/* Watchdogs and MPU warm reset mask */ +#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00 + +/* + * SocFPGA Stratix10 reset IDs, bank mapping is as follows: + * 0 ... mpumodrst + * 1 ... per0modrst + * 2 ... per1modrst + * 3 ... brgmodrst + */ +#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0) +#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4) +#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16) + +#endif /* _RESET_MANAGER_SOC64_H_ */ |