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authorMasahiro Yamada <yamada.masahiro@socionext.com>2016-10-27 23:47:07 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2016-10-29 17:24:30 +0900
commit6dd34ae4c4cce6a4b9f62c9be55b343a6f0a35f8 (patch)
tree49480de9c7c85e14037a9145a8238e0d1fa9549a /arch/arm/mach-uniphier/dram/ddrphy-init.h
parent9c5313dc095ccab69dc9a0e100cdbda62369d4fb (diff)
ARM: uniphier: rework existing DDR PHY code to reuse for LD11 SoC
The DDR PHY register view of LD11 is slightly different from that of LD4/Pro4/sLD8, but it will be possible to share the register macros (and I want to re-use as much code as possible). Change the code in the more flexible form. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/dram/ddrphy-init.h')
-rw-r--r--arch/arm/mach-uniphier/dram/ddrphy-init.h20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-init.h b/arch/arm/mach-uniphier/dram/ddrphy-init.h
new file mode 100644
index 0000000000..3fc610baea
--- /dev/null
+++ b/arch/arm/mach-uniphier/dram/ddrphy-init.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_DDRPHY_INIT_H
+#define ARCH_DDRPHY_INTT_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+/* for LD4, Pro4, sLD8 */
+#define NR_DATX8_PER_DDRPHY 2
+
+int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus);
+void ddrphy_prepare_training(void __iomem *phy_base, int rank);
+int ddrphy_training(void __iomem *phy_base);
+
+#endif /* ARCH_DDRPHY_INT_H */