Merge u-boot/master into u-boot-ti/master

In master we had already taken a patch to fix the davinci GPIO code for
CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support
DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850).  Resolve these
conflicts manually and comment the #else/#endif lines for clarity.

Conflicts:
	arch/arm/include/asm/arch-davinci/gpio.h
	drivers/gpio/da8xx_gpio.c

Signed-off-by: Tom Rini <trini@ti.com>

10 files changed, 1031 insertions, 265 deletions

diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c
index 6a0bcca9f9..b9fdb078bd 100644
--- a/arch/blackfin/cpu/cpu.c
+++ b/arch/blackfin/cpu/cpu.c
@@ -68,7 +68,9 @@ void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
 	/* Reset upon a double exception rather than just hanging.
 	 * Do not do bfin_read on SWRST as that will reset status bits.
 	 */
+# ifdef SWRST
 	bfin_write_SWRST(DOUBLE_FAULT);
+# endif
 #endif
 
 	serial_early_puts("Board init flash\n");
@@ -92,7 +94,7 @@ int irq_init(void)
 #elif defined(SICA_IMASK0)
 	bfin_write_SICA_IMASK0(0);
 	bfin_write_SICA_IMASK1(0);
-#else
+#elif defined(SIC_IMASK)
 	bfin_write_SIC_IMASK(0);
 #endif
 	/* Set up a dummy NMI handler if needed.  */
diff --git a/arch/blackfin/cpu/gpio.c b/arch/blackfin/cpu/gpio.c
index 5674d42b6d..f684be531c 100644
--- a/arch/blackfin/cpu/gpio.c
+++ b/arch/blackfin/cpu/gpio.c
@@ -66,6 +66,14 @@ static struct gpio_port_t * const gpio_array[] = {
 	(struct gpio_port_t *)PORTH_FER,
 	(struct gpio_port_t *)PORTI_FER,
 	(struct gpio_port_t *)PORTJ_FER,
+#elif defined(CONFIG_BF60x)
+	(struct gpio_port_t *)PORTA_FER,
+	(struct gpio_port_t *)PORTB_FER,
+	(struct gpio_port_t *)PORTC_FER,
+	(struct gpio_port_t *)PORTD_FER,
+	(struct gpio_port_t *)PORTE_FER,
+	(struct gpio_port_t *)PORTF_FER,
+	(struct gpio_port_t *)PORTG_FER,
 #else
 # error no gpio arrays defined
 #endif
@@ -216,6 +224,12 @@ static void port_setup(unsigned gpio, unsigned short usage)
 	else
 		gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
 	SSYNC();
+#elif defined(CONFIG_BF60x)
+	if (usage == GPIO_USAGE)
+		gpio_array[gpio_bank(gpio)]->port_fer_clear = gpio_bit(gpio);
+	else
+		gpio_array[gpio_bank(gpio)]->port_fer_set = gpio_bit(gpio);
+	SSYNC();
 #endif
 }
 
@@ -290,7 +304,7 @@ static void portmux_setup(unsigned short per)
 		}
 	}
 }
-#elif defined(CONFIG_BF54x)
+#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
 inline void portmux_setup(unsigned short per)
 {
 	u32 pmux;
@@ -330,7 +344,7 @@ inline void portmux_setup(unsigned short per)
 # define portmux_setup(...)  do { } while (0)
 #endif
 
-#ifndef CONFIG_BF54x
+#if !defined(CONFIG_BF54x) && !defined(CONFIG_BF60x)
 /***********************************************************
 *
 * FUNCTIONS: Blackfin General Purpose Ports Access Functions
@@ -534,7 +548,7 @@ int peripheral_request(unsigned short per, const char *label)
 		 * be requested and used by several drivers
 		 */
 
-#ifdef CONFIG_BF54x
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
 		if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) {
 #else
 		if (!(per & P_MAYSHARE)) {
@@ -651,7 +665,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
 		       gpio, get_label(gpio));
 		return -EBUSY;
 	}
-#ifndef CONFIG_BF54x
+#if !defined(CONFIG_BF54x) && !defined(CONFIG_BF60x)
 	else {	/* Reset POLAR setting when acquiring a gpio for the first time */
 		set_gpio_polar(gpio, 0);
 	}
@@ -732,12 +746,16 @@ void bfin_special_gpio_free(unsigned gpio)
 
 static inline void __bfin_gpio_direction_input(unsigned gpio)
 {
-#ifdef CONFIG_BF54x
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
 	gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
 #else
 	gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
 #endif
+#if defined(CONFIG_BF60x)
+	gpio_array[gpio_bank(gpio)]->inen_set = gpio_bit(gpio);
+#else
 	gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
+#endif
 }
 
 int bfin_gpio_direction_input(unsigned gpio)
@@ -785,9 +803,13 @@ int bfin_gpio_direction_output(unsigned gpio, int value)
 
 	local_irq_save(flags);
 
+#if defined(CONFIG_BF60x)
+	gpio_array[gpio_bank(gpio)]->inen_clear = gpio_bit(gpio);
+#else
 	gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
+#endif
 	gpio_set_value(gpio, value);
-#ifdef CONFIG_BF54x
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
 	gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
 #else
 	gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
@@ -801,7 +823,7 @@ int bfin_gpio_direction_output(unsigned gpio, int value)
 
 int bfin_gpio_get_value(unsigned gpio)
 {
-#ifdef CONFIG_BF54x
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
 	return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)));
 #else
 	unsigned long flags;
diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c
index fb3a101c79..1a066806d1 100644
--- a/arch/blackfin/cpu/initcode.c
+++ b/arch/blackfin/cpu/initcode.c
@@ -15,20 +15,141 @@
 #include <asm/blackfin.h>
 #include <asm/mach-common/bits/bootrom.h>
 #include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/ebiu.h>
-#include <asm/mach-common/bits/pll.h>
-#include <asm/mach-common/bits/uart.h>
 
 #define BUG() while (1) { asm volatile("emuexcpt;"); }
 
 #include "serial.h"
 
+#ifndef __ADSPBF60x__
+#include <asm/mach-common/bits/ebiu.h>
+#include <asm/mach-common/bits/pll.h>
+#else /* __ADSPBF60x__ */
+#include <asm/mach-common/bits/cgu.h>
+
+#define CONFIG_BFIN_GET_DCLK_M \
+	((CONFIG_CLKIN_HZ*CONFIG_VCO_MULT)/(CONFIG_DCLK_DIV*1000000))
+
+#ifndef CONFIG_DMC_DDRCFG
+#if ((CONFIG_BFIN_GET_DCLK_M != 125) && \
+	(CONFIG_BFIN_GET_DCLK_M != 133) && \
+	(CONFIG_BFIN_GET_DCLK_M != 150) && \
+	(CONFIG_BFIN_GET_DCLK_M != 166) && \
+	(CONFIG_BFIN_GET_DCLK_M != 200) && \
+	(CONFIG_BFIN_GET_DCLK_M != 225) && \
+	(CONFIG_BFIN_GET_DCLK_M != 250))
+#error "DDR2 CLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
+#endif
+#endif
+
+/* DMC control bits */
+#define SRREQ			0x8
+
+/* DMC status bits */
+#define IDLE                    0x1
+#define MEMINITDONE             0x4
+#define SRACK                   0x8
+#define PDACK                   0x10
+#define DPDACK                  0x20
+#define DLLCALDONE              0x2000
+#define PENDREF                 0xF0000
+#define PHYRDPHASE              0xF00000
+#define PHYRDPHASE_OFFSET       20
+
+/* DMC DLL control bits */
+#define DLLCALRDCNT             0xFF
+#define DATACYC_OFFSET          8
+
+struct ddr_config {
+	u32 ddr_clk;
+	u32 dmc_ddrctl;
+	u32 dmc_ddrcfg;
+	u32 dmc_ddrtr0;
+	u32 dmc_ddrtr1;
+	u32 dmc_ddrtr2;
+	u32 dmc_ddrmr;
+	u32 dmc_ddrmr1;
+};
+
+static struct ddr_config ddr_config_table[] = {
+	[0] = {
+		.ddr_clk    = 125,	/* 125MHz */
+		.dmc_ddrctl = 0x00000904,
+		.dmc_ddrcfg = 0x00000422,
+		.dmc_ddrtr0 = 0x20705212,
+		.dmc_ddrtr1 = 0x201003CF,
+		.dmc_ddrtr2 = 0x00320107,
+		.dmc_ddrmr  = 0x00000422,
+		.dmc_ddrmr1 = 0x4,
+	},
+	[1] = {
+		.ddr_clk    = 133,	/* 133MHz */
+		.dmc_ddrctl = 0x00000904,
+		.dmc_ddrcfg = 0x00000422,
+		.dmc_ddrtr0 = 0x20806313,
+		.dmc_ddrtr1 = 0x2013040D,
+		.dmc_ddrtr2 = 0x00320108,
+		.dmc_ddrmr  = 0x00000632,
+		.dmc_ddrmr1 = 0x4,
+	},
+	[2] = {
+		.ddr_clk    = 150,	/* 150MHz */
+		.dmc_ddrctl = 0x00000904,
+		.dmc_ddrcfg = 0x00000422,
+		.dmc_ddrtr0 = 0x20A07323,
+		.dmc_ddrtr1 = 0x20160492,
+		.dmc_ddrtr2 = 0x00320209,
+		.dmc_ddrmr  = 0x00000632,
+		.dmc_ddrmr1 = 0x4,
+	},
+	[3] = {
+		.ddr_clk    = 166,	/* 166MHz */
+		.dmc_ddrctl = 0x00000904,
+		.dmc_ddrcfg = 0x00000422,
+		.dmc_ddrtr0 = 0x20A07323,
+		.dmc_ddrtr1 = 0x2016050E,
+		.dmc_ddrtr2 = 0x00320209,
+		.dmc_ddrmr  = 0x00000632,
+		.dmc_ddrmr1 = 0x4,
+	},
+	[4] = {
+		.ddr_clk    = 200,	/* 200MHz */
+		.dmc_ddrctl = 0x00000904,
+		.dmc_ddrcfg = 0x00000422,
+		.dmc_ddrtr0 = 0x20a07323,
+		.dmc_ddrtr1 = 0x2016050f,
+		.dmc_ddrtr2 = 0x00320509,
+		.dmc_ddrmr  = 0x00000632,
+		.dmc_ddrmr1 = 0x4,
+	},
+	[5] = {
+		.ddr_clk    = 225,	/* 225MHz */
+		.dmc_ddrctl = 0x00000904,
+		.dmc_ddrcfg = 0x00000422,
+		.dmc_ddrtr0 = 0x20E0A424,
+		.dmc_ddrtr1 = 0x302006DB,
+		.dmc_ddrtr2 = 0x0032020D,
+		.dmc_ddrmr  = 0x00000842,
+		.dmc_ddrmr1 = 0x4,
+	},
+	[6] = {
+		.ddr_clk    = 250,	/* 250MHz */
+		.dmc_ddrctl = 0x00000904,
+		.dmc_ddrcfg = 0x00000422,
+		.dmc_ddrtr0 = 0x20E0A424,
+		.dmc_ddrtr1 = 0x3020079E,
+		.dmc_ddrtr2 = 0x0032050D,
+		.dmc_ddrmr  = 0x00000842,
+		.dmc_ddrmr1 = 0x4,
+	},
+};
+#endif /* __ADSPBF60x__ */
+
 __attribute__((always_inline))
 static inline void serial_init(void)
 {
-	uint32_t uart_base = UART_DLL;
+	uint32_t uart_base = UART_BASE;
 
-#ifdef __ADSPBF54x__
+#if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
 # ifdef BFIN_BOOT_UART_USE_RTS
 #  define BFIN_UART_USE_RTS 1
 # else
@@ -38,7 +159,12 @@ static inline void serial_init(void)
 		size_t i;
 
 		/* force RTS rather than relying on auto RTS */
+#if BFIN_UART_HW_VER < 4
 		bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
+#else
+		bfin_write32(&pUART->control, bfin_read32(&pUART->control) |
+				FCPOL);
+#endif
 
 		/* Wait for the line to clear up.  We cannot rely on UART
 		 * registers as none of them reflect the status of the RSR.
@@ -68,13 +194,14 @@ static inline void serial_init(void)
 #endif
 
 	if (BFIN_DEBUG_EARLY_SERIAL) {
-		int ucen = bfin_read16(&pUART->gctl) & UCEN;
+		int enabled = serial_early_enabled(uart_base);
+
 		serial_early_init(uart_base);
 
 		/* If the UART is off, that means we need to program
 		 * the baud rate ourselves initially.
 		 */
-		if (ucen != UCEN)
+		if (!enabled)
 			serial_early_set_baud(uart_base, CONFIG_BAUDRATE);
 	}
 }
@@ -82,12 +209,17 @@ static inline void serial_init(void)
 __attribute__((always_inline))
 static inline void serial_deinit(void)
 {
-#ifdef __ADSPBF54x__
-	uint32_t uart_base = UART_DLL;
+#if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
+	uint32_t uart_base = UART_BASE;
 
 	if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 		/* clear forced RTS rather than relying on auto RTS */
+#if BFIN_UART_HW_VER < 4
 		bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
+#else
+		bfin_write32(&pUART->control, bfin_read32(&pUART->control) &
+				~FCPOL);
+#endif
 	}
 #endif
 }
@@ -95,7 +227,7 @@ static inline void serial_deinit(void)
 __attribute__((always_inline))
 static inline void serial_putc(char c)
 {
-	uint32_t uart_base = UART_DLL;
+	uint32_t uart_base = UART_BASE;
 
 	if (!BFIN_DEBUG_EARLY_SERIAL)
 		return;
@@ -103,9 +235,9 @@ static inline void serial_putc(char c)
 	if (c == '\n')
 		serial_putc('\r');
 
-	bfin_write16(&pUART->thr, c);
+	bfin_write(&pUART->thr, c);
 
-	while (!(bfin_read16(&pUART->lsr) & TEMT))
+	while (!(_lsr_read(pUART) & TEMT))
 		continue;
 }
 
@@ -152,6 +284,24 @@ program_nmi_handler(void)
 # define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
 #endif
 
+#ifdef __ADSPBF60x__
+
+#ifndef CONFIG_CGU_CTL_VAL
+# define CONFIG_CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CONFIG_CLKIN_HALF)
+#endif
+
+#ifndef CONFIG_CGU_DIV_VAL
+# define CONFIG_CGU_DIV_VAL \
+	((CONFIG_CCLK_DIV   << CSEL_P)   | \
+	 (CONFIG_SCLK0_DIV  << S0SEL_P)  | \
+	 (CONFIG_SCLK_DIV << SYSSEL_P) | \
+	 (CONFIG_SCLK1_DIV  << S1SEL_P)  | \
+	 (CONFIG_DCLK_DIV   << DSEL_P)   | \
+	 (CONFIG_OCLK_DIV   << OSEL_P))
+#endif
+
+#else /* __ADSPBF60x__ */
+
 /* PLL_DIV defines */
 #ifndef CONFIG_PLL_DIV_VAL
 # if (CONFIG_CCLK_DIV == 1)
@@ -275,6 +425,8 @@ program_nmi_handler(void)
 # endif
 #endif
 
+#endif /*  __ADSPBF60x__ */
+
 __attribute__((always_inline)) static inline void
 program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
 {
@@ -283,8 +435,14 @@ program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
 	/* Save the clock pieces that are used in baud rate calculation */
 	if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 		serial_putc('b');
+#ifdef __ADSPBF60x__
+		*sdivB = bfin_read_CGU_DIV();
+		*sdivB = ((*sdivB >> 8) & 0x1f) * ((*sdivB >> 5) & 0x7);
+		*vcoB = (bfin_read_CGU_CTL() >> 8) & 0x7f;
+#else
 		*sdivB = bfin_read_PLL_DIV() & 0xf;
 		*vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
+#endif
 		*divB = serial_early_get_div();
 		serial_putc('c');
 	}
@@ -303,8 +461,21 @@ program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
 	 */
 	if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
 		serial_putc('e');
+#ifdef __ADSPBF60x__
+		bfin_write_SEC_GCTL(0x2);
+		SSYNC();
+		bfin_write_SEC_FCTL(0xc1);
+		bfin_write_SEC_SCTL(2, bfin_read_SEC_SCTL(2) | 0x6);
+
+		bfin_write_SEC_CCTL(0x2);
+		SSYNC();
+		bfin_write_SEC_GCTL(0x1);
+		bfin_write_SEC_CCTL(0x1);
+#endif
 		bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
+#if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART
 		bfin_write_WDOG_CTL(0);
+#endif
 		serial_putc('f');
 	}
 #endif
@@ -316,6 +487,7 @@ program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
 	 * boot.  Once we switch over to u-boot's SPI flash driver, we'll
 	 * increase the speed appropriately.
 	 */
+#ifdef SPI_BAUD
 	if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
 		serial_putc('h');
 		if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
@@ -323,6 +495,7 @@ program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
 		bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
 		serial_putc('i');
 	}
+#endif
 
 	serial_putc('j');
 }
@@ -335,6 +508,15 @@ maybe_self_refresh(ADI_BOOT_DATA *bs)
 	if (!CONFIG_MEM_SIZE)
 		return false;
 
+#ifdef __ADSPBF60x__
+	/* resume from hibernate, return false let ddr initialize */
+	if ((bfin_read32(DPM0_STAT) & 0xF0) == 0x50) {
+		serial_putc('b');
+		return false;
+	}
+
+#else /* __ADSPBF60x__ */
+
 	/* If external memory is enabled, put it into self refresh first. */
 #if defined(EBIU_RSTCTL)
 	if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
@@ -350,6 +532,7 @@ maybe_self_refresh(ADI_BOOT_DATA *bs)
 	}
 #endif
 
+#endif /* __ADSPBF60x__ */
 	serial_putc('c');
 
 	return false;
@@ -362,6 +545,37 @@ program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
 
 	serial_putc('a');
 
+#ifdef __ADSPBF60x__
+	if (bfin_read_DMC0_STAT() & MEMINITDONE) {
+		bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
+		SSYNC();
+		while (!(bfin_read_DMC0_STAT() & SRACK))
+			continue;
+	}
+
+	/* Don't set the same value of MSEL and DF to CGU_CTL */
+	if ((bfin_read_CGU_CTL() & (MSEL_MASK | DF_MASK))
+			!= CONFIG_CGU_CTL_VAL) {
+		bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL);
+		bfin_write_CGU_CTL(CONFIG_CGU_CTL_VAL);
+		while ((bfin_read_CGU_STAT() & (CLKSALGN | PLLBP)) ||
+				!(bfin_read_CGU_STAT() & PLLLK))
+			continue;
+	}
+
+	bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL | UPDT);
+	while (bfin_read_CGU_STAT() & CLKSALGN)
+		continue;
+
+	if (bfin_read_DMC0_STAT() & MEMINITDONE) {
+		bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
+		SSYNC();
+		while (bfin_read_DMC0_STAT() & SRACK)
+			continue;
+	}
+
+#else /* __ADSPBF60x__ */
+
 	vr_ctl = bfin_read_VR_CTL();
 
 	serial_putc('b');
@@ -433,7 +647,7 @@ program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
 #elif defined(SICA_IWR0)
 		bfin_write_SICA_IWR0(1);
 		bfin_write_SICA_IWR1(0);
-#else
+#elif defined(SIC_IWR)
 		bfin_write_SIC_IWR(1);
 #endif
 
@@ -482,13 +696,15 @@ program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
 #elif defined(SICA_IWR0)
 		bfin_write_SICA_IWR0(-1);
 		bfin_write_SICA_IWR1(-1);
-#else
+#elif defined(SIC_IWR)
 		bfin_write_SIC_IWR(-1);
 #endif
 
 		serial_putc('n');
 	}
 
+#endif /* __ADSPBF60x__ */
+
 	serial_putc('o');
 
 	return vr_ctl;
@@ -505,16 +721,25 @@ update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
 	 * for dividing which means we'd generate a libgcc reference.
 	 */
 	if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
-		serial_putc('b');
 		unsigned int sdivR, vcoR;
-		sdivR = bfin_read_PLL_DIV() & 0xf;
-		vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
 		int dividend = sdivB * divB * vcoR;
 		int divisor = vcoB * sdivR;
 		unsigned int quotient;
+
+		serial_putc('b');
+
+#ifdef __ADSPBF60x__
+		sdivR = bfin_read_CGU_DIV();
+		sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7);
+		vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f;
+#else
+		sdivR = bfin_read_PLL_DIV() & 0xf;
+		vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
+#endif
+
 		for (quotient = 0; dividend > 0; ++quotient)
 			dividend -= divisor;
-		serial_early_put_div(UART_DLL, quotient - ANOMALY_05000230);
+		serial_early_put_div(quotient - ANOMALY_05000230);
 		serial_putc('c');
 	}
 
@@ -531,6 +756,85 @@ program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
 
 	serial_putc('b');
 
+#ifdef __ADSPBF60x__
+	int dlldatacycle;
+	int dll_ctl;
+	int i = 0;
+
+	if (CONFIG_BFIN_GET_DCLK_M ==  125)
+		i = 0;
+	else if (CONFIG_BFIN_GET_DCLK_M ==  133)
+		i = 1;
+	else if (CONFIG_BFIN_GET_DCLK_M ==  150)
+		i = 2;
+	else if (CONFIG_BFIN_GET_DCLK_M ==  166)
+		i = 3;
+	else if (CONFIG_BFIN_GET_DCLK_M ==  200)
+		i = 4;
+	else if (CONFIG_BFIN_GET_DCLK_M ==  225)
+		i = 5;
+	else if (CONFIG_BFIN_GET_DCLK_M ==  250)
+		i = 6;
+
+#if 0
+	for (i = 0; i < ARRAY_SIZE(ddr_config_table); i++)
+		if (CONFIG_BFIN_GET_DCLK_M == ddr_config_table[i].ddr_clk)
+			break;
+#endif
+
+#ifndef CONFIG_DMC_DDRCFG
+	bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
+#else
+	bfin_write_DMC0_CFG(CONFIG_DMC_DDRCFG);
+#endif
+#ifndef CONFIG_DMC_DDRTR0
+	bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
+#else
+	bfin_write_DMC0_TR0(CONFIG_DMC_DDRTR0);
+#endif
+#ifndef CONFIG_DMC_DDRTR1
+	bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
+#else
+	bfin_write_DMC0_TR1(CONFIG_DMC_DDRTR1);
+#endif
+#ifndef CONFIG_DMC_DDRTR2
+	bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
+#else
+	bfin_write_DMC0_TR2(CONFIG_DMC_DDRTR2);
+#endif
+#ifndef CONFIG_DMC_DDRMR
+	bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
+#else
+	bfin_write_DMC0_MR(CONFIG_DMC_DDRMR);
+#endif
+#ifndef CONFIG_DMC_DDREMR1
+	bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
+#else
+	bfin_write_DMC0_EMR1(CONFIG_DMC_DDREMR1);
+#endif
+#ifndef CONFIG_DMC_DDRCTL
+	bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
+#else
+	bfin_write_DMC0_CTL(CONFIG_DMC_DDRCTL);
+#endif
+
+	SSYNC();
+	while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
+		continue;
+
+	dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >>
+			PHYRDPHASE_OFFSET;
+	dll_ctl = bfin_read_DMC0_DLLCTL();
+	dll_ctl &= 0x0ff;
+	bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
+
+	SSYNC();
+	while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
+		continue;
+	serial_putc('!');
+
+#else /* __ADSPBF60x__ */
+
 	/* Program the external memory controller before we come out of
 	 * self-refresh.  This only works with our SDRAM controller.
 	 */
@@ -583,6 +887,7 @@ program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
 # endif
 #endif
 
+#endif /* __ADSPBF60x__ */
 	serial_putc('e');
 }
 
@@ -595,7 +900,46 @@ check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
 		return;
 
 	serial_putc('b');
+#ifdef __ADSPBF60x__
+	if (bfin_read32(DPM0_RESTORE0) != 0) {
+		uint32_t reg = bfin_read_DMC0_CTL();
+		reg &= ~0x8;
+		bfin_write_DMC0_CTL(reg);
+
+		while ((bfin_read_DMC0_STAT() & 0x8))
+			continue;
+		while (!(bfin_read_DMC0_STAT() & 0x1))
+			continue;
+
+		serial_putc('z');
+		uint32_t *hibernate_magic = bfin_read32(DPM0_RESTORE4);
+		SSYNC(); /* make sure memory controller is done */
+		if (hibernate_magic[0] == 0xDEADBEEF) {
+			serial_putc('c');
+			SSYNC();
+			bfin_write_EVT15(hibernate_magic[1]);
+			bfin_write_IMASK(EVT_IVG15);
+			__asm__ __volatile__ (
+				/* load reti early to avoid anomaly 281 */
+				"reti = %2;"
+				/* clear hibernate magic */
+				"[%0] = %1;"
+				/* load stack pointer */
+				"SP = [%0 + 8];"
+				/* lower ourselves from reset ivg to ivg15 */
+				"raise 15;"
+				"nop;nop;nop;"
+				"rti;"
+				:
+				: "p"(hibernate_magic),
+				"d"(0x2000 /* jump.s 0 */),
+				"d"(0xffa00000)
+			);
+		}
+
 
+	}
+#else
 	/* Are we coming out of hibernate (suspend to memory) ?
 	 * The memory layout is:
 	 * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
@@ -606,7 +950,8 @@ check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
 	 */
 	if (ANOMALY_05000307 || vr_ctl & 0x8000) {
 		uint32_t *hibernate_magic = 0;
-		__builtin_bfin_ssync(); /* make sure memory controller is done */
+
+		SSYNC();
 		if (hibernate_magic[0] == 0xDEADBEEF) {
 			serial_putc('c');
 			bfin_write_EVT15(hibernate_magic[1]);
@@ -627,6 +972,7 @@ check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
 		}
 		serial_putc('d');
 	}
+#endif
 
 	serial_putc('e');
 }
diff --git a/arch/blackfin/cpu/initcode.h b/arch/blackfin/cpu/initcode.h
index e0aad6de0f..1fec7f3d85 100644
--- a/arch/blackfin/cpu/initcode.h
+++ b/arch/blackfin/cpu/initcode.h
@@ -15,6 +15,8 @@
 # define serial_putc(c)
 #endif
 
+#ifndef __ADSPBF60x__
+
 #ifndef CONFIG_EBIU_RSTCTL_VAL
 # define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
 #endif
@@ -30,6 +32,8 @@
 # error invalid EBIU_DDRQUE value: must not set reserved bits
 #endif
 
+#endif /* __ADSPBF60x__ */
+
 __attribute__((always_inline)) static inline void
 program_async_controller(ADI_BOOT_DATA *bs)
 {
@@ -45,10 +49,13 @@ program_async_controller(ADI_BOOT_DATA *bs)
 
 	serial_putc('a');
 
+#ifdef __ADSPBF60x__
 	/* Program the async banks controller. */
+#ifdef EBIU_AMGCTL
 	bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
 	bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
 	bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
+#endif
 
 	serial_putc('b');
 
@@ -66,6 +73,51 @@ program_async_controller(ADI_BOOT_DATA *bs)
 #endif
 
 	serial_putc('c');
+
+#else   /* __ADSPBF60x__ */
+	/* Program the static memory controller. */
+# ifdef CONFIG_SMC_GCTL_VAL
+	bfin_write_SMC_GCTL(CONFIG_SMC_GCTL_VAL);
+# endif
+# ifdef CONFIG_SMC_B0CTL_VAL
+	bfin_write_SMC_B0CTL(CONFIG_SMC_B0CTL_VAL);
+# endif
+# ifdef CONFIG_SMC_B0TIM_VAL
+	bfin_write_SMC_B0TIM(CONFIG_SMC_B0TIM_VAL);
+# endif
+# ifdef CONFIG_SMC_B0ETIM_VAL
+	bfin_write_SMC_B0ETIM(CONFIG_SMC_B0ETIM_VAL);
+# endif
+# ifdef CONFIG_SMC_B1CTL_VAL
+	bfin_write_SMC_B1CTL(CONFIG_SMC_B1CTL_VAL);
+# endif
+# ifdef CONFIG_SMC_B1TIM_VAL
+	bfin_write_SMC_B1TIM(CONFIG_SMC_B1TIM_VAL);
+# endif
+# ifdef CONFIG_SMC_B1ETIM_VAL
+	bfin_write_SMC_B1ETIM(CONFIG_SMC_B1ETIM_VAL);
+# endif
+# ifdef CONFIG_SMC_B2CTL_VAL
+	bfin_write_SMC_B2CTL(CONFIG_SMC_B2CTL_VAL);
+# endif
+# ifdef CONFIG_SMC_B2TIM_VAL
+	bfin_write_SMC_B2TIM(CONFIG_SMC_B2TIM_VAL);
+# endif
+# ifdef CONFIG_SMC_B2ETIM_VAL
+	bfin_write_SMC_B2ETIM(CONFIG_SMC_B2ETIM_VAL);
+# endif
+# ifdef CONFIG_SMC_B3CTL_VAL
+	bfin_write_SMC_B3CTL(CONFIG_SMC_B3CTL_VAL);
+# endif
+# ifdef CONFIG_SMC_B3TIM_VAL
+	bfin_write_SMC_B3TIM(CONFIG_SMC_B3TIM_VAL);
+# endif
+# ifdef CONFIG_SMC_B3ETIM_VAL
+	bfin_write_SMC_B3ETIM(CONFIG_SMC_B3ETIM_VAL);
+# endif
+
+#endif
+	serial_putc('d');
 }
 
 #endif
diff --git a/arch/blackfin/cpu/reset.c b/arch/blackfin/cpu/reset.c
index ff39035de2..b6718d3bb5 100644
--- a/arch/blackfin/cpu/reset.c
+++ b/arch/blackfin/cpu/reset.c
@@ -23,6 +23,7 @@
 __attribute__ ((__l1_text__, __noreturn__))
 static void bfin_reset(void)
 {
+#ifdef SWRST
 	/* Wait for completion of "system" events such as cache line
 	 * line fills so that we avoid infinite stalls later on as
 	 * much as possible.  This code is in L1, so it won't trigger
@@ -66,10 +67,15 @@ static void bfin_reset(void)
 		: "a" (15 * 1)
 		: "LC1", "LB1", "LT1"
 	);
+#endif
 
 	while (1)
+#if defined(__ADSPBF60x__)
+		bfin_write_RCU0_CTL(0x1);
+#else
 		/* Issue core reset */
 		asm("raise 1");
+#endif
 }
 
 /* We need to trampoline ourselves up into L1 since our linker
diff --git a/arch/blackfin/cpu/serial.c b/arch/blackfin/cpu/serial.c
index 64340ec67d..9847e9f2c5 100644
--- a/arch/blackfin/cpu/serial.c
+++ b/arch/blackfin/cpu/serial.c
@@ -43,7 +43,6 @@
 #include <serial.h>
 #include <linux/compiler.h>
 #include <asm/blackfin.h>
-#include <asm/mach-common/bits/uart.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -52,8 +51,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #include "serial.h"
 
 #ifdef CONFIG_DEBUG_SERIAL
-static uint16_t cached_lsr[256];
-static uint16_t cached_rbr[256];
+static uart_lsr_t cached_lsr[256];
+static uart_lsr_t cached_rbr[256];
 static size_t cache_count;
 
 /* The LSR is read-to-clear on some parts, so we have to make sure status
@@ -61,10 +60,10 @@ static size_t cache_count;
  * works around anomaly 05000099 at the same time by keeping a cumulative
  * tally of all the status bits.
  */
-static uint16_t uart_lsr_save;
-static uint16_t uart_lsr_read(uint32_t uart_base)
+static uart_lsr_t uart_lsr_save;
+static uart_lsr_t uart_lsr_read(uint32_t uart_base)
 {
-	uint16_t lsr = bfin_read(&pUART->lsr);
+	uart_lsr_t lsr = _lsr_read(pUART);
 	uart_lsr_save |= (lsr & (OE|PE|FE|BI));
 	return lsr | uart_lsr_save;
 }
@@ -72,20 +71,20 @@ static uint16_t uart_lsr_read(uint32_t uart_base)
 static void uart_lsr_clear(uint32_t uart_base)
 {
 	uart_lsr_save = 0;
-	bfin_write(&pUART->lsr, bfin_read(&pUART->lsr) | -1);
+	_lsr_write(pUART, -1);
 }
 #else
 /* When debugging is disabled, we only care about the DR bit, so if other
  * bits get set/cleared, we don't really care since we don't read them
  * anyways (and thus anomaly 05000099 is irrelevant).
  */
-static inline uint16_t uart_lsr_read(uint32_t uart_base)
+static inline uart_lsr_t uart_lsr_read(uint32_t uart_base)
 {
-	return bfin_read(&pUART->lsr);
+	return _lsr_read(pUART);
 }
 static void uart_lsr_clear(uint32_t uart_base)
 {
-	bfin_write(&pUART->lsr, bfin_read(&pUART->lsr) | -1);
+	_lsr_write(pUART, -1);
 }
 #endif
 
@@ -127,20 +126,14 @@ static int uart_getc(uint32_t uart_base)
 
 #ifdef CONFIG_DEBUG_SERIAL
 	/* grab & clear the LSR */
-	uint16_t uart_lsr_val = uart_lsr_read(uart_base);
+	uart_lsr_t uart_lsr_val = uart_lsr_read(uart_base);
 
 	cached_lsr[cache_count] = uart_lsr_val;
 	cached_rbr[cache_count] = uart_rbr_val;
 	cache_count = (cache_count + 1) % ARRAY_SIZE(cached_lsr);
 
 	if (uart_lsr_val & (OE|PE|FE|BI)) {
-		uint16_t dll, dlh;
 		printf("\n[SERIAL ERROR]\n");
-		ACCESS_LATCH();
-		dll = bfin_read(&pUART->dll);
-		dlh = bfin_read(&pUART->dlh);
-		ACCESS_PORT_IER();
-		printf("\tDLL=0x%x DLH=0x%x\n", dll, dlh);
 		do {
 			--cache_count;
 			printf("\t%3zu: RBR=0x%02x LSR=0x%02x\n", cache_count,
@@ -160,6 +153,8 @@ static int uart_getc(uint32_t uart_base)
 # define LOOP(x)
 #endif
 
+#if BFIN_UART_HW_VER < 4
+
 LOOP(
 static void uart_loop(uint32_t uart_base, int state)
 {
@@ -178,6 +173,28 @@ static void uart_loop(uint32_t uart_base, int state)
 }
 )
 
+#else
+
+LOOP(
+static void uart_loop(uint32_t uart_base, int state)
+{
+	u32 control;
+
+	/* Drain the TX fifo first so bytes don't come back */
+	while (!(uart_lsr_read(uart_base) & TEMT))
+		continue;
+
+	control = bfin_read(&pUART->control);
+	if (state)
+		control |= LOOP_ENA | MRTS;
+	else
+		control &= ~(LOOP_ENA | MRTS);
+	bfin_write(&pUART->control, control);
+}
+)
+
+#endif
+
 #ifdef CONFIG_SYS_BFIN_UART
 
 static void uart_puts(uint32_t uart_base, const char *s)
@@ -246,16 +263,16 @@ struct serial_device bfin_serial##n##_device = { \
 	LOOP(.loop = uart##n##_loop) \
 };
 
-#ifdef UART0_DLL
+#ifdef UART0_RBR
 DECL_BFIN_UART(0)
 #endif
-#ifdef UART1_DLL
+#ifdef UART1_RBR
 DECL_BFIN_UART(1)
 #endif
-#ifdef UART2_DLL
+#ifdef UART2_RBR
 DECL_BFIN_UART(2)
 #endif
-#ifdef UART3_DLL
+#ifdef UART3_RBR
 DECL_BFIN_UART(3)
 #endif
 
@@ -274,16 +291,16 @@ __weak struct serial_device *default_serial_console(void)
 
 void bfin_serial_initialize(void)
 {
-#ifdef UART0_DLL
+#ifdef UART0_RBR
 	serial_register(&bfin_serial0_device);
 #endif
-#ifdef UART1_DLL
+#ifdef UART1_RBR
 	serial_register(&bfin_serial1_device);
 #endif
-#ifdef UART2_DLL
+#ifdef UART2_RBR
 	serial_register(&bfin_serial2_device);
 #endif
-#ifdef UART3_DLL
+#ifdef UART3_RBR
 	serial_register(&bfin_serial3_device);
 #endif
 }
@@ -293,7 +310,7 @@ void bfin_serial_initialize(void)
 /* Symbol for our assembly to call. */
 void serial_set_baud(uint32_t baud)
 {
-	serial_early_set_baud(UART_DLL, baud);
+	serial_early_set_baud(UART_BASE, baud);
 }
 
 /* Symbol for common u-boot code to call.
@@ -307,7 +324,7 @@ void serial_setbrg(void)
 /* Symbol for our assembly to call. */
 void serial_initialize(void)
 {
-	serial_early_init(UART_DLL);
+	serial_early_init(UART_BASE);
 }
 
 /* Symbol for common u-boot code to call. */
@@ -315,23 +332,23 @@ int serial_init(void)
 {
 	serial_initialize();
 	serial_setbrg();
-	uart_lsr_clear(UART_DLL);
+	uart_lsr_clear(UART_BASE);
 	return 0;
 }
 
 int serial_tstc(void)
 {
-	return uart_tstc(UART_DLL);
+	return uart_tstc(UART_BASE);
 }
 
 int serial_getc(void)
 {
-	return uart_getc(UART_DLL);
+	return uart_getc(UART_BASE);
 }
 
 void serial_putc(const char c)
 {
-	uart_putc(UART_DLL, c);
+	uart_putc(UART_BASE, c);
 }
 
 void serial_puts(const char *s)
@@ -343,7 +360,7 @@ void serial_puts(const char *s)
 LOOP(
 void serial_loop(int state)
 {
-	uart_loop(UART_DLL, state);
+	uart_loop(UART_BASE, state);
 }
 )
 
diff --git a/arch/blackfin/cpu/serial.h b/arch/blackfin/cpu/serial.h
index 8a076ddc92..9200339668 100644
--- a/arch/blackfin/cpu/serial.h
+++ b/arch/blackfin/cpu/serial.h
@@ -3,7 +3,7 @@
  *            any functions defined here must be always_inline since
  *            initcode cannot have function calls.
  *
- * Copyright (c) 2004-2007 Analog Devices Inc.
+ * Copyright (c) 2004-2011 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -12,7 +12,7 @@
 #define __BFIN_CPU_SERIAL_H__
 
 #include <asm/blackfin.h>
-#include <asm/mach-common/bits/uart.h>
+#include <asm/portmux.h>
 
 #ifndef CONFIG_UART_CONSOLE
 # define CONFIG_UART_CONSOLE 0
@@ -24,88 +24,34 @@
 # define BFIN_DEBUG_EARLY_SERIAL 0
 #endif
 
-#ifndef __ASSEMBLY__
-
-#include <asm/portmux.h>
-
-#define LOB(x) ((x) & 0xFF)
-#define HIB(x) (((x) >> 8) & 0xFF)
-
-#if defined(__ADSPBF50x__) || defined(__ADSPBF54x__)
+#if defined(__ADSPBF60x__)
+# define BFIN_UART_HW_VER 4
+#elif defined(__ADSPBF50x__) || defined(__ADSPBF54x__)
 # define BFIN_UART_HW_VER 2
 #else
 # define BFIN_UART_HW_VER 1
 #endif
 
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits.  So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-struct bfin_mmr_serial {
-#if BFIN_UART_HW_VER == 2
-	__BFP(dll);
-	__BFP(dlh);
-	__BFP(gctl);
-	__BFP(lcr);
-	__BFP(mcr);
-	__BFP(lsr);
-	__BFP(msr);
-	__BFP(scr);
-	__BFP(ier_set);
-	__BFP(ier_clear);
-	__BFP(thr);
-	__BFP(rbr);
-#else
-	union {
-		u16 dll;
-		u16 thr;
-		const u16 rbr;
-	};
-	const u16 __spad0;
-	union {
-		u16 dlh;
-		u16 ier;
-	};
-	const u16 __spad1;
-	const __BFP(iir);
-	__BFP(lcr);
-	__BFP(mcr);
-	__BFP(lsr);
-	__BFP(msr);
-	__BFP(scr);
-	const u32 __spad2;
-	__BFP(gctl);
-#endif
-};
-#undef __BFP
-
 #define __PASTE_UART(num, pfx, sfx) pfx##num##_##sfx
 #define _PASTE_UART(num, pfx, sfx) __PASTE_UART(num, pfx, sfx)
-#define MMR_UART(n) _PASTE_UART(n, UART, DLL)
 #define _P_UART(n, pin) _PASTE_UART(n, P_UART, pin)
 #define P_UART(pin) _P_UART(CONFIG_UART_CONSOLE, pin)
 
-#ifndef UART_DLL
-# define UART_DLL MMR_UART(CONFIG_UART_CONSOLE)
-#else
-# define UART0_DLL UART_DLL
-# if CONFIG_UART_CONSOLE != 0
-#  error CONFIG_UART_CONSOLE must be 0 on parts with only one UART
-# endif
-#endif
 #define pUART ((volatile struct bfin_mmr_serial *)uart_base)
 
-#if BFIN_UART_HW_VER == 2
-# define ACCESS_LATCH()
-# define ACCESS_PORT_IER()
+#ifndef __ASSEMBLY__
+__attribute__((always_inline))
+static inline void serial_do_portmux(void);
+#endif
+
+#if BFIN_UART_HW_VER < 4
+# include "serial1.h"
 #else
-# define ACCESS_LATCH() \
-	bfin_write(&pUART->lcr, bfin_read(&pUART->lcr) | DLAB)
-# define ACCESS_PORT_IER() \
-	bfin_write(&pUART->lcr, bfin_read(&pUART->lcr) & ~DLAB)
+# include "serial4.h"
 #endif
 
+#ifndef __ASSEMBLY__
+
 __attribute__((always_inline))
 static inline void serial_do_portmux(void)
 {
@@ -115,143 +61,7 @@ static inline void serial_do_portmux(void)
 		return;
 	}
 
-#if defined(__ADSPBF50x__)
-# define DO_MUX(port, mux_tx, mux_rx, tx, rx) \
-	bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_1 | PORT_x_MUX_##mux_rx##_FUNC_1); \
-	bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
-	switch (CONFIG_UART_CONSOLE) {
-	case 0: DO_MUX(G, 7, 7, 12, 13); break;	/* Port G; mux 7; PG12 and PG13 */
-	case 1: DO_MUX(F, 3, 3, 6, 7);   break;	/* Port F; mux 3; PF6 and PF7 */
-	}
-	SSYNC();
-#elif defined(__ADSPBF51x__)
-# define DO_MUX(port, mux_tx, mux_rx, tx, rx) \
-	bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_2 | PORT_x_MUX_##mux_rx##_FUNC_2); \
-	bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
-	switch (CONFIG_UART_CONSOLE) {
-	case 0: DO_MUX(G, 5, 5, 9, 10);  break;	/* Port G; mux 5; PG9 and PG10 */
-	case 1: DO_MUX(F, 2, 3, 14, 15); break;	/* Port H; mux 2/3; PH14 and PH15 */
-	}
-	SSYNC();
-#elif defined(__ADSPBF52x__)
-# define DO_MUX(port, mux, tx, rx) \
-	bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_3); \
-	bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
-	switch (CONFIG_UART_CONSOLE) {
-	case 0: DO_MUX(G, 2, 7, 8);   break;	/* Port G; mux 2; PG2 and PG8 */
-	case 1: DO_MUX(F, 5, 14, 15); break;	/* Port F; mux 5; PF14 and PF15 */
-	}
-	SSYNC();
-#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
-	const uint16_t func[] = { PFDE, PFTE, };
-	bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~func[CONFIG_UART_CONSOLE]);
-	bfin_write_PORTF_FER(bfin_read_PORTF_FER() |
-	                     (1 << P_IDENT(P_UART(RX))) |
-	                     (1 << P_IDENT(P_UART(TX))));
-	SSYNC();
-#elif defined(__ADSPBF54x__)
-# define DO_MUX(port, tx, rx) \
-	bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##tx##_MASK | PORT_x_MUX_##rx##_MASK)) | PORT_x_MUX_##tx##_FUNC_1 | PORT_x_MUX_##rx##_FUNC_1); \
-	bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
-	switch (CONFIG_UART_CONSOLE) {
-	case 0: DO_MUX(E, 7, 8); break;	/* Port E; PE7 and PE8 */
-	case 1: DO_MUX(H, 0, 1); break;	/* Port H; PH0 and PH1 */
-	case 2: DO_MUX(B, 4, 5); break;	/* Port B; PB4 and PB5 */
-	case 3: DO_MUX(B, 6, 7); break;	/* Port B; PB6 and PB7 */
-	}
-	SSYNC();
-#elif defined(__ADSPBF561__)
-	/* UART pins could be GPIO, but they aren't pin muxed.  */
-#else
-# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED)
-#  error "missing portmux logic for UART"
-# endif
-#endif
-}
-
-__attribute__((always_inline))
-static inline int uart_init(uint32_t uart_base)
-{
-	/* always enable UART -- avoids anomalies 05000309 and 05000350 */
-	bfin_write(&pUART->gctl, UCEN);
-
-	/* Set LCR to Word Lengh 8-bit word select */
-	bfin_write(&pUART->lcr, WLS_8);
-
-	SSYNC();
-
-	return 0;
-}
-
-__attribute__((always_inline))
-static inline int serial_early_init(uint32_t uart_base)
-{
-	/* handle portmux crap on different Blackfins */
-	serial_do_portmux();
-
-	return uart_init(uart_base);
-}
-
-__attribute__((always_inline))
-static inline int serial_early_uninit(uint32_t uart_base)
-{
-	/* disable the UART by clearing UCEN */
-	bfin_write(&pUART->gctl, 0);
-
-	return 0;
-}
-
-__attribute__((always_inline))
-static inline void serial_early_put_div(uint32_t uart_base, uint16_t divisor)
-{
-	/* Set DLAB in LCR to Access DLL and DLH */
-	ACCESS_LATCH();
-	SSYNC();
-
-	/* Program the divisor to get the baud rate we want */
-	bfin_write(&pUART->dll, LOB(divisor));
-	bfin_write(&pUART->dlh, HIB(divisor));
-	SSYNC();
-
-	/* Clear DLAB in LCR to Access THR RBR IER */
-	ACCESS_PORT_IER();
-	SSYNC();
-}
-
-__attribute__((always_inline))
-static inline uint16_t serial_early_get_div(void)
-{
-	uint32_t uart_base = UART_DLL;
-
-	/* Set DLAB in LCR to Access DLL and DLH */
-	ACCESS_LATCH();
-	SSYNC();
-
-	uint8_t dll = bfin_read(&pUART->dll);
-	uint8_t dlh = bfin_read(&pUART->dlh);
-	uint16_t divisor = (dlh << 8) | dll;
-
-	/* Clear DLAB in LCR to Access THR RBR IER */
-	ACCESS_PORT_IER();
-	SSYNC();
-
-	return divisor;
-}
-
-/* We cannot use get_sclk() early on as it uses caches in external memory */
-#if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL)
-# define get_sclk() (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV)
-#endif
-
-__attribute__((always_inline))
-static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
-{
-	/* Translate from baud into divisor in terms of SCLK.  The
-	 * weird multiplication is to make sure we over sample just
-	 * a little rather than under sample the incoming signals.
-	 */
-	serial_early_put_div(uart_base,
-		(get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230);
+	serial_early_do_portmux();
 }
 
 #ifndef BFIN_IN_INITCODE
diff --git a/arch/blackfin/cpu/serial1.h b/arch/blackfin/cpu/serial1.h
new file mode 100644
index 0000000000..a20175bc7f
--- /dev/null
+++ b/arch/blackfin/cpu/serial1.h
@@ -0,0 +1,348 @@
+/*
+ * serial.h - common serial defines for early debug and serial driver.
+ *            any functions defined here must be always_inline since
+ *            initcode cannot have function calls.
+ *
+ * Copyright (c) 2004-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_CPU_SERIAL1_H__
+#define __BFIN_CPU_SERIAL1_H__
+
+#include <asm/mach-common/bits/uart.h>
+
+#ifndef __ASSEMBLY__
+
+#define MMR_UART(n) _PASTE_UART(n, UART, DLL)
+#ifdef UART_DLL
+# define UART0_DLL UART_DLL
+# if CONFIG_UART_CONSOLE != 0
+#  error CONFIG_UART_CONSOLE must be 0 on parts with only one UART
+# endif
+#endif
+#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE)
+
+#define LOB(x) ((x) & 0xFF)
+#define HIB(x) (((x) >> 8) & 0xFF)
+
+/*
+ * All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits.  So use a helper macro to streamline this.
+ */
+struct bfin_mmr_serial {
+#if BFIN_UART_HW_VER == 2
+	u16 dll;
+	u16 __pad_0;
+	u16 dlh;
+	u16 __pad_1;
+	u16 gctl;
+	u16 __pad_2;
+	u16 lcr;
+	u16 __pad_3;
+	u16 mcr;
+	u16 __pad_4;
+	u16 lsr;
+	u16 __pad_5;
+	u16 msr;
+	u16 __pad_6;
+	u16 scr;
+	u16 __pad_7;
+	u16 ier_set;
+	u16 __pad_8;
+	u16 ier_clear;
+	u16 __pad_9;
+	u16 thr;
+	u16 __pad_10;
+	u16 rbr;
+	u16 __pad_11;
+#else
+	union {
+		u16 dll;
+		u16 thr;
+		const u16 rbr;
+	};
+	const u16 __spad0;
+	union {
+		u16 dlh;
+		u16 ier;
+	};
+	const u16 __spad1;
+	const u16 iir;
+	u16 __pad_0;
+	u16 lcr;
+	u16 __pad_1;
+	u16 mcr;
+	u16 __pad_2;
+	u16 lsr;
+	u16 __pad_3;
+	u16 msr;
+	u16 __pad_4;
+	u16 scr;
+	u16 __pad_5;
+	const u32 __spad2;
+	u16 gctl;
+	u16 __pad_6;
+#endif
+};
+
+#define uart_lsr_t uint32_t
+#define _lsr_read(p)     bfin_read(&p->lsr)
+#define _lsr_write(p, v) bfin_write(&p->lsr, v)
+
+#if BFIN_UART_HW_VER == 2
+# define ACCESS_LATCH()
+# define ACCESS_PORT_IER()
+#else
+# define ACCESS_LATCH()    bfin_write_or(&pUART->lcr, DLAB)
+# define ACCESS_PORT_IER() bfin_write_and(&pUART->lcr, ~DLAB)
+#endif
+
+__attribute__((always_inline))
+static inline void serial_early_do_mach_portmux(char port, int mux_mask,
+	int mux_func, int port_pin)
+{
+	switch (port) {
+#if defined(__ADSPBF54x__)
+	case 'B':
+		bfin_write_PORTB_MUX((bfin_read_PORTB_MUX() &
+			~mux_mask) | mux_func);
+		bfin_write_PORTB_FER(bfin_read_PORTB_FER() | port_pin);
+		break;
+	case 'E':
+		bfin_write_PORTE_MUX((bfin_read_PORTE_MUX() &
+			~mux_mask) | mux_func);
+		bfin_write_PORTE_FER(bfin_read_PORTE_FER() | port_pin);
+		break;
+#endif
+#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF52x__)
+	case 'F':
+		bfin_write_PORTF_MUX((bfin_read_PORTF_MUX() &
+			~mux_mask) | mux_func);
+		bfin_write_PORTF_FER(bfin_read_PORTF_FER() | port_pin);
+		break;
+	case 'G':
+		bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() &
+			~mux_mask) | mux_func);
+		bfin_write_PORTG_FER(bfin_read_PORTG_FER() | port_pin);
+		break;
+	case 'H':
+		bfin_write_PORTH_MUX((bfin_read_PORTH_MUX() &
+			~mux_mask) | mux_func);
+		bfin_write_PORTH_FER(bfin_read_PORTH_FER() | port_pin);
+		break;
+#endif
+	default:
+		break;
+	}
+}
+
+__attribute__((always_inline))
+static inline void serial_early_do_portmux(void)
+{
+#if defined(__ADSPBF50x__)
+	switch (CONFIG_UART_CONSOLE) {
+	case 0:
+		serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK,
+		PORT_x_MUX_7_FUNC_1, PG12); /* TX: G; mux 7; func 1; PG12 */
+		serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK,
+		PORT_x_MUX_7_FUNC_1, PG13); /* RX: G; mux 7; func 1; PG13 */
+		break;
+	case 1:
+		serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK,
+		PORT_x_MUX_3_FUNC_1, PF7); /* TX: F; mux 3; func 1; PF6 */
+		serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK,
+		PORT_x_MUX_3_FUNC_1, PF6); /* RX: F; mux 3; func 1; PF7 */
+		break;
+	}
+#elif defined(__ADSPBF51x__)
+	switch (CONFIG_UART_CONSOLE) {
+	case 0:
+		serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK,
+		PORT_x_MUX_5_FUNC_2, PG9); /* TX: G; mux 5; func 2; PG9 */
+		serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK,
+		PORT_x_MUX_5_FUNC_2, PG10); /* RX: G; mux 5; func 2; PG10 */
+		break;
+	case 1:
+		serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK,
+		PORT_x_MUX_3_FUNC_2, PH7); /* TX: H; mux 3; func 2; PH6 */
+		serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK,
+		PORT_x_MUX_3_FUNC_2, PH6); /* RX: H; mux 3; func 2; PH7 */
+		break;
+	}
+#elif defined(__ADSPBF52x__)
+	switch (CONFIG_UART_CONSOLE) {
+	case 0:
+		serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK,
+		PORT_x_MUX_2_FUNC_3, PG7); /* TX: G; mux 2; func 3; PG7 */
+		serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK,
+		PORT_x_MUX_2_FUNC_3, PG8); /* RX: G; mux 2; func 3; PG8 */
+		break;
+	case 1:
+		serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK,
+		PORT_x_MUX_5_FUNC_3, PF14); /* TX: F; mux 5; func 3; PF14 */
+		serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK,
+		PORT_x_MUX_5_FUNC_3, PF15); /* RX: F; mux 5; func 3; PF15 */
+		break;
+	}
+#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
+	const uint16_t func[] = { PFDE, PFTE, };
+	bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~func[CONFIG_UART_CONSOLE]);
+	bfin_write_PORTF_FER(bfin_read_PORTF_FER() |
+			(1 << P_IDENT(P_UART(RX))) |
+			(1 << P_IDENT(P_UART(TX))));
+#elif defined(__ADSPBF54x__)
+	switch (CONFIG_UART_CONSOLE) {
+	case 0:
+		serial_early_do_mach_portmux('E', PORT_x_MUX_7_MASK,
+		PORT_x_MUX_7_FUNC_1, PE7); /* TX: E; mux 7; func 1; PE7 */
+		serial_early_do_mach_portmux('E', PORT_x_MUX_8_MASK,
+		PORT_x_MUX_8_FUNC_1, PE8); /* RX: E; mux 8; func 1; PE8 */
+		break;
+	case 1:
+		serial_early_do_mach_portmux('H', PORT_x_MUX_0_MASK,
+		PORT_x_MUX_0_FUNC_1, PH0); /* TX: H; mux 0; func 1; PH0 */
+		serial_early_do_mach_portmux('H', PORT_x_MUX_1_MASK,
+		PORT_x_MUX_1_FUNC_1, PH1); /* RX: H; mux 1; func 1; PH1 */
+		break;
+	case 2:
+		serial_early_do_mach_portmux('B', PORT_x_MUX_4_MASK,
+		PORT_x_MUX_4_FUNC_1, PB4); /* TX: B; mux 4; func 1; PB4 */
+		serial_early_do_mach_portmux('B', PORT_x_MUX_5_MASK,
+		PORT_x_MUX_5_FUNC_1, PB5); /* RX: B; mux 5; func 1; PB5 */
+		break;
+	case 3:
+		serial_early_do_mach_portmux('B', PORT_x_MUX_6_MASK,
+		PORT_x_MUX_6_FUNC_1, PB6); /* TX: B; mux 6; func 1; PB6 */
+		serial_early_do_mach_portmux('B', PORT_x_MUX_7_MASK,
+		PORT_x_MUX_7_FUNC_1, PB7); /* RX: B; mux 7; func 1; PB7 */
+		break;
+	}
+#elif defined(__ADSPBF561__)
+	/* UART pins could be GPIO, but they aren't pin muxed.  */
+#else
+# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED)
+#  error "missing portmux logic for UART"
+# endif
+#endif
+	SSYNC();
+}
+
+__attribute__((always_inline))
+static inline uint32_t uart_sclk(void)
+{
+#if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL)
+	/* We cannot use get_sclk() early on as it uses
+	 * caches in external memory
+	 */
+	return CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV;
+#else
+	return get_sclk();
+#endif
+}
+
+__attribute__((always_inline))
+static inline int uart_init(uint32_t uart_base)
+{
+	/* always enable UART -- avoids anomalies 05000309 and 05000350 */
+	bfin_write(&pUART->gctl, UCEN);
+
+	/* Set LCR to Word Lengh 8-bit word select */
+	bfin_write(&pUART->lcr, WLS_8);
+
+	SSYNC();
+
+	return 0;
+}
+
+__attribute__((always_inline))
+static inline int serial_early_init(uint32_t uart_base)
+{
+	/* handle portmux crap on different Blackfins */
+	serial_do_portmux();
+
+	return uart_init(uart_base);
+}
+
+__attribute__((always_inline))
+static inline int serial_early_uninit(uint32_t uart_base)
+{
+	/* disable the UART by clearing UCEN */
+	bfin_write(&pUART->gctl, 0);
+
+	return 0;
+}
+
+__attribute__((always_inline))
+static inline int serial_early_enabled(uint32_t uart_base)
+{
+	return bfin_read(&pUART->gctl) & UCEN;
+}
+
+__attribute__((always_inline))
+static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
+{
+	/* Translate from baud into divisor in terms of SCLK.  The
+	 * weird multiplication is to make sure we over sample just
+	 * a little rather than under sample the incoming signals.
+	 */
+	uint16_t divisor = (uart_sclk() + (baud * 8)) / (baud * 16) -
+			ANOMALY_05000230;
+
+	/* Set DLAB in LCR to Access DLL and DLH */
+	ACCESS_LATCH();
+	SSYNC();
+
+	/* Program the divisor to get the baud rate we want */
+	bfin_write(&pUART->dll, LOB(divisor));
+	bfin_write(&pUART->dlh, HIB(divisor));
+	SSYNC();
+
+	/* Clear DLAB in LCR to Access THR RBR IER */
+	ACCESS_PORT_IER();
+	SSYNC();
+}
+
+__attribute__((always_inline))
+static inline void serial_early_put_div(uint16_t divisor)
+{
+	uint32_t uart_base = UART_BASE;
+
+	/* Set DLAB in LCR to Access DLL and DLH */
+	ACCESS_LATCH();
+	SSYNC();
+
+	/* Program the divisor to get the baud rate we want */
+	bfin_write(&pUART->dll, LOB(divisor));
+	bfin_write(&pUART->dlh, HIB(divisor));
+	SSYNC();
+
+	/* Clear DLAB in LCR to Access THR RBR IER */
+	ACCESS_PORT_IER();
+	SSYNC();
+}
+
+__attribute__((always_inline))
+static inline uint16_t serial_early_get_div(void)
+{
+	uint32_t uart_base = UART_BASE;
+
+	/* Set DLAB in LCR to Access DLL and DLH */
+	ACCESS_LATCH();
+	SSYNC();
+
+	uint8_t dll = bfin_read(&pUART->dll);
+	uint8_t dlh = bfin_read(&pUART->dlh);
+	uint16_t divisor = (dlh << 8) | dll;
+
+	/* Clear DLAB in LCR to Access THR RBR IER */
+	ACCESS_PORT_IER();
+	SSYNC();
+
+	return divisor;
+}
+
+#endif
+
+#endif
diff --git a/arch/blackfin/cpu/serial4.h b/arch/blackfin/cpu/serial4.h
new file mode 100644
index 0000000000..887845c186
--- /dev/null
+++ b/arch/blackfin/cpu/serial4.h
@@ -0,0 +1,161 @@
+/*
+ * serial.h - common serial defines for early debug and serial driver.
+ *            any functions defined here must be always_inline since
+ *            initcode cannot have function calls.
+ *
+ * Copyright (c) 2004-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_CPU_SERIAL4_H__
+#define __BFIN_CPU_SERIAL4_H__
+
+#include <asm/mach-common/bits/uart4.h>
+
+#ifndef __ASSEMBLY__
+
+#define MMR_UART(n) _PASTE_UART(n, UART, REVID)
+#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE)
+
+struct bfin_mmr_serial {
+	u32 revid;
+	u32 control;
+	u32 status;
+	u32 scr;
+	u32 clock;
+	u32 emask;
+	u32 emaskst;
+	u32 emaskcl;
+	u32 rbr;
+	u32 thr;
+	u32 taip;
+	u32 tsr;
+	u32 rsr;
+	u32 txdiv_cnt;
+	u32 rxdiv_cnt;
+};
+#define uart_lsr_t uint32_t
+#define _lsr_read(p)     bfin_read(&p->status)
+#define _lsr_write(p, v) bfin_write(&p->status, v)
+
+__attribute__((always_inline))
+static inline void serial_early_do_mach_portmux(char port, int mux_mask,
+	int mux_func, int port_pin)
+{
+	switch (port) {
+	case 'D':
+		bfin_write_PORTD_MUX((bfin_read_PORTD_MUX() &
+			~mux_mask) | mux_func);
+		bfin_write_PORTD_FER_SET(port_pin);
+		break;
+	case 'G':
+		bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() &
+			~mux_mask) | mux_func);
+		bfin_write_PORTG_FER_SET(port_pin);
+		break;
+	}
+}
+
+__attribute__((always_inline))
+static inline void serial_early_do_portmux(void)
+{
+#if defined(__ADSPBF60x__)
+	switch (CONFIG_UART_CONSOLE) {
+	case 0:
+		serial_early_do_mach_portmux('D', PORT_x_MUX_7_MASK,
+		PORT_x_MUX_7_FUNC_2, PD7); /* TX: D; mux 7; func 2; PD7 */
+		serial_early_do_mach_portmux('D', PORT_x_MUX_8_MASK,
+		PORT_x_MUX_8_FUNC_2, PD8); /* RX: D; mux 8; func 2; PD8 */
+		break;
+	case 1:
+		serial_early_do_mach_portmux('G', PORT_x_MUX_15_MASK,
+		PORT_x_MUX_15_FUNC_1, PG15); /* TX: G; mux 15; func 1; PG15 */
+		serial_early_do_mach_portmux('G', PORT_x_MUX_14_MASK,
+		PORT_x_MUX_14_FUNC_1, PG14); /* RX: G; mux 14; func 1; PG14 */
+		break;
+	}
+#else
+# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED)
+#  error "missing portmux logic for UART"
+# endif
+#endif
+	SSYNC();
+}
+
+__attribute__((always_inline))
+static inline uint32_t uart_sclk(void)
+{
+#if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL)
+	/* We cannot use get_sclk() early on as it uses caches in
+	 * external memory
+	 */
+	return CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV /
+		CONFIG_SCLK0_DIV;
+#else
+	return get_sclk0();
+#endif
+}
+
+__attribute__((always_inline))
+static inline int uart_init(uint32_t uart_base)
+{
+	/* always enable UART to 8-bit mode */
+	bfin_write(&pUART->control, UEN | UMOD_UART | WLS_8);
+
+	SSYNC();
+
+	return 0;
+}
+
+__attribute__((always_inline))
+static inline int serial_early_init(uint32_t uart_base)
+{
+	/* handle portmux crap on different Blackfins */
+	serial_do_portmux();
+
+	return uart_init(uart_base);
+}
+
+__attribute__((always_inline))
+static inline int serial_early_uninit(uint32_t uart_base)
+{
+	/* disable the UART by clearing UEN */
+	bfin_write(&pUART->control, 0);
+
+	return 0;
+}
+
+__attribute__((always_inline))
+static inline int serial_early_enabled(uint32_t uart_base)
+{
+	return bfin_read(&pUART->control) & UEN;
+}
+
+__attribute__((always_inline))
+static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
+{
+	uint32_t divisor = uart_sclk() / (baud * 16);
+
+	/* Program the divisor to get the baud rate we want */
+	bfin_write(&pUART->clock, divisor);
+	SSYNC();
+}
+
+__attribute__((always_inline))
+static inline void serial_early_put_div(uint32_t divisor)
+{
+	uint32_t uart_base = UART_BASE;
+	bfin_write(&pUART->clock, divisor);
+}
+
+__attribute__((always_inline))
+static inline uint32_t serial_early_get_div(void)
+{
+	uint32_t uart_base = UART_BASE;
+	return bfin_read(&pUART->clock);
+}
+
+#endif
+
+#endif
diff --git a/arch/blackfin/cpu/start.S b/arch/blackfin/cpu/start.S
index 90b4d1ae94..7155fc858b 100644
--- a/arch/blackfin/cpu/start.S
+++ b/arch/blackfin/cpu/start.S
@@ -65,6 +65,7 @@ ENTRY(_start)
 	p5.h = HI(COREMMR_BASE);
 
 #ifdef CONFIG_HW_WATCHDOG
+#ifndef __ADSPBF60x__
 # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_START
 #  define CONFIG_HW_WATCHDOG_TIMEOUT_START 5000
 # endif
@@ -78,6 +79,7 @@ ENTRY(_start)
 	/* fire up the watchdog - R0.L above needs to be 0x0000 */
 	W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r0;
 #endif
+#endif
 
 	/* Turn on the serial for debugging the init process */
 	serial_early_init