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authorKumar Gala <galak@kernel.crashing.org>2011-10-03 08:37:57 -0500
committerKumar Gala <galak@kernel.crashing.org>2011-10-03 08:52:15 -0500
commit2b3a1cdd9ed14441ae91845851aaf91adddbafc0 (patch)
treedd409bc5656f74b3e9bc69054219eb076ada6d08 /arch/powerpc/include
parent5ace2992b5a89afaa3144af4a076480651f4ddfa (diff)
powerpc/mpc8548: Add workaround for erratum NMG_LBC103
The erratum NMG_LBC103 is LBIU3 in MPC8548 errata document. Any local bus transaction may fail during LBIU resynchronization process when the clock divider [CLKDIV] is changing. Ensure there is no transaction on the local bus for at least 100 microseconds after changing clock divider LCRR[CLKDIV]. Refer to the erratum LBIU3 of mpc8548. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index a0a12b23e7..fc78c58d03 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -63,6 +63,7 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
+#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
#elif defined(CONFIG_MPC8555)
#define CONFIG_MAX_CPUS 1