diff options
| author | Tom Rini <trini@konsulko.com> | 2019-09-02 23:21:44 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-09-02 23:21:44 -0400 |
| commit | 83a5df42614c566c3c642871f683e66a53d228ae (patch) | |
| tree | ea53c8fd1dd9bf65bc1d29dd9a0957d060dc1917 /arch/riscv/cpu/ax25/cache.c | |
| parent | d22c8be964a870f59d2fdab6c67cefa0c4799364 (diff) | |
| parent | 61ce84b2cf1a6672c8e402ce8174554b25629692 (diff) | |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Skip unavailable hart in the get_count().
- fu540 set serial env from otp.
- fu540 add mmc0 as a boot target device.
- Update fix_rela_dyn and add absolute reloc addend.
- Andestech PLIC driver will skip unavailable hart.
- Support Andestech V5L2 cache driver.
Diffstat (limited to 'arch/riscv/cpu/ax25/cache.c')
| -rw-r--r-- | arch/riscv/cpu/ax25/cache.c | 39 |
1 files changed, 30 insertions, 9 deletions
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index cd95058d9d..41de30cc02 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -5,17 +5,24 @@ */ #include <common.h> +#include <dm.h> +#include <dm/uclass-internal.h> +#include <cache.h> +#include <asm/csr.h> + +#ifdef CONFIG_RISCV_NDS_CACHE +/* mcctlcommand */ +#define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc + +/* D-cache operation */ +#define CCTL_L1D_WBINVAL_ALL 6 +#endif void flush_dcache_all(void) { - /* - * Andes' AX25 does not have a coherence agent. U-Boot must use data - * cache flush and invalidate functions to keep data in the system - * coherent. - * The implementation of the fence instruction in the AX25 flushes the - * data cache and is used for this purpose. - */ - asm volatile ("fence" ::: "memory"); +#ifdef CONFIG_RISCV_NDS_CACHE + csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); +#endif } void flush_dcache_range(unsigned long start, unsigned long end) @@ -59,11 +66,18 @@ void dcache_enable(void) { #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE + struct udevice *dev = NULL; + asm volatile ( "csrr t1, mcache_ctl\n\t" "ori t0, t1, 0x2\n\t" "csrw mcache_ctl, t0\n\t" ); + + uclass_find_first_device(UCLASS_CACHE, &dev); + + if (dev) + cache_enable(dev); #endif #endif } @@ -72,12 +86,19 @@ void dcache_disable(void) { #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE + struct udevice *dev = NULL; + + csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); asm volatile ( - "fence\n\t" "csrr t1, mcache_ctl\n\t" "andi t0, t1, ~0x2\n\t" "csrw mcache_ctl, t0\n\t" ); + + uclass_find_first_device(UCLASS_CACHE, &dev); + + if (dev) + cache_disable(dev); #endif #endif } |