diff options
| author | Rick Chen <rick@andestech.com> | 2019-11-14 13:52:21 +0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2019-12-10 08:23:10 +0800 |
| commit | ca06444aac2c643db3a3f2eb37afc60fae15177e (patch) | |
| tree | b8b80458bbd6e047b1f850c8a4353180bcba74cd /arch/riscv/cpu | |
| parent | 31fbf6032ddd9b968b1ca102f71fe7f42fabf58a (diff) | |
riscv: ax25: add SPL support
The U-Boot SPL will boot in M mode and load the FIT image which
include OpenSBI and U-Boot proper images. After loading progress,
it will jump to OpenSBI first and then U-Boot proper which will
run in S mode.
Also remove V5L2_CACHE due to U-Boot SPL code size consideration.
Without this concern, it can be enable manually for performance.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
Diffstat (limited to 'arch/riscv/cpu')
| -rw-r--r-- | arch/riscv/cpu/ax25/Kconfig | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index d411a79c21..8d8d71dcbf 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -6,7 +6,9 @@ config RISCV_NDS imply RISCV_TIMER imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE) imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE) - imply V5L2_CACHE + imply SPL_CPU_SUPPORT + imply SPL_OPENSBI + imply SPL_LOAD_FIT help Run U-Boot on AndeStar V5 platforms and use some specific features which are provided by Andes Technology AndeStar V5 families. |