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| author | Tom Rini <trini@konsulko.com> | 2019-09-02 23:21:44 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-09-02 23:21:44 -0400 |
| commit | 83a5df42614c566c3c642871f683e66a53d228ae (patch) | |
| tree | ea53c8fd1dd9bf65bc1d29dd9a0957d060dc1917 /arch/riscv/dts/ae350_64.dts | |
| parent | d22c8be964a870f59d2fdab6c67cefa0c4799364 (diff) | |
| parent | 61ce84b2cf1a6672c8e402ce8174554b25629692 (diff) | |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Skip unavailable hart in the get_count().
- fu540 set serial env from otp.
- fu540 add mmc0 as a boot target device.
- Update fix_rela_dyn and add absolute reloc addend.
- Andestech PLIC driver will skip unavailable hart.
- Support Andestech V5L2 cache driver.
Diffstat (limited to 'arch/riscv/dts/ae350_64.dts')
| -rw-r--r-- | arch/riscv/dts/ae350_64.dts | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index 705491a8e4..d8f00f8d3a 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -62,13 +62,18 @@ compatible = "riscv,cpu-intc"; }; }; + }; - L2: l2-cache@e0500000 { - compatible = "cache"; - cache-level = <2>; - cache-size = <0x40000>; - reg = <0x0 0xe0500000 0x0 0x40000>; - }; + L2: l2-cache@e0500000 { + compatible = "v5l2cache"; + cache-level = <2>; + cache-size = <0x40000>; + reg = <0x0 0xe0500000 0x0 0x40000>; + andes,inst-prefetch = <3>; + andes,data-prefetch = <3>; + /* The value format is <XRAMOCTL XRAMICTL> */ + andes,tag-ram-ctl = <0 0>; + andes,data-ram-ctl = <0 0>; }; memory@0 { |