diff options
| author | Tom Rini <trini@konsulko.com> | 2016-07-12 08:15:17 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-07-12 08:15:17 -0400 |
| commit | b8e599746cac1833328bc3a8e37eeefe346baf90 (patch) | |
| tree | ec49cc9ac3c8638fe11774e945cf0bcc4e87c1f4 /arch/x86/include/asm/arch-baytrail | |
| parent | bff97dde8c8cf6fd5f04bb26fca83f61eadc1741 (diff) | |
| parent | 9532fe3b40ddf66ef976dee3d5cf1d8b3396bf4d (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-x86
Diffstat (limited to 'arch/x86/include/asm/arch-baytrail')
| -rw-r--r-- | arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl | 15 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-baytrail/acpi/lpc.asl | 19 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-baytrail/acpi/platform.asl | 3 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-baytrail/global_nvs.h | 21 |
4 files changed, 47 insertions, 11 deletions
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl b/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl new file mode 100644 index 0000000000..a28d4dfade --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/acpi/global_nvs.h> + +OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE) +Field(GNVS, ByteAcc, NoLock, Preserve) +{ + Offset (0x00), + PCNT, 8, /* processor count */ + IURE, 8, /* internal UART enabled */ +} diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl index 22f0d68f4d..fe34d3271c 100644 --- a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl +++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl @@ -119,17 +119,14 @@ Device (LPCB) Method(_STA, 0, Serialized) { - /* - * TODO: - * - * Need to hide the internal UART depending on whether - * internal UART is enabled or not so that external - * SuperIO UART can be exposed to system. - */ - Store(1, UI3E) - Store(1, UI4E) - Store(1, C1EN) - Return (STA_VISIBLE) + If (LEqual(IURE, 1)) { + Store(1, UI3E) + Store(1, UI4E) + Store(1, C1EN) + Return (STA_VISIBLE) + } Else { + Return (STA_MISSING) + } } diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl index 6bc82ecfe1..a80d2c0e51 100644 --- a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl +++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl @@ -22,6 +22,9 @@ Method(_WAK, 1) Return (Package() {0, 0}) } +/* ACPI global NVS */ +#include "global_nvs.asl" + /* TODO: add CPU ASL support */ Scope (\_SB) diff --git a/arch/x86/include/asm/arch-baytrail/global_nvs.h b/arch/x86/include/asm/arch-baytrail/global_nvs.h new file mode 100644 index 0000000000..56e362633f --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/global_nvs.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _GLOBAL_NVS_H_ +#define _GLOBAL_NVS_H_ + +struct __packed acpi_global_nvs { + u8 pcnt; /* processor count */ + u8 iuart_en; /* internal UART enabled */ + + /* + * Add padding so sizeof(struct acpi_global_nvs) == 0x100. + * This must match the size defined in the global_nvs.asl. + */ + u8 rsvd[254]; +}; + +#endif /* _GLOBAL_NVS_H_ */ |