x86: Add a generic Intel pinctrl driver

Recent Intel SoCs share a pinctrl mechanism with many common elements. Add
an implementation of this core functionality, allowing SoC-specific
drivers to avoid adding common code.

As well as a pinctrl driver this provides a GPIO driver based on the same
code.

Once other SoCs use this driver we may consider moving more properties to
the device tree (e.g. the community info and pad definitions).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

2 files changed, 679 insertions, 0 deletions

diff --git a/arch/x86/include/asm/intel_pinctrl.h b/arch/x86/include/asm/intel_pinctrl.h
new file mode 100644
index 0000000000..72fd9246cb
--- /dev/null
+++ b/arch/x86/include/asm/intel_pinctrl.h
@@ -0,0 +1,306 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017 Intel Corporation.
+ * Copyright 2019 Google LLC
+ *
+ * Modified from coreboot gpio.h
+ */
+
+#ifndef __ASM_INTEL_PINCTRL_H
+#define __ASM_INTEL_PINCTRL_H
+
+#include <dm/pinctrl.h>
+
+/**
+ * struct pad_config - config for a pad
+ * @pad: offset of pad within community
+ * @pad_config: Pad config data corresponding to DW0, DW1, etc.
+ */
+struct pad_config {
+	int pad;
+	u32 pad_config[4];
+};
+
+#include <asm/arch/gpio.h>
+
+/* GPIO community IOSF sideband clock gating */
+#define MISCCFG_GPSIDEDPCGEN	BIT(5)
+/* GPIO community RCOMP clock gating */
+#define MISCCFG_GPRCOMPCDLCGEN	BIT(4)
+/* GPIO community RTC clock gating */
+#define MISCCFG_GPRTCDLCGEN	BIT(3)
+/* GFX controller clock gating */
+#define MISCCFG_GSXSLCGEN	BIT(2)
+/* GPIO community partition clock gating */
+#define MISCCFG_GPDPCGEN	BIT(1)
+/* GPIO community local clock gating */
+#define MISCCFG_GPDLCGEN	BIT(0)
+/* Enable GPIO community power management configuration */
+#define MISCCFG_ENABLE_GPIO_PM_CONFIG (MISCCFG_GPSIDEDPCGEN | \
+	MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
+	| MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
+
+/*
+ * GPIO numbers may not be contiguous and instead will have a different
+ * starting pin number for each pad group.
+ */
+#define INTEL_GPP_BASE(first_of_community, start_of_group, end_of_group,\
+			group_pad_base)					\
+	{								\
+		.first_pad = (start_of_group) - (first_of_community),	\
+		.size = (end_of_group) - (start_of_group) + 1,		\
+		.acpi_pad_base = (group_pad_base),			\
+	}
+
+/*
+ * A pad base of -1 indicates that this group uses contiguous numbering
+ * and a pad base should not be used for this group.
+ */
+#define PAD_BASE_NONE	-1
+
+/* The common/default group numbering is contiguous */
+#define INTEL_GPP(first_of_community, start_of_group, end_of_group)	\
+	INTEL_GPP_BASE(first_of_community, start_of_group, end_of_group,\
+		       PAD_BASE_NONE)
+
+/**
+ * struct reset_mapping - logical to actual value for PADRSTCFG in DW0
+ *
+ * Note that the values are expected to be within the field placement of the
+ * register itself. i.e. if the reset field is at 31:30 then the values within
+ * logical and chipset should occupy 31:30.
+ */
+struct reset_mapping {
+	u32 logical;
+	u32 chipset;
+};
+
+/**
+ * struct pad_group - describes the groups within each community
+ *
+ * @first_pad: offset of first pad of the group relative to the community
+ * @size: size of the group
+ * @acpi_pad_base: starting pin number for the pads in this group when they are
+ *	used in ACPI.  This is only needed if the pins are not contiguous across
+ *	groups. Most groups will have this set to PAD_BASE_NONE and use
+ *	contiguous numbering for ACPI.
+ */
+struct pad_group {
+	int first_pad;
+	uint size;
+	int acpi_pad_base;
+};
+
+/**
+ * struct pad_community - community of pads
+ *
+ * This describes a community, or each group within a community when multiple
+ * groups exist inside a community
+ *
+ * @name: Community name
+ * @acpi_path: ACPI path
+ * @num_gpi_regs: number of gpi registers in community
+ * @max_pads_per_group: number of pads in each group; number of pads bit-mapped
+ *	in each GPI status/en and Host Own Reg
+ * @first_pad: first pad in community
+ * @last_pad: last pad in community
+ * @host_own_reg_0: offset to Host Ownership Reg 0
+ * @gpi_int_sts_reg_0: offset to GPI Int STS Reg 0
+ * @gpi_int_en_reg_0: offset to GPI Int Enable Reg 0
+ * @gpi_smi_sts_reg_0: offset to GPI SMI STS Reg 0
+ * @gpi_smi_en_reg_0: offset to GPI SMI EN Reg 0
+ * @pad_cfg_base: offset to first PAD_GFG_DW0 Reg
+ * @gpi_status_offset: specifies offset in struct gpi_status
+ * @port: PCR Port ID
+ * @reset_map: PADRSTCFG logical to chipset mapping
+ * @num_reset_vals: number of values in @reset_map
+ * @groups; list of groups for this community
+ * @num_groups: number of groups
+ */
+struct pad_community {
+	const char *name;
+	const char *acpi_path;
+	size_t num_gpi_regs;
+	size_t max_pads_per_group;
+	uint first_pad;
+	uint last_pad;
+	u16 host_own_reg_0;
+	u16 gpi_int_sts_reg_0;
+	u16 gpi_int_en_reg_0;
+	u16 gpi_smi_sts_reg_0;
+	u16 gpi_smi_en_reg_0;
+	u16 pad_cfg_base;
+	u8 gpi_status_offset;
+	u8 port;
+	const struct reset_mapping *reset_map;
+	size_t num_reset_vals;
+	const struct pad_group *groups;
+	size_t num_groups;
+};
+
+/**
+ * struct intel_pinctrl_priv - private data for each pinctrl device
+ *
+ * @comm: Pad community for this device
+ * @num_cfgs: Number of configuration words for each pad
+ * @itss: ITSS device (for interrupt handling)
+ * @itss_pol_cfg: Use to program Interrupt Polarity Control (IPCx) register
+ *	Each bit represents IRQx Active High Polarity Disable configuration:
+ *	when set to 1, the interrupt polarity associated with IRQx is inverted
+ *	to appear as Active Low to IOAPIC and vice versa
+ */
+struct intel_pinctrl_priv {
+	const struct pad_community *comm;
+	int num_cfgs;
+	struct udevice *itss;
+	bool itss_pol_cfg;
+};
+
+/* Exported common operations for the pinctrl driver */
+extern const struct pinctrl_ops intel_pinctrl_ops;
+
+/* Exported common probe function for the pinctrl driver */
+int intel_pinctrl_probe(struct udevice *dev);
+
+/**
+ * intel_pinctrl_ofdata_to_platdata() - Handle common platdata setup
+ *
+ * @dev: Pinctrl device
+ * @comm: Pad community for this device
+ * @num_cfgs: Number of configuration words for each pad
+ * @return 0 if OK, -EDOM if @comm is NULL, other -ve value on other error
+ */
+int intel_pinctrl_ofdata_to_platdata(struct udevice *dev,
+				     const struct pad_community *comm,
+				     int num_cfgs);
+
+/**
+ * pinctrl_route_gpe() - set GPIO groups for the general-purpose-event blocks
+ *
+ * The values from PMC register GPE_CFG are passed which is then mapped to
+ * proper groups for MISCCFG. This basically sets the MISCCFG register bits:
+ *  dw0 = gpe0_route[11:8]. This is ACPI GPE0b.
+ *  dw1 = gpe0_route[15:12]. This is ACPI GPE0c.
+ *  dw2 = gpe0_route[19:16]. This is ACPI GPE0d.
+ *
+ * @dev: ITSS device
+ * @gpe0b: Value for GPE0B
+ * @gpe0c: Value for GPE0C
+ * @gpe0d: Value for GPE0D
+ * @return 0 if OK, -ve on error
+ */
+int pinctrl_route_gpe(struct udevice *dev, uint gpe0b, uint gpe0c, uint gpe0d);
+
+/**
+ * pinctrl_config_pads() - Configure a list of pads
+ *
+ * Configures multiple pads using the provided data from the device tree.
+ *
+ * @dev: pinctrl device (any will do)
+ * @pads: Pad data, consisting of a pad number followed by num_cfgs entries
+ *	containing the data for that pad (num_cfgs is set by the pinctrl device)
+ * @pads_count: Number of pads to configure
+ * @return 0 if OK, -ve on error
+ */
+int pinctrl_config_pads(struct udevice *dev, u32 *pads, int pads_count);
+
+/**
+ * pinctrl_gpi_clear_int_cfg() - Set up the interrupts for use
+ *
+ * This enables the interrupt inputs and clears the status register bits
+ *
+ * @return 0 if OK, -ve on error
+ */
+int pinctrl_gpi_clear_int_cfg(void);
+
+/**
+ * pinctrl_config_pads_for_node() - Configure pads
+ *
+ * Set up the pads using the data in a given node
+ *
+ * @dev: pinctrl device (any will do)
+ * @node: Node containing the 'pads' property with the data in it
+ * @return 0 if OK, -ve on error
+ */
+int pinctrl_config_pads_for_node(struct udevice *dev, ofnode node);
+
+/**
+ * pinctrl_read_pads() - Read pad data from a node
+ *
+ * @dev: pinctrl device (any will do, it is just used to get config)
+ * @node: Node to read pad data from
+ * @prop: Property name to use (e.g. "pads")
+ * @padsp: Returns a pointer to an allocated array of pad data, in the format:
+ *	<pad>
+ *	<pad_config0>
+ *	<pad_config1>
+ *	...
+ *
+ *	The number of pad config values is set by the pinctrl controller.
+ *	The caller must free this array.
+ * @pad_countp: Returns the number of pads read
+ * @ereturn 0 if OK, -ve on error
+ */
+int pinctrl_read_pads(struct udevice *dev, ofnode node, const char *prop,
+		      u32 **padsp, int *pad_countp);
+
+/**
+ * pinctrl_count_pads() - Count the number of pads in a pad array
+ *
+ * This used used with of-platdata where the array may be smaller than its
+ * maximum size. This function searches for the last pad in the array by finding
+ * the first 'zero' record
+ *
+ * This works out the number of records in the array. Each record has one word
+ * for the pad and num_cfgs words for the config.
+ *
+ * @dev: pinctrl device (any will do)
+ * @pads: Array of pad data
+ * @size: Size of pad data in bytes
+ * @return number of pads represented by the data
+ */
+int pinctrl_count_pads(struct udevice *dev, u32 *pads, int size);
+
+/**
+ * intel_pinctrl_get_config_reg_addr() - Get address of the pin config registers
+ *
+ * @dev: Pinctrl device
+ * @offset: GPIO offset within this device
+ * @return register offset within the GPIO p2sb region
+ */
+u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset);
+
+/**
+ * intel_pinctrl_get_config_reg() - Get the value of a GPIO register
+ *
+ * @dev: Pinctrl device
+ * @offset: GPIO offset within this device
+ * @return register value within the GPIO p2sb region
+ */
+u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset);
+
+/**
+ * intel_pinctrl_get_pad() - Get pad information for a pad
+ *
+ * This is used by the GPIO controller to find the pinctrl used by a pad.
+ *
+ * @pad: Pad to check
+ * @devp: Returns pinctrl device containing that pad
+ * @offsetp: Returns offset of pad within that pinctrl device
+ */
+int intel_pinctrl_get_pad(uint pad, struct udevice **devp, uint *offsetp);
+
+/**
+ * intel_pinctrl_get_acpi_pin() - Get the ACPI pin for a pinctrl pin
+ *
+ * Maps a pinctrl pin (in terms of its offset within the pins controlled by that
+ * pinctrl) to an ACPI GPIO pin-table entry.
+ *
+ * @dev: Pinctrl device to check
+ * @offset: Offset of pin within that device (0 = first)
+ * @return associated ACPI GPIO pin-table entry, or standard pin number if the
+ *	ACPI pad base is not set
+ */
+int intel_pinctrl_get_acpi_pin(struct udevice *dev, uint offset);
+
+#endif
diff --git a/arch/x86/include/asm/intel_pinctrl_defs.h b/arch/x86/include/asm/intel_pinctrl_defs.h
new file mode 100644
index 0000000000..6da06bb52b
--- /dev/null
+++ b/arch/x86/include/asm/intel_pinctrl_defs.h
@@ -0,0 +1,373 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corp.
+ * Copyright 2019 Google LLC
+ *
+ * Modified from coreboot gpio_defs.h
+ */
+
+#ifndef _ASM_INTEL_PINCTRL_DEFS_H_
+#define _ASM_INTEL_PINCTRL_DEFS_H_
+
+/* This file is included by device trees, so avoid BIT() macros */
+
+#define PAD_CFG0_TX_STATE_BIT		0
+#define PAD_CFG0_TX_STATE		(1 << PAD_CFG0_TX_STATE_BIT)
+#define PAD_CFG0_RX_STATE_BIT		1
+#define PAD_CFG0_RX_STATE		(1 << PAD_CFG0_RX_STATE_BIT)
+#define PAD_CFG0_TX_DISABLE		(1 << 8)
+#define PAD_CFG0_RX_DISABLE		(1 << 9)
+
+#define PAD_CFG0_MODE_SHIFT		10
+#define PAD_CFG0_MODE_MASK		(7 << PAD_CFG0_MODE_SHIFT)
+#define  PAD_CFG0_MODE_GPIO		(0 << PAD_CFG0_MODE_SHIFT)
+#define  PAD_CFG0_MODE_NF1		(1 << PAD_CFG0_MODE_SHIFT)
+#define  PAD_CFG0_MODE_NF2		(2 << PAD_CFG0_MODE_SHIFT)
+#define  PAD_CFG0_MODE_NF3		(3 << PAD_CFG0_MODE_SHIFT)
+#define  PAD_CFG0_MODE_NF4		(4 << PAD_CFG0_MODE_SHIFT)
+#define  PAD_CFG0_MODE_NF5		(5 << PAD_CFG0_MODE_SHIFT)
+#define  PAD_CFG0_MODE_NF6		(6 << PAD_CFG0_MODE_SHIFT)
+
+#define PAD_CFG0_ROUTE_MASK		(0xf << 17)
+#define  PAD_CFG0_ROUTE_NMI		(1 << 17)
+#define  PAD_CFG0_ROUTE_SMI		(1 << 18)
+#define  PAD_CFG0_ROUTE_SCI		(1 << 19)
+#define  PAD_CFG0_ROUTE_IOAPIC		(1 << 20)
+#define PAD_CFG0_RXTENCFG_MASK		(3 << 21)
+#define PAD_CFG0_RXINV_MASK		(1 << 23)
+#define  PAD_CFG0_RX_POL_INVERT		(1 << 23)
+#define  PAD_CFG0_RX_POL_NONE		(0 << 23)
+#define  PAD_CFG0_PREGFRXSEL		(1 << 24)
+#define PAD_CFG0_TRIG_MASK		(3 << 25)
+#define  PAD_CFG0_TRIG_LEVEL		(0 << 25)
+#define  PAD_CFG0_TRIG_EDGE_SINGLE	(1 << 25) /* controlled by RX_INVERT*/
+#define  PAD_CFG0_TRIG_OFF		(2 << 25)
+#define  PAD_CFG0_TRIG_EDGE_BOTH	(3 << 25)
+#define PAD_CFG0_RXRAW1_MASK		(1 << 28)
+#define PAD_CFG0_RXPADSTSEL_MASK	(1 << 29)
+#define PAD_CFG0_RESET_MASK		(3 << 30)
+#define  PAD_CFG0_LOGICAL_RESET_PWROK	(0U << 30)
+#define  PAD_CFG0_LOGICAL_RESET_DEEP	(1U << 30)
+#define  PAD_CFG0_LOGICAL_RESET_PLTRST	(2U << 30)
+#define  PAD_CFG0_LOGICAL_RESET_RSMRST	(3U << 30)
+
+/*
+ * Use the fourth bit in IntSel field to indicate gpio ownership. This field is
+ * RO and hence not used during gpio configuration.
+ */
+#define PAD_CFG1_GPIO_DRIVER		(0x1 << 4)
+#define PAD_CFG1_IRQ_MASK		(0xff << 0)
+#define PAD_CFG1_IOSTERM_MASK		(0x3 << 8)
+#define PAD_CFG1_IOSTERM_SAME		(0x0 << 8)
+#define PAD_CFG1_IOSTERM_DISPUPD	(0x1 << 8)
+#define PAD_CFG1_IOSTERM_ENPD		(0x2 << 8)
+#define PAD_CFG1_IOSTERM_ENPU		(0x3 << 8)
+#define PAD_CFG1_PULL_MASK		(0xf << 10)
+#define  PAD_CFG1_PULL_NONE		(0x0 << 10)
+#define  PAD_CFG1_PULL_DN_5K		(0x2 << 10)
+#define  PAD_CFG1_PULL_DN_20K		(0x4 << 10)
+#define  PAD_CFG1_PULL_UP_1K		(0x9 << 10)
+#define  PAD_CFG1_PULL_UP_5K		(0xa << 10)
+#define  PAD_CFG1_PULL_UP_2K		(0xb << 10)
+#define  PAD_CFG1_PULL_UP_20K		(0xc << 10)
+#define  PAD_CFG1_PULL_UP_667		(0xd << 10)
+#define  PAD_CFG1_PULL_NATIVE		(0xf << 10)
+
+/* Tx enabled driving last value driven, Rx enabled */
+#define PAD_CFG1_IOSSTATE_TX_LAST_RXE	(0x0 << 14)
+/*
+ * Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller
+ * internally
+ */
+#define PAD_CFG1_IOSSTATE_TX0_RX_DCR_X0	(0x1 << 14)
+/*
+ * Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller
+ * internally
+ */
+#define PAD_CFG1_IOSSTATE_TX0_RX_DCR_X1	(0x2 << 14)
+/*
+ * Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller
+ * internally
+ */
+#define PAD_CFG1_IOSSTATE_TX1_RX_DCR_X0	(0x3 << 14)
+/*
+ * Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller
+ * internally
+ */
+#define PAD_CFG1_IOSSTATE_TX1_RX_DCR_X1	(0x4 << 14)
+/* Tx enabled driving 0, Rx enabled */
+#define PAD_CFG1_IOSSTATE_TX0_RXE	(0x5 << 14)
+/* Tx enabled driving 1, Rx enabled */
+#define PAD_CFG1_IOSSTATE_TX1_RXE	(0x6 << 14)
+/* Hi-Z, Rx driving 0 back to its controller internally */
+#define PAD_CFG1_IOSSTATE_HIZCRX0	(0x7 << 14)
+/* Hi-Z, Rx driving 1 back to its controller internally */
+#define PAD_CFG1_IOSSTATE_HIZCRX1	(0x8 << 14)
+/* Tx disabled, Rx enabled */
+#define PAD_CFG1_IOSSTATE_TXD_RXE	(0x9 << 14)
+#define PAD_CFG1_IOSSTATE_IGNORE	(0xf << 14) /* Ignore Iostandby */
+/* mask to extract Iostandby bits */
+#define PAD_CFG1_IOSSTATE_MASK		(0xf << 14)
+#define PAD_CFG1_IOSSTATE_SHIFT		14 /* set Iostandby bits [17:14] */
+
+#define PAD_CFG2_DEBEN			1
+/* Debounce Duration = (2 ^ PAD_CFG2_DEBOUNCE_x_RTC) * RTC clock duration */
+#define PAD_CFG2_DEBOUNCE_8_RTC		(0x3 << 1)
+#define PAD_CFG2_DEBOUNCE_16_RTC	(0x4 << 1)
+#define PAD_CFG2_DEBOUNCE_32_RTC	(0x5 << 1)
+#define PAD_CFG2_DEBOUNCE_64_RTC	(0x6 << 1)
+#define PAD_CFG2_DEBOUNCE_128_RTC	(0x7 << 1)
+#define PAD_CFG2_DEBOUNCE_256_RTC	(0x8 << 1)
+#define PAD_CFG2_DEBOUNCE_512_RTC	(0x9 << 1)
+#define PAD_CFG2_DEBOUNCE_1K_RTC	(0xa << 1)
+#define PAD_CFG2_DEBOUNCE_2K_RTC	(0xb << 1)
+#define PAD_CFG2_DEBOUNCE_4K_RTC	(0xc << 1)
+#define PAD_CFG2_DEBOUNCE_8K_RTC	(0xd << 1)
+#define PAD_CFG2_DEBOUNCE_16K_RTC	(0xe << 1)
+#define PAD_CFG2_DEBOUNCE_32K_RTC	(0xf << 1)
+#define PAD_CFG2_DEBOUNCE_MASK		0x1f
+
+/* voltage tolerance  0=3.3V default 1=1.8V tolerant */
+#if IS_ENABLED(INTEL_PINCTRL_IOSTANDBY)
+#define PAD_CFG1_TOL_MASK		(0x1 << 25)
+#define  PAD_CFG1_TOL_1V8		(0x1 << 25)
+#endif
+
+#define PAD_FUNC(value)		PAD_CFG0_MODE_##value
+#define PAD_RESET(value)	PAD_CFG0_LOGICAL_RESET_##value
+#define PAD_PULL(value)		PAD_CFG1_PULL_##value
+
+#define PAD_IOSSTATE(value)	PAD_CFG1_IOSSTATE_##value
+#define PAD_IOSTERM(value)	PAD_CFG1_IOSTERM_##value
+
+#define PAD_IRQ_CFG(route, trig, inv) \
+				(PAD_CFG0_ROUTE_##route | \
+				PAD_CFG0_TRIG_##trig | \
+				PAD_CFG0_RX_POL_##inv)
+
+#if IS_ENABLED(INTEL_PINCTRL_DUAL_ROUTE_SUPPORT)
+#define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv)  \
+				(PAD_CFG0_ROUTE_##route1 | \
+				PAD_CFG0_ROUTE_##route2 | \
+				PAD_CFG0_TRIG_##trig | \
+				PAD_CFG0_RX_POL_##inv)
+#endif /* CONFIG_INTEL_PINCTRL_DUAL_ROUTE_SUPPORT */
+
+#define _PAD_CFG_STRUCT(__pad, __config0, __config1)	\
+		__pad(__config0) (__config1)
+
+/* Native function configuration */
+#define PAD_CFG_NF(pad, pull, rst, func) \
+	_PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
+		PAD_IOSSTATE(TX_LAST_RXE))
+
+#if IS_ENABLED(CONFIG_INTEL_GPIO_PADCFG_PADTOL)
+/*
+ * Native 1.8V tolerant pad, only applies to some pads like I2C/I2S. Not
+ * applicable to all SOCs. Refer EDS.
+ */
+#define PAD_CFG_NF_1V8(pad, pull, rst, func) \
+	_PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) |\
+		PAD_IOSSTATE(TX_LAST_RXE) | PAD_CFG1_TOL_1V8)
+#endif
+
+/* Native function configuration for standby state */
+#define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \
+	_PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
+		PAD_IOSSTATE(iosstate))
+
+/*
+ * Native function configuration for standby state, also configuring iostandby
+ * as masked
+ */
+#define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \
+	_PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
+		PAD_IOSSTATE(IGNORE))
+
+/*
+ * Native function configuration for standby state, also configuring iosstate
+ * and iosterm
+ */
+#define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \
+	_PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
+		PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
+
+/* General purpose output, no pullup/down */
+#define PAD_CFG_GPO(pad, val, rst)	\
+	_PAD_CFG_STRUCT(pad,		\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
+		PAD_PULL(NONE) | PAD_IOSSTATE(TX_LAST_RXE))
+
+/* General purpose output, with termination specified */
+#define PAD_CFG_TERM_GPO(pad, val, pull, rst)	\
+	_PAD_CFG_STRUCT(pad,		\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
+		PAD_PULL(pull) | PAD_IOSSTATE(TX_LAST_RXE))
+
+/* General purpose output, no pullup/down */
+#define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull)	\
+	_PAD_CFG_STRUCT(pad,		\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
+		PAD_PULL(pull) | PAD_IOSSTATE(TX_LAST_RXE) | \
+			PAD_CFG1_GPIO_DRIVER)
+
+/* General purpose output */
+#define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \
+	_PAD_CFG_STRUCT(pad,		\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
+		PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm))
+
+/* General purpose input */
+#define PAD_CFG_GPI(pad, pull, rst) \
+	_PAD_CFG_STRUCT(pad,		\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
+		PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE))
+
+/* General purpose input. The following macro sets the
+ * Host Software Pad Ownership to GPIO Driver mode.
+ */
+#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \
+	_PAD_CFG_STRUCT(pad,		\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
+		PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE))
+
+#define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \
+	_PAD_CFG_STRUCT(pad,		\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE |	\
+		PAD_CFG0_RX_DISABLE,					\
+		PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER |			\
+		PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
+
+#define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \
+	_PAD_CFG_STRUCT(pad,		\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE |	\
+		PAD_CFG0_RX_DISABLE, PAD_PULL(pull) |			\
+		PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
+
+/* GPIO Interrupt */
+#define PAD_CFG_GPI_INT(pad, pull, rst, trig) \
+	_PAD_CFG_STRUCT(pad,		\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE |	\
+			PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE,	\
+		PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE))
+
+/*
+ * No Connect configuration for unused pad.
+ * Both TX and RX are disabled. RX disabling is done to avoid unnecessary
+ * setting of GPI_STS.
+ */
+#define PAD_NC(pad, pull)			\
+	_PAD_CFG_STRUCT(pad,					\
+		PAD_FUNC(GPIO) | PAD_RESET(DEEP) |		\
+		PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE,	\
+		PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE))
+
+/* General purpose input, routed to APIC */
+#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \
+	_PAD_CFG_STRUCT(pad,		\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+		PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \
+		PAD_IOSSTATE(TXD_RXE))
+
+/* General purpose input, routed to APIC - with IOStandby Config*/
+#define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \
+	_PAD_CFG_STRUCT(pad,		\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+		PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \
+		PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
+
+/*
+ * The following APIC macros assume the APIC will handle the filtering
+ * on its own end. One just needs to pass an active high message into the
+ * ITSS.
+ */
+#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \
+	PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT)
+
+#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \
+	PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE)
+
+#define PAD_CFG_GPI_APIC_EDGE_LOW(pad, pull, rst) \
+	PAD_CFG_GPI_APIC(pad, pull, rst, EDGE_SINGLE, INVERT)
+
+/* General purpose input, routed to SMI */
+#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \
+	_PAD_CFG_STRUCT(pad,		\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+		PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \
+		PAD_IOSSTATE(TXD_RXE))
+
+/* General purpose input, routed to SMI */
+#define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \
+	_PAD_CFG_STRUCT(pad,		\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+		PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \
+		PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
+
+#define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \
+	PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT)
+
+#define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \
+	PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE)
+
+/* General purpose input, routed to SCI */
+#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \
+	_PAD_CFG_STRUCT(pad,		\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+		PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
+		PAD_IOSSTATE(TXD_RXE))
+
+/* General purpose input, routed to SCI */
+#define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \
+	_PAD_CFG_STRUCT(pad,		\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+		PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
+		PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
+
+#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \
+	PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT)
+
+#define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \
+	PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE)
+
+#define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \
+	_PAD_CFG_STRUCT_3(pad,		\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+		PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
+		PAD_IOSSTATE(TXD_RXE), PAD_CFG2_DEBEN | PAD_CFG2_##dur)
+
+#define PAD_CFG_GPI_SCI_LOW_DEBEN(pad, pull, rst, trig, dur) \
+	PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, INVERT, dur)
+
+#define PAD_CFG_GPI_SCI_HIGH_DEBEN(pad, pull, rst, trig, dur) \
+	PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, NONE, dur)
+
+/* General purpose input, routed to NMI */
+#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \
+	_PAD_CFG_STRUCT(pad,		\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+		PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \
+		PAD_IOSSTATE(TXD_RXE))
+
+#if IS_ENABLED(INTEL_PINCTRL_DUAL_ROUTE_SUPPORT)
+/* GPI, GPIO Driver, SCI interrupt */
+#define PAD_CFG_GPI_GPIO_DRIVER_SCI(pad, pull, rst, trig, inv)	\
+	_PAD_CFG_STRUCT(pad,		\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+			PAD_IRQ_CFG(SCI, trig, inv),	\
+		PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE))
+
+#define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \
+	_PAD_CFG_STRUCT(pad,						\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+		PAD_IRQ_CFG_DUAL_ROUTE(route1, route2,  trig, inv), \
+		PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE))
+
+#define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv)	\
+	PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, IOAPIC, SCI)
+
+#endif /* CONFIG_INTEL_PINCTRL_DUAL_ROUTE_SUPPORT */
+
+#endif /* _ASM_INTEL_PINCTRL_DEFS_H_ */