i.MX6: engicam: Add imx6q/imx6ul boards for existing boards

Add new board names for existing board support
imx6q - icore and icore_rqs boards
imx6ul - geam6ul and isiot boards

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

5 files changed, 0 insertions, 250 deletions

diff --git a/board/engicam/icorem6/Kconfig b/board/engicam/icorem6/Kconfig
deleted file mode 100644
index 4a1c9ac436..0000000000
--- a/board/engicam/icorem6/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MX6Q_ICORE
-
-config SYS_BOARD
-	default "icorem6"
-
-config SYS_VENDOR
-	default "engicam"
-
-config SYS_CONFIG_NAME
-	default "imx6-engicam"
-
-endif
diff --git a/board/engicam/icorem6/MAINTAINERS b/board/engicam/icorem6/MAINTAINERS
deleted file mode 100644
index a348bdde9e..0000000000
--- a/board/engicam/icorem6/MAINTAINERS
+++ /dev/null
@@ -1,10 +0,0 @@
-ICOREM6QDL BOARD
-M:	Jagan Teki <jagan@amarulasolutions.com>
-S:	Maintained
-F:	board/engicam/icorem6
-F:	include/configs/imx6-engicam.h
-F:	configs/imx6qdl_icore_mmc_defconfig
-F:	configs/imx6qdl_icore_nand_defconfig
-F:	arch/arm/dts/imx6qdl-icore.dtsi
-F:	arch/arm/dts/imx6q-icore.dts
-F:	arch/arm/dts/imx6dl-icore.dts
diff --git a/board/engicam/icorem6/Makefile b/board/engicam/icorem6/Makefile
deleted file mode 100644
index 9ec9ecdafb..0000000000
--- a/board/engicam/icorem6/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# Copyright (C) 2016 Amarula Solutions B.V.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y  := icorem6.o
diff --git a/board/engicam/icorem6/README b/board/engicam/icorem6/README
deleted file mode 100644
index 3779e9665d..0000000000
--- a/board/engicam/icorem6/README
+++ /dev/null
@@ -1,30 +0,0 @@
-How to use U-Boot on Engicam i.CoreM6 Solo/DualLite and Quad/Dual Starter Kit:
------------------------------------------------------------------------------
-
-$ make mrproper
-
-- Configure U-Boot for Engicam i.CoreM6 Quad/Dual/Solo/DualLite:
-$ make imx6qdl_icore_mmc_defconfig
-
-- Build U-Boot
-$ make
-
-This will generate the SPL image called SPL and the u-boot-dtb.img.
-
-- Flash the SPL image into the micro SD card:
-
-sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
-
-- Flash the u-boot-dtb.img image into the micro SD card:
-
-sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
-
-- Jumper settings:
-
-MMC Boot: JM3 Closed
-
-- Connect the Serial cable between the Starter Kit and the PC for the console.
-(J28 is the Linux Serial console connector)
-
-- Insert the micro SD card in the board, power it up and U-Boot messages should
-come up.
diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c
deleted file mode 100644
index a967ccd0a7..0000000000
--- a/board/engicam/icorem6/icorem6.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * Copyright (C) 2016 Amarula Solutions B.V.
- * Copyright (C) 2016 Engicam S.r.l.
- * Author: Jagan Teki <jagan@amarulasolutions.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <linux/sizes.h>
-
-#include <asm/arch/clock.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/video.h>
-
-#include "../common/board.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_NAND_MXS
-
-#define GPMI_PAD_CTRL0	(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
-#define GPMI_PAD_CTRL1	(PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
-			PAD_CTL_SRE_FAST)
-#define GPMI_PAD_CTRL2	(GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
-
-iomux_v3_cfg_t gpmi_pads[] = {
-	IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
-	IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
-	IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
-	IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
-	IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
-	IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
-	IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
-	IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
-	IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
-	IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
-	IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
-	IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
-	IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
-	IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
-	IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
-};
-
-void setup_gpmi_nand(void)
-{
-	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-	/* config gpmi nand iomux */
-	SETUP_IOMUX_PADS(gpmi_pads);
-
-	/* gate ENFC_CLK_ROOT clock first,before clk source switch */
-	clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
-
-	/* config gpmi and bch clock to 100 MHz */
-	clrsetbits_le32(&mxc_ccm->cs2cdr,
-			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
-			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
-			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
-			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
-			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
-			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
-
-	/* enable ENFC_CLK_ROOT clock */
-	setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
-
-	/* enable gpmi and bch clock gating */
-	setbits_le32(&mxc_ccm->CCGR4,
-		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
-		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
-		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
-		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
-		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
-
-	/* enable apbh clock gating */
-	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
-}
-#endif
-
-#if defined(CONFIG_VIDEO_IPUV3)
-static iomux_v3_cfg_t const rgb_pads[] = {
-	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
-	IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15),
-	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),
-	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),
-	IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
-	IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
-	IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
-	IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
-	IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
-	IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
-	IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
-	IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
-	IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
-	IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
-	IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
-	IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
-	IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
-	IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
-	IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
-	IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
-	IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
-	IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
-};
-
-static void enable_rgb(struct display_info_t const *dev)
-{
-	SETUP_IOMUX_PADS(rgb_pads);
-}
-
-struct display_info_t const displays[] = {
-	{
-		.bus	= -1,
-		.addr	= 0,
-		.pixfmt	= IPU_PIX_FMT_RGB666,
-		.detect	= NULL,
-		.enable	= enable_rgb,
-		.mode	= {
-			.name           = "Amp-WD",
-			.refresh        = 60,
-			.xres           = 800,
-			.yres           = 480,
-			.pixclock       = 30000,
-			.left_margin    = 30,
-			.right_margin   = 30,
-			.upper_margin   = 5,
-			.lower_margin   = 5,
-			.hsync_len      = 64,
-			.vsync_len      = 20,
-			.sync           = FB_SYNC_EXT,
-			.vmode          = FB_VMODE_NONINTERLACED
-		}
-	},
-};
-
-size_t display_count = ARRAY_SIZE(displays);
-
-void setup_display(void)
-{
-	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	int reg;
-
-	enable_ipu_clock();
-
-	/* Turn on LDB0,IPU,IPU DI0 clocks */
-	reg = __raw_readl(&mxc_ccm->CCGR3);
-	reg |=  (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff);
-	writel(reg, &mxc_ccm->CCGR3);
-
-	/* set LDB0, LDB1 clk select to 011/011 */
-	reg = readl(&mxc_ccm->cs2cdr);
-	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
-		MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
-	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
-		(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
-	writel(reg, &mxc_ccm->cs2cdr);
-
-	reg = readl(&mxc_ccm->cscmr2);
-	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
-	writel(reg, &mxc_ccm->cscmr2);
-
-	reg = readl(&mxc_ccm->chsccdr);
-	reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
-		MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
-	writel(reg, &mxc_ccm->chsccdr);
-
-	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
-		IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
-		IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
-		IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
-		IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
-		IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
-		IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
-		IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
-		IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
-	writel(reg, &iomux->gpr[2]);
-
-	reg = readl(&iomux->gpr[3]);
-	reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) |
-		(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
-		IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
-	writel(reg, &iomux->gpr[3]);
-}
-#endif /* CONFIG_VIDEO_IPUV3 */