diff options
author | Angelo Dureghello <angelo@sysam.it> | 2017-05-14 21:42:27 +0200 |
---|---|---|
committer | Angelo Dureghello <angelo@sysam.it> | 2017-08-18 01:26:08 +0200 |
commit | c74dda8b44622266feac7a0080a4302dbec052f5 (patch) | |
tree | 494d090e439f20ff002d035a61431a0dd26e0323 /board/freescale/m54455evb | |
parent | 336aee50cf55d4d98ddf3a4412c18286e7f0a4c0 (diff) |
m68k: mcf5445x: move early ddr init as board-specific
For certain boot types and sbf, for V4 cpu's, an early ddr/sdram init
is required. This patch moves this ddr/sdram early initalization
away from start.S (to be board related).
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Diffstat (limited to 'board/freescale/m54455evb')
-rw-r--r-- | board/freescale/m54455evb/Makefile | 1 | ||||
-rw-r--r-- | board/freescale/m54455evb/sbf_dram_init.S | 101 |
2 files changed, 102 insertions, 0 deletions
diff --git a/board/freescale/m54455evb/Makefile b/board/freescale/m54455evb/Makefile index 1c775fadb8..ecbc3ca044 100644 --- a/board/freescale/m54455evb/Makefile +++ b/board/freescale/m54455evb/Makefile @@ -6,3 +6,4 @@ # obj-y = m54455evb.o +extra-y += sbf_dram_init.o diff --git a/board/freescale/m54455evb/sbf_dram_init.S b/board/freescale/m54455evb/sbf_dram_init.S new file mode 100644 index 0000000000..2bf95a93a7 --- /dev/null +++ b/board/freescale/m54455evb/sbf_dram_init.S @@ -0,0 +1,101 @@ +/* + * Board-specific sbf ddr/sdram init. + * + * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + #include <config.h> + +.global sbf_dram_init +.text + +sbf_dram_init: + /* Dram Initialization a1, a2, and d0 */ + /* mscr sdram */ + move.l #0xFC0A4074, %a1 + move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1) + nop + + /* SDRAM Chip 0 and 1 */ + move.l #0xFC0B8110, %a1 + move.l #0xFC0B8114, %a2 + + /* calculate the size */ + move.l #0x13, %d1 + move.l #(CONFIG_SYS_SDRAM_SIZE), %d2 +#ifdef CONFIG_SYS_SDRAM_BASE1 + lsr.l #1, %d2 +#endif + +dramsz_loop: + lsr.l #1, %d2 + add.l #1, %d1 + cmp.l #1, %d2 + bne dramsz_loop +#ifdef CONFIG_SYS_NAND_BOOT + beq asm_nand_chk_status +#endif + /* SDRAM Chip 0 and 1 */ + move.l #(CONFIG_SYS_SDRAM_BASE), (%a1) + or.l %d1, (%a1) +#ifdef CONFIG_SYS_SDRAM_BASE1 + move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2) + or.l %d1, (%a2) +#endif + nop + + /* dram cfg1 and cfg2 */ + move.l #0xFC0B8008, %a1 + move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1) + nop + move.l #0xFC0B800C, %a2 + move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2) + nop + + move.l #0xFC0B8000, %a1 /* Mode */ + move.l #0xFC0B8004, %a2 /* Ctrl */ + + /* Issue PALL */ + move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) + nop + + /* Issue LEMR */ + move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1) + nop + move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1) + nop + + move.l #1000, %d1 + bsr asm_delay + + /* Issue PALL */ + move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) + nop + + /* Perform two refresh cycles */ + move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0 + nop + move.l %d0, (%a2) + move.l %d0, (%a2) + nop + + move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1) + nop + + move.l #500, %d1 + bsr asm_delay + + move.l #(CONFIG_SYS_SDRAM_CTRL), %d1 + and.l #0x7FFFFFFF, %d1 + + or.l #0x10000C00, %d1 + + move.l %d1, (%a2) + nop + + move.l #2000, %d1 + bsr asm_delay + + rts |