powerpc: remove 4xx support

There was for long time no activity in the 4xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 4xx,
so remove it.

Signed-off-by: Heiko Schocher <hs@denx.de>

6 files changed, 0 insertions, 267 deletions

diff --git a/board/gdsys/gdppc440etx/Kconfig b/board/gdsys/gdppc440etx/Kconfig
deleted file mode 100644
index 1f21c89175..0000000000
--- a/board/gdsys/gdppc440etx/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_GDPPC440ETX
-
-config SYS_BOARD
-	default "gdppc440etx"
-
-config SYS_VENDOR
-	default "gdsys"
-
-config SYS_CONFIG_NAME
-	default "gdppc440etx"
-
-endif
diff --git a/board/gdsys/gdppc440etx/MAINTAINERS b/board/gdsys/gdppc440etx/MAINTAINERS
deleted file mode 100644
index cd8d1c6f8e..0000000000
--- a/board/gdsys/gdppc440etx/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-GDPPC440ETX BOARD
-M:	Dirk Eibach <eibach@gdsys.de>
-S:	Maintained
-F:	board/gdsys/gdppc440etx/
-F:	include/configs/gdppc440etx.h
-F:	configs/gdppc440etx_defconfig
diff --git a/board/gdsys/gdppc440etx/Makefile b/board/gdsys/gdppc440etx/Makefile
deleted file mode 100644
index 7e3fc384d4..0000000000
--- a/board/gdsys/gdppc440etx/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= gdppc440etx.o
-extra-y	+= init.o
diff --git a/board/gdsys/gdppc440etx/config.mk b/board/gdsys/gdppc440etx/config.mk
deleted file mode 100644
index 73341a5121..0000000000
--- a/board/gdsys/gdppc440etx/config.mk
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-#
-# G&D 440EP/GR ETX-Module
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c
deleted file mode 100644
index 04191dff1e..0000000000
--- a/board/gdsys/gdppc440etx/gdppc440etx.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * (C) Copyright 2008
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * Based on board/amcc/yosemite/yosemite.c
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/4xx_pci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* info for FLASH chips */
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-int board_early_init_f(void)
-{
-	register uint reg;
-
-	/*
-	 * Setup the external bus controller/chip selects
-	 */
-	mfebc(EBC0_CFG, reg);
-	mtebc(EBC0_CFG, reg | 0x04000000);		/* Set ATC */
-
-	/*
-	 * Setup the GPIO pins
-	 */
-
-	/* setup Address lines for flash size 64Meg. */
-	out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000);
-	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000);
-	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000);
-
-	/* setup emac */
-	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
-	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
-	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
-	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
-	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
-
-	/* UART0 and UART1*/
-	out32(GPIO1_TCR, in32(GPIO1_TCR)     | 0x16000000);
-	out32(GPIO1_OSRL, in32(GPIO1_OSRL)   | 0x02180000);
-	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000);
-	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000);
-
-	/* disable boot-eeprom WP */
-	out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000);
-	out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000);
-	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000);
-	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000);
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000);
-
-	/* external interrupts IRQ0...3 */
-	out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
-	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
-	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
-
-
-	/*
-	 * Setup the interrupt controller polarities, triggers, etc.
-	 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all */
-	mtdcr(UIC0CR, 0x00000009);	/* ATI & UIC1 crit are critical */
-	mtdcr(UIC0PR, 0xfffffe13);	/* per ref-board manual */
-	mtdcr(UIC0TR, 0x01c00008);	/* per ref-board manual */
-	mtdcr(UIC0VR, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC1ER, 0x00000000);	/* disable all */
-	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC1PR, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr(UIC1TR, 0x00ffc000);	/* per ref-board manual */
-	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-
-	/*
-	 * Setup other serial configuration
-	 */
-	mfsdr(SDR0_PCI0, reg);
-	mtsdr(SDR0_PCI0, 0x80000000 | reg);	/* PCI arbiter enabled */
-	mtsdr(SDR0_PFC0, 0x00003e00);	/* Pin function */
-	mtsdr(SDR0_PFC1, 0x00048000);	/* Pin function: UART0 has 4 pins */
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	uint pbcr;
-	int size_val;
-	uint sz;
-
-	/* Re-do sizing to get full correct info */
-	mfebc(PB0CR, pbcr);
-
-	if (gd->bd->bi_flashsize > 0x08000000)
-		panic("Max. flash banksize is 128 MB!\n");
-
-	for (sz = gd->bd->bi_flashsize, size_val = 7;
-	    ((sz & 0x08000000) == 0) && (size_val > 0); --size_val)
-		sz <<= 1;
-
-	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-	mtebc(PB0CR, pbcr);
-
-	/* adjust flash start and offset */
-	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
-	gd->bd->bi_flashoffset = 0;
-
-	/* Monitor protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CONFIG_SYS_MONITOR_LEN,
-			    0xffffffff,
-			    &flash_info[0]);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module");
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-/*
- * Override weak pci_pre_init()
- */
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller *hose)
-{
-	/* First call common code */
-	__pci_pre_init(hose);
-
-	/* enable 66 MHz ext. Clock */
-	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000);
-	out32(GPIO1_OR, in32(GPIO1_OR) | 0x00008000);
-
-	return 1;
-}
-#endif	/* defined(CONFIG_PCI) */
diff --git a/board/gdsys/gdppc440etx/init.S b/board/gdsys/gdppc440etx/init.S
deleted file mode 100644
index 2db84b59a1..0000000000
--- a/board/gdsys/gdppc440etx/init.S
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
-* (C) Copyright 2008
-* Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
-*
-* based on board/amcc/yosemite/init.S
-* original Copyright not specified there
- * SPDX-License-Identifier:	GPL-2.0+
-*/
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-
-#include <asm/mmu.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- *************************************************************************/
-
-    .section .bootpg,"ax"
-    .globl tlbtab
-
-tlbtab:
-    tlbtab_start
-
-    /*
-     * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use
-     * the speed up boot process. It is patched after relocation to enable SA_I
-     */
-    tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR,
-	0, AC_RWX | SA_G/*|SA_I*/)
-
-    /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-    tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR,
-	0, AC_RWX | SA_G )
-
-    tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE,
-	0, AC_RWX | SA_IG )
-    tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE,
-	0, AC_RW | SA_IG )
-
-    /* PCI */
-    tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE,
-	0, AC_RW | SA_IG )
-    tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1,
-	0, AC_RW | SA_IG )
-    tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2,
-	0, AC_RW | SA_IG )
-    tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3,
-	0, AC_RW | SA_IG )
-
-    tlbtab_end