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authorTom Rini <trini@konsulko.com>2019-06-11 13:41:24 -0400
committerTom Rini <trini@konsulko.com>2019-06-11 13:41:24 -0400
commit529faf80c339b78bd361b59735664f2605322b8e (patch)
tree2186ebe6f8f713d0dd497eb9d20c1a30e64105bb /board/phytec/pcl063
parent68b90e57bc034e237923b02acb633dc4e91d44cb (diff)
parent23612534fe0fe426716ee9cb5cfeb74a456cb891 (diff)
Merge tag 'u-boot-imx-20190612' of git://git.denx.de/u-boot-imx
u-boot-imx-20190612 -------------------- - Board fixes: - imx6logic - wandboard - mx6sabre boots again - imx8qm_mek - pico-* boards - Toradex apalis / colibri - engicam imx6 (environment) - KP MX53 - opos6ul - Switch to DM: - vining2000 - dh MX6 - Toradex colibri i.MX7 - Novena - Security : fix CSF size for HAB - Other: - imx: fix building for i.mx8 without spl - pcie and switch to DM mx6sabreauto: Enable SPL SDP support
Diffstat (limited to 'board/phytec/pcl063')
-rw-r--r--board/phytec/pcl063/Kconfig13
-rw-r--r--board/phytec/pcl063/MAINTAINERS6
-rw-r--r--board/phytec/pcl063/pcl063.c5
-rw-r--r--board/phytec/pcl063/spl.c76
4 files changed, 95 insertions, 5 deletions
diff --git a/board/phytec/pcl063/Kconfig b/board/phytec/pcl063/Kconfig
index 977db70f64..58f72f2791 100644
--- a/board/phytec/pcl063/Kconfig
+++ b/board/phytec/pcl063/Kconfig
@@ -10,3 +10,16 @@ config SYS_CONFIG_NAME
default "pcl063"
endif
+
+if TARGET_PCL063_ULL
+
+config SYS_BOARD
+ default "pcl063"
+
+config SYS_VENDOR
+ default "phytec"
+
+config SYS_CONFIG_NAME
+ default "pcl063_ull"
+
+endif
diff --git a/board/phytec/pcl063/MAINTAINERS b/board/phytec/pcl063/MAINTAINERS
index c65a951f3d..710b9680d4 100644
--- a/board/phytec/pcl063/MAINTAINERS
+++ b/board/phytec/pcl063/MAINTAINERS
@@ -1,8 +1,14 @@
PCL063 BOARD
M: Martyn Welch <martyn.welch@collabora.com>
+M: Parthiban Nallathambi <parthitce@gmail.com>
S: Maintained
F: arch/arm/dts/imx6ul-pcl063.dtsi
F: arch/arm/dts/imx6ul-phycore-segin.dts
+F: arch/arm/dts/imx6ull-phycore-segin.dts
+F: arch/arm/dts/pcl063-common.dtsi
+F: arch/arm/dts/imx6ull-u-boot.dtsi
F: board/phytec/pcl063/
F: configs/phycore_pcl063_defconfig
+F: configs/phycore_pcl063_ull_defconfig
F: include/configs/pcl063.h
+F: include/configs/pcl063_ull.h
diff --git a/board/phytec/pcl063/pcl063.c b/board/phytec/pcl063/pcl063.c
index 38b233d1b0..17012df037 100644
--- a/board/phytec/pcl063/pcl063.c
+++ b/board/phytec/pcl063/pcl063.c
@@ -200,7 +200,10 @@ int board_init(void)
int checkboard(void)
{
- puts("Board: PHYTEC phyCORE-i.MX6UL\n");
+ u32 cpurev = get_cpu_rev();
+
+ printf("Board: PHYTEC phyCORE-i.MX%s\n",
+ get_imx_type((cpurev & 0xFF000) >> 12));
return 0;
}
diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c
index b93cd493f2..73a774645d 100644
--- a/board/phytec/pcl063/spl.c
+++ b/board/phytec/pcl063/spl.c
@@ -13,6 +13,7 @@
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
#include <fsl_esdhc.h>
/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */
@@ -117,11 +118,32 @@ static iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
+#ifndef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+#endif
+
static struct fsl_esdhc_cfg usdhc_cfg[] = {
{
.esdhc_base = USDHC1_BASE_ADDR,
.max_bus_width = 4,
},
+#ifndef CONFIG_NAND_MXS
+ {
+ .esdhc_base = USDHC2_BASE_ADDR,
+ .max_bus_width = 8,
+ },
+#endif
};
int board_mmc_getcd(struct mmc *mmc)
@@ -131,12 +153,58 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis)
{
- imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+ int i, ret;
+
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ SETUP_IOMUX_PADS(usdhc1_pads);
+ usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ break;
+#ifndef CONFIG_NAND_MXS
+ case 1:
+ SETUP_IOMUX_PADS(usdhc2_pads);
+ usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ break;
+#endif
+ default:
+ printf("Warning - USDHC%d controller not supporting\n",
+ i + 1);
+ return 0;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ return ret;
+ }
+ }
+
+ return 0;
}
+void board_boot_order(u32 *spl_boot_list)
+{
+ u32 bmode = imx6_src_get_boot_mode();
+ u8 boot_dev = BOOT_DEVICE_MMC1;
+
+ switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
+ case IMX6_BMODE_SD:
+ case IMX6_BMODE_ESD:
+ boot_dev = BOOT_DEVICE_MMC1;
+ break;
+ case IMX6_BMODE_MMC:
+ case IMX6_BMODE_EMMC:
+ boot_dev = BOOT_DEVICE_MMC2;
+ break;
+ default:
+ /* Default - BOOT_DEVICE_MMC1 */
+ printf("Wrong board boot order\n");
+ break;
+ }
+
+ spl_boot_list[0] = boot_dev;
+}
#endif /* CONFIG_FSL_ESDHC */
void board_init_f(ulong dummy)