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authorLokesh Vutla <lokeshvutla@ti.com>2016-05-16 11:47:26 +0530
committerTom Rini <trini@konsulko.com>2016-05-27 15:47:52 -0400
commit97f3a178b2a3d5a7767cb6cb15ba9c40ba804ebb (patch)
tree006195ca5c4c6e7ec9f52d7a2426e07bcc1aa053 /board/sr1500/socfpga.c
parent3164f3c68941a1665090bca903d56754ac36f89d (diff)
board: AM335x-ICEv2: Add cpsw support
In order to enable cpsw on AM335x ICEv2 board, the following needs to be done: 1)There are few on board jumper settings which gives a choice between cpsw and PRUSS, that needs to be properly selected[1]. Even after selecting this, there are few GPIOs which control these muxes that needs to be held high. 2) The clock to PHY is provided by a PLL-based clock synthesizer[2] connected via I2C. This needs to properly programmed and locked for PHY operation. And PHY needs to be reset before before being used, which is also held by a GPIO. 3) RMII mode needs to be selected. [1] http://www.ti.com/lit/zip/tidr336 [2] http://www.ti.com/lit/ds/symlink/cdce913.pdf Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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