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authorYuantian Tang <andy.tang@nxp.com>2019-04-10 16:43:34 +0800
committerPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>2019-05-22 12:24:24 +0530
commit353f36d96e49f3ad34ffc4a16dea7398c6f90f65 (patch)
tree471648fb8a99207408b3b367606fcd82918fa5d3 /board
parentd4ad111dc4da561d1638f5edb87fa2e6012300d8 (diff)
armv8: ls1028ardb: Add support for LS1028ARDB
LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluation platform that supports the LS1028A family SoCs. This patch add basic support of the platform. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'board')
-rw-r--r--board/freescale/ls1028a/Kconfig26
-rw-r--r--board/freescale/ls1028a/MAINTAINERS10
-rw-r--r--board/freescale/ls1028a/Makefile8
-rw-r--r--board/freescale/ls1028a/README79
-rw-r--r--board/freescale/ls1028a/ddr.c20
-rw-r--r--board/freescale/ls1028a/ls1028a.c193
6 files changed, 336 insertions, 0 deletions
diff --git a/board/freescale/ls1028a/Kconfig b/board/freescale/ls1028a/Kconfig
new file mode 100644
index 0000000000..bbfd4dd07d
--- /dev/null
+++ b/board/freescale/ls1028a/Kconfig
@@ -0,0 +1,26 @@
+if TARGET_LS1028ARDB
+
+config SYS_BOARD
+ default "ls1028a"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1028ardb"
+
+config EMMC_BOOT
+ bool "Support for booting from EMMC"
+ default n
+
+config SYS_TEXT_BASE
+ default 0x96000000 if SD_BOOT || EMMC_BOOT
+ default 0x82000000 if TFABOOT
+ default 0x20100000
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/ls1028a/MAINTAINERS b/board/freescale/ls1028a/MAINTAINERS
new file mode 100644
index 0000000000..135454cfd6
--- /dev/null
+++ b/board/freescale/ls1028a/MAINTAINERS
@@ -0,0 +1,10 @@
+LS1028ARDB BOARD
+M: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
+M: Rai Harninder <harninder.rai@nxp.com>
+M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+M: Tang Yuantian <andy.tang@nxp.com>
+S: Maintained
+F: board/freescale/ls1028a/
+F: include/configs/ls1028a_common.h
+F: include/configs/ls1028ardb.h
+F: configs/ls1028ardb_tfa_defconfig
diff --git a/board/freescale/ls1028a/Makefile b/board/freescale/ls1028a/Makefile
new file mode 100644
index 0000000000..9bc144cbfe
--- /dev/null
+++ b/board/freescale/ls1028a/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2019 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls1028a.o
+obj-y += ddr.o
diff --git a/board/freescale/ls1028a/README b/board/freescale/ls1028a/README
new file mode 100644
index 0000000000..94a390c917
--- /dev/null
+++ b/board/freescale/ls1028a/README
@@ -0,0 +1,79 @@
+Overview
+--------
+The LS1028A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports ARM SoC LS1028A and its
+derivatives.
+
+LS1028A SoC Overview
+--------------------------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+
+RDB Default Switch Settings (1: ON; 0: OFF)
+-------------------------------------------
+For XSPI NOR boot (default)
+SW2: 1111_1000
+SW3: 1111_0000
+SW5: 0011_1001
+
+For SD Boot
+SW2: 1000_1000
+SW3: 1111_0000
+SW5: 0011_1001
+
+For eMMC Boot
+SW2: 1001_1000
+SW3: 1111_0000
+SW5: 0011_1001
+
+LS1028ARDB board Overview
+-------------------------
+Processor
+ Two Arm Cortex- A72 processor cores:
+ - Based on 64-bit ARMv8 architecture
+ - Up to 1.3 GHz operation
+ - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
+ data cache
+ - Arranged as a single cluster of two cores sharing a single 1 MB L2
+ cache
+DDR memory
+ - Five onboard 1G x8 discrete memory modules (Four data byte lanes
+ ECC)
+ - 32-bit data and 4-bit ECC
+ - One chip select
+ - Data transfer rates of up to 1.6 GT/s
+ - Single-bit error correction and double-bit error detection ECC (4-bit
+ check word across 32-bit data)
+High-speed serial ports(SerDes)
+ - Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the
+ Qualcomm AR8033 PHY
+ - Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected
+ through the NXP F104S8A PHY
+ - Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3
+ (8 Gbit/s) cards
+ - Lane 3: Connects to one PCIe M.2 Key-E slot or one SATA M.2 Key-B
+ slot through a register mux to support either PCIe Gen 3 (8 Gbit/s) or
+ SATA Gen 3 cards (6 Gbit/s) at a time
+eSDHC
+ - eSDHC1, eSDHC2
+SPI
+ - Connects to two mikroBUS sockets to support mikro-click modules,
+ such as Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near
+ field communications (NFC) controller
+Octal SPI (XSPI)
+ - One 256 MB onboard XSPI serial NOR flash memory
+ - One 512 MB onboard XSPI serial NAND flash memory
+ - Supports a QSPI emulator for offboard QSPI emulation
+I2C
+ - All system devices are accessed via I2C1, which is multiplexed on
+ I2C multiplexer PCA9848 to isolate address conflicts and reduce
+ capacitive load
+ - I2C1 is used for EEPROMs, RTC, INA220 current-power sensor,
+ thermal monitor, PCIe/SATA M.2 connectors and mikro-click modules
+ 1 and 2
+CAN
+ - The two CAN DB9 ports can support CAN FD fast phase at data rates of
+ up to 5 Mbit/s
+Serial audio interface(SAI)
+ - Audio codec SGTL5000 provides headphone and audio LINEOUT for
+ stereo speakers
+ - IEEE1588 interface to support audio on SAI4
diff --git a/board/freescale/ls1028a/ddr.c b/board/freescale/ls1028a/ddr.c
new file mode 100644
index 0000000000..74d3af5c35
--- /dev/null
+++ b/board/freescale/ls1028a/ddr.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fsl_initdram(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+
+ if (!gd->ram_size)
+ gd->ram_size = fsl_ddr_sdram_size();
+
+ return 0;
+}
diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c
new file mode 100644
index 0000000000..e3666c34b6
--- /dev/null
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <fsl_ddr.h>
+#include <asm/io.h>
+#include <hwconfig.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <environment.h>
+#include <asm/arch-fsl-layerscape/soc.h>
+#include <i2c.h>
+#include <asm/arch/soc.h>
+#ifdef CONFIG_FSL_LS_PPA
+#include <asm/arch/ppa.h>
+#endif
+#include <fsl_immap.h>
+#include <netdev.h>
+
+#include <fdtdec.h>
+#include <miiphy.h>
+#include "../common/qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_FSL_LS_PPA
+ ppa_init();
+#endif
+
+#ifndef CONFIG_SYS_EARLY_PCI_INIT
+ pci_init();
+#endif
+
+#if defined(CONFIG_TARGET_LS1028ARDB)
+ u8 val = I2C_MUX_CH_DEFAULT;
+
+ i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
+#endif
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+ i2c_early_init_f();
+#endif
+
+ fsl_lsch3_early_init_f();
+ return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+ puts("\nDDR ");
+ print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+ print_ddr_info(0);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ u64 base[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+
+ ft_cpu_setup(blob, bd);
+
+ /* fixup DT for the two GPP DDR banks */
+ base[0] = gd->bd->bi_dram[0].start;
+ size[0] = gd->bd->bi_dram[0].size;
+ base[1] = gd->bd->bi_dram[1].start;
+ size[1] = gd->bd->bi_dram[1].size;
+
+#ifdef CONFIG_RESV_RAM
+ /* reduce size if reserved memory is within this bank */
+ if (gd->arch.resv_ram >= base[0] &&
+ gd->arch.resv_ram < base[0] + size[0])
+ size[0] = gd->arch.resv_ram - base[0];
+ else if (gd->arch.resv_ram >= base[1] &&
+ gd->arch.resv_ram < base[1] + size[1])
+ size[1] = gd->arch.resv_ram - base[1];
+#endif
+
+ fdt_fixup_memory_banks(blob, base, size, 2);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_QIXIS
+int checkboard(void)
+{
+#ifdef CONFIG_TFABOOT
+ enum boot_src src = get_boot_src();
+#endif
+ u8 sw;
+
+ int clock;
+ char *board;
+ char buf[64] = {0};
+ static const char *freq[6] = {"100.00", "125.00", "156.25",
+ "161.13", "322.26", "100.00 SS"};
+
+ cpu_name(buf);
+ /* find the board details */
+ sw = QIXIS_READ(id);
+
+ switch (sw) {
+ case 0x46:
+ board = "QDS";
+ break;
+ case 0x47:
+ board = "RDB";
+ break;
+ case 0x49:
+ board = "HSSI";
+ break;
+ default:
+ board = "unknown";
+ break;
+ }
+
+ sw = QIXIS_READ(arch);
+ printf("Board: %s-%s, Version: %c, boot from ",
+ buf, board, (sw & 0xf) + 'A' - 1);
+
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+#ifdef CONFIG_TFABOOT
+ if (src == BOOT_SOURCE_SD_MMC) {
+ puts("SD\n");
+ } else if (src == BOOT_SOURCE_SD_MMC2) {
+ puts("eMMC\n");
+ } else {
+#endif
+#ifdef CONFIG_SD_BOOT
+ puts("SD\n");
+#elif defined(CONFIG_EMMC_BOOT)
+ puts("eMMC\n");
+#else
+ switch (sw) {
+ case 0:
+ case 4:
+ printf("NOR\n");
+ break;
+ case 1:
+ printf("NAND\n");
+ break;
+ default:
+ printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+ break;
+ }
+#endif
+#ifdef CONFIG_TFABOOT
+ }
+#endif
+
+ printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
+ puts("SERDES1 Reference : ");
+
+ sw = QIXIS_READ(brdcfg[2]);
+#ifdef CONFIG_TARGET_LS1028ARDB
+ clock = (sw >> 6) & 3;
+#else
+ clock = (sw >> 4) & 0xf;
+#endif
+
+ printf("Clock1 = %sMHz ", freq[clock]);
+#ifdef CONFIG_TARGET_LS1028ARDB
+ clock = (sw >> 4) & 3;
+#else
+ clock = sw & 0xf;
+#endif
+ printf("Clock2 = %sMHz\n", freq[clock]);
+
+ return 0;
+}
+#endif