diff options
| author | Stefano Babic <sbabic@denx.de> | 2014-07-16 08:51:30 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2014-07-16 08:51:30 +0200 |
| commit | dab5e3469d294a4e1ffed8407d296a78e02cc01f (patch) | |
| tree | c6378034591210b3142ca3add806d52c6ea22b3b /board | |
| parent | 14a1613140519a8d0a88e6054c302a8cb3e067a5 (diff) | |
| parent | 524123a70761110c5cf3ccc5f52f6d4da071b959 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
Conflicts:
boards.cfg
Diffstat (limited to 'board')
195 files changed, 2781 insertions, 23781 deletions
diff --git a/board/Barix/ipam390/ipam390.c b/board/Barix/ipam390/ipam390.c index ae88b4230a..6ce8960bbd 100644 --- a/board/Barix/ipam390/ipam390.c +++ b/board/Barix/ipam390/ipam390.c @@ -20,7 +20,7 @@ #include <spi.h> #include <spi_flash.h> #include <asm/arch/hardware.h> -#include <asm/arch/emif_defs.h> +#include <asm/ti-common/davinci_nand.h> #include <asm/arch/emac_defs.h> #include <asm/arch/pinmux_defs.h> #include <asm/io.h> diff --git a/board/BuR/tseries/board.c b/board/BuR/tseries/board.c index f0510e599e..c0178e75cf 100644 --- a/board/BuR/tseries/board.c +++ b/board/BuR/tseries/board.c @@ -117,7 +117,9 @@ void sdram_init(void) int board_init(void) { gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; +#ifdef CONFIG_NAND gpmc_init(); +#endif return 0; } diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c index 3c76e96926..210ac71738 100644 --- a/board/BuR/tseries/mux.c +++ b/board/BuR/tseries/mux.c @@ -27,6 +27,11 @@ static struct module_pin_mux uart0_pin_mux[] = { }; #ifdef CONFIG_MMC static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */ + {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */ + {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */ + {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */ + {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ @@ -125,7 +130,7 @@ static struct module_pin_mux gpIOs[] = { {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)}, /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3, later used as MODE3 for PWM */ {OFFSET(mmc0_dat2), (MODE(7) | PULLUDEN | RXACTIVE)}, - /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */ + /* GPIO2_27 (MMC0_DAT1) - MII_nNAND */ {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)}, /* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */ {OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)}, @@ -148,7 +153,7 @@ static struct module_pin_mux gpIOs[] = { * DISPLAY_ONOFF (Backlight Enable at LVDS Versions) */ {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)}, - /* GPIO0_19 (DMA_INTR0) - ISPLAY_MODE (CPLD) */ + /* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */ {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* GPIO0_20 (DMA_INTR1) - REP-Switch */ {OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)}, diff --git a/board/Marvell/include/pci.h b/board/Marvell/include/pci.h index 167248db1e..572e0d345d 100644 --- a/board/Marvell/include/pci.h +++ b/board/Marvell/include/pci.h @@ -7,8 +7,8 @@ /* includes */ -#include"core.h" -#include"memory.h" +#include "core.h" +#include "memory.h" /* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */ #define PCI_MAX_DEVICES 22 diff --git a/board/RPXlite_dw/Makefile b/board/RPXlite_dw/Makefile deleted file mode 100644 index eff33cff95..0000000000 --- a/board/RPXlite_dw/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = RPXlite_dw.o flash.o diff --git a/board/RPXlite_dw/README b/board/RPXlite_dw/README deleted file mode 100644 index 9e2d0f42a0..0000000000 --- a/board/RPXlite_dw/README +++ /dev/null @@ -1,161 +0,0 @@ - -After following the step of Yoo. Jonghoon and Wolfgang Denk, -I ported u-boot on RPXlite DW version board: RPXlite_DW or LITE_DW. - -There are at least three differences between the Yoo-ported RPXlite and the RPXlite_DW. - -Board(in U-Boot) version(in EmbeddedPlanet) CPU SDRAM FLASH -RPXlite RPXlite CW 850 16MB 4MB -RPXlite_DW RPXlite DW(EP 823 H1 DW) 823e 64MB 16MB - -This fireware is specially coded for EmbeddedPlanet Co. Software Development -Platform(RPXlite DW),which has a NEC NL6448BC20-08 LCD panel. - -It has the following three features: - -1. 64MHz/48MHz system frequence setting options. -The default setting is 48MHz.To get a 64MHz u-boot,just add -'64' in make command,like - -make distclean -make RPXlite_DW_64_config -make all - -2. CONFIG_ENV_IS_IN_FLASH/CONFIG_ENV_IS_IN_NVRAM - -The default environment parameter is stored in FLASH because it is a common choice for -environment parameter.So I make NVRAM as backup parameter storeage.The reason why I -didn't use EEPROM for ENV is that PlanetCore V2.0 use EEPROM as environment parameter -home.Because of the possibility of using two firewares on this board,I didn't -'disturb' EEPROM.To get NVRAM support,you may use the following build command: - -make distclean -make RPXlite_DW_NVRAM_config -make all - -3. LCD panel support - -To support the Platform better,I added LCD panel(NL6448BC20-08) function. -For the convenience of debug, CONFIG_PERBOOT was supported. So you just -perss ENTER if you want to get a serial console in boot downcounting. -Then you can switch to LCD and serial console freely just typing -'run lcd' or 'run ser'. They are only vaild when CONFIG_LCD was enabled. - -To get a LCD support u-boot,you can do the following: - -make distclean -make RPXlite_DW_LCD_config -make all - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -The basic make commands could be: - -make RPXlite_DW_config -make RPXlite_DW_64_config -make RPXlite_DW_LCD_config -make RPXlite_DW_NVRAM_config - -BTW,you can combine the above features together and get a workable u-boot to meet your need. -For example,to get a 64MHZ && ENV_IS_IN_FLASH && LCD panel support u-boot,you can type: - -make RPXlite_DW_NVRAM_64_LCD_config -make all - -So other combining make commands could be: - -make RPXlite_DW_NVRAM_64_config -make RPXlite_DW_NVRAM_LCD_config -make RPXlite_DW_64_LCD_config - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The boot process by "make RPXlite_DW_config" could be: - -U-Boot 1.1.2 (Aug 29 2004 - 15:11:27) - -CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB D-Cache -Board: RPXlite_DW -DRAM: 64 MB -FLASH: 16 MB -*** Warning - bad CRC, using default environment - -In: serial -Out: serial -Err: serial -Net: SCC ETHERNET -u-boot> - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -A word on the U-Boot environment variable setting and usage : - -In the beginning, you could just need very simple default environment variable setting, -like[include/configs/RPXlite.h] : - -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -This is enough for kernel NFS test. But as debug process goes on, you would expect -to save some time on environment variable setting and u-boot/kernel updating. -So the default environment variable setting would become more complicated. Just like -the one I did in include/configs/RPXlite_DW.h. - -Two u-boot commands, ku and uu, should be careful to use. They were designed to update -kernel and u-boot image file respectively. You must tftp your image to default address -'100000' and then use them correctly. Yeah, you can create your own command to do this -job. :-) The example u-boot image updating process could be : - -u-boot>t 100000 RPXlite_DW_LCD.bin -Using SCC ETHERNET device -TFTP from server 172.16.115.6; our IP address is 172.16.115.7 -Filename 'RPXlite_DW_LCD.bin'. -Load address: 0x100000 -Loading: ############################# -done -Bytes transferred = 144700 (2353c hex) -u-boot>run uu -Un-Protect Flash Sectors 0-4 in Bank # 1 -Erase Flash Sectors 0-4 in Bank # 1 -.... done -Copy to Flash... done -ff000000: 27051956 552d426f 6f742031 2e312e32 '..VU-Boot 1.1.2 -ff000010: 20284175 67203239 20323030 34202d20 (Aug 29 2004 - -ff000020: 31353a32 303a3238 29000000 00000000 15:20:28)....... -ff000030: 00000000 00000000 00000000 00000000 ................ -ff000040: 00000000 00000000 00000000 00000000 ................ -ff000050: 00000000 00000000 00000000 00000000 ................ -ff000060: 00000000 00000000 00000000 00000000 ................ -ff000070: 00000000 00000000 00000000 00000000 ................ -ff000080: 00000000 00000000 00000000 00000000 ................ -ff000090: 00000000 00000000 00000000 00000000 ................ -ff0000a0: 00000000 00000000 00000000 00000000 ................ -ff0000b0: 00000000 00000000 00000000 00000000 ................ -ff0000c0: 00000000 00000000 00000000 00000000 ................ -ff0000d0: 00000000 00000000 00000000 00000000 ................ -ff0000e0: 00000000 00000000 00000000 00000000 ................ -ff0000f0: 00000000 00000000 00000000 00000000 ................ -u-boot updating finished -u-boot> - -Also for environment updating, 'run eu' could let you erase OLD default environment variable -and then use the working u-boot environment setting. - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Finally, if you want to keep the serial port to possible debug on spot for deployment, you -just need to enable 'DEPLOYMENT' in RPXlite_DW.h as 'DEBUG' does. Only the special string -defined by CONFIG_AUTOBOOT_STOP_STR like 'st' can stop the autoboot. - -I'd like to extend my heartfelt gratitute to kind people for helping me work it out. -I would particually thank Wolfgang Denk for his nice help. - -Enjoy, - -Sam Song, samsongshu@yahoo.com.cn -Institute of Electrical Machinery and Controls -Shanghai University - -Oct. 11, 2004 diff --git a/board/RPXlite_dw/RPXlite_dw.c b/board/RPXlite_dw/RPXlite_dw.c deleted file mode 100644 index 29d52dec8c..0000000000 --- a/board/RPXlite_dw/RPXlite_dw.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * (C) Copyright 2004 - * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Sam Song - * U-Boot port on RPXlite DW board : RPXlite_DW or LITE_DW - * Tested on working at 64MHz(CPU)/32MHz(BUS),48MHz/24MHz - * with 64MB, 2 SDRAM Micron chips,MT48LC16M16A2-75. - */ - -#include <common.h> -#include <mpc8xx.h> - -/* ------------------------------------------------------------------------- */ -static long int dram_size (long int, long int *, long int); -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 00h in UPMA RAM) - */ - 0x0F03CC04, 0x00ACCC24, 0x1FF74C20, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, - - /* - * Burst Read. (Offset 08h in UPMA RAM) - */ - 0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20, - 0x01FFCC20, 0x1FF74C20, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18h in UPMA RAM) - */ - 0x0F03CC02, 0x00AC0C24, 0x1FF74C25, /* last */ - _NOT_USED_, _NOT_USED_, 0x0FA00C34,0x0FFFCC35, - _NOT_USED_, - - /* - * Burst Write. (Offset 20h in UPMA RAM) - */ - 0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22, - 0x01FFFC24, 0x1FF74C25, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* - * Refresh. (Offset 30h in UPMA RAM) - */ - 0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34, - 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4, - /* INIT sequence RAM WORDS - * SDRAM Initialization (offset 0x36 in UPMA RAM) - * The above definition uses the remaining space - * to establish an initialization sequence, - * which is executed by a RUN command. - * The sequence is COMMAND INHIBIT(NOP),Precharge, - * Load Mode Register,NOP,Auto Refresh. - */ - - /* - * Exception. (Offset 3Ch in UPMA RAM) - */ - 0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_ -}; - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: RPXlite_DW\n") ; - return (0) ; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size9; - - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR ; - - memctl->memc_mar = 0x00000088; - - /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ - /*Disable Periodic timer A. */ - - udelay(200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002236; /* SDRAM bank 0 - refresh twice */ - - udelay(1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - /*Enable Periodic timer A */ - - udelay (1000); - - /* Check Bank 0 Memory Size - * try 9 column mode - */ - - size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE); - - /* - * Final mapping: - */ - - memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - - udelay (1000); - - return (size9); -} - -void rpxlite_init (void) -{ - /* Enable NVRAM */ - *((uchar *) BCSR0) |= BCSR0_ENNVRAM; -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} diff --git a/board/RPXlite_dw/flash.c b/board/RPXlite_dw/flash.c deleted file mode 100644 index c8de5ef5ee..0000000000 --- a/board/RPXlite_dw/flash.c +++ /dev/null @@ -1,474 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * Some of flash control words are modified. (from 2x16bit device - * to 4x8bit device) - * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices - * are not tested. - * - * (?) Does an RPXLite board which - * does not use AM29LV800 flash memory exist ? - * I don't know... - */ - -/* Yes,Yoo.They do use other FLASH for the board. - * - * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn - * U-Boot port on RPXlite DW version board - * - * By now,it uses 4 AM29DL323DB90VI devices(4x8bit). - * The total FLASH has 16MB(4x4MB). - * I just made some necessary changes on the basis of Wolfgang and Yoo's job. - * - * June 8, 2004 */ - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions vu_long : volatile unsigned long IN include/common.h - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -unsigned long flash_init (void) -{ - unsigned long size_b0 ; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* If Monitor is in the cope of FLASH,then - * protect this area by default in case for - * other occupation. [SAM] */ - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, - &flash_info[0]); -#endif - flash_info[0].size = size_b0; - return (size_b0); -} - -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x00010000; - info->start[3] = base + 0x00018000; - info->start[4] = base + 0x00020000; - info->start[5] = base + 0x00028000; - info->start[6] = base + 0x00030000; - info->start[7] = base + 0x00038000; - - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i-7) * 0x00040000); - } - } else { - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - -} - -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMDL323B: printf ("AM29DL323B (32 Mbit, bottom boot sector)\n"); - break; - /* I just add the FLASH_AMDL323B for RPXlite_DW BOARD. [SAM] */ - default: printf ("Unknown Chip Type\n"); - break; - } - printf (" Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count); - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s",info->start[i],info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0xAAA] = 0x00AA00AA ; - addr[0x555] = 0x00550055 ; - addr[0xAAA] = 0x00900090 ; - - value = addr[0] ; - switch (value & 0x00FF00FF) { - case AMD_MANUFACT: /* AMD_MANUFACT =0x00010001 in flash.h */ - info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h */ - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[2] ; /* device ID */ - switch (value & 0x00FF00FF) { - case (AMD_ID_LV400T & 0x00FF00FF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - case (AMD_ID_LV400B & 0x00FF00FF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - case (AMD_ID_LV800T & 0x00FF00FF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - case (AMD_ID_LV800B & 0x00FF00FF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; /* Size doubled by yooth */ - break; /* => 4 MB */ - case (AMD_ID_LV160T & 0x00FF00FF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - case (AMD_ID_LV160B & 0x00FF00FF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - case (AMD_ID_DL323B & 0x00FF00FF): - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x01000000; - break; /* => 16 MB(4x4MB) */ - /* AMD_ID_DL323B= 0x22532253 FLASH_AMDL323B= 0x0013 - * AMD_ID_DL323B could be found in <flash.h>.[SAM] - * So we could get : flash_id = 0x00000013. - * The first four-bit represents VEDOR ID,leaving others for FLASH ID. */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* FLASH_BTYPE=0x0001 mask for bottom boot sector type.If the last bit equals 1, - * it means bottom boot flash. GOOD IDEA! [SAM] - */ - - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x00010000; - info->start[3] = base + 0x00018000; - info->start[4] = base + 0x00020000; - info->start[5] = base + 0x00028000; - info->start[6] = base + 0x00030000; - info->start[7] = base + 0x00038000; - - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i-7) * 0x00040000) ; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - /* info->protect[i] = addr[4] & 1 ; */ - /* Mask it for disorder FLASH protection **[Sam]** */ - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0xF0F0F0F0; /* reset bank */ - } - return (info->size); -} - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0x80808080; - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *)(info->start[sect]) ; - addr[0] = 0x30303030 ; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long *)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/RPXlite_dw/u-boot.lds b/board/RPXlite_dw/u-boot.lds deleted file mode 100644 index 0eb2fba00c..0000000000 --- a/board/RPXlite_dw/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXlite_dw/u-boot.lds.debug b/board/RPXlite_dw/u-boot.lds.debug deleted file mode 100644 index 0ea27e8759..0000000000 --- a/board/RPXlite_dw/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/abilis/tb100/Makefile b/board/abilis/tb100/Makefile new file mode 100644 index 0000000000..4f273b322b --- /dev/null +++ b/board/abilis/tb100/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2014 Pierrick Hascoet, Abilis Systems +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += tb100.o diff --git a/board/abilis/tb100/tb100.c b/board/abilis/tb100/tb100.c new file mode 100644 index 0000000000..ff3632f6c0 --- /dev/null +++ b/board/abilis/tb100/tb100.c @@ -0,0 +1,23 @@ +/* + * (C) Copyright 2014 Pierrick Hascoet, Abilis Systems + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> + +void reset_cpu(ulong addr) +{ +#define CRM_SWRESET 0xff101044 + writel(0x1, (void *)CRM_SWRESET); +} + +int board_eth_init(bd_t *bis) +{ + if (designware_initialize(ETH0_BASE_ADDRESS, 0) >= 0) + return 1; + + return 0; +} diff --git a/board/adder/Makefile b/board/adder/Makefile deleted file mode 100644 index 8dc505a5fe..0000000000 --- a/board/adder/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2004 Arabella Software Ltd. -# Yuli Barcohen <yuli@arabellasw.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := adder.o diff --git a/board/adder/adder.c b/board/adder/adder.c deleted file mode 100644 index 2ee7096b83..0000000000 --- a/board/adder/adder.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (C) 2004-2005 Arabella Software Ltd. - * Yuli Barcohen <yuli@arabellasw.com> - * - * Support for Analogue&Micro Adder boards family. - * Tested on AdderII and Adder87x. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> -#if defined(CONFIG_OF_LIBFDT) - #include <libfdt.h> -#endif - -/* - * SDRAM is single Samsung K4S643232F-T70 chip (8MB) - * or single Micron MT48LC4M32B2TG-7 chip (16MB). - * Minimal CPU frequency is 40MHz. - */ -static uint sdram_table[] = { - /* Single read (offset 0x00 in UPM RAM) */ - 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00, - 0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04, - - /* Burst read (offset 0x08 in UPM RAM) */ - 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44, - 0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35, - 0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35, - - /* Single write (offset 0x18 in UPM RAM) */ - 0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47, - 0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* Burst write (offset 0x20 in UPM RAM) */ - 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* Refresh (offset 0x30 in UPM RAM) */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* Exception (offset 0x3C in UPM RAM) */ - 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04 -}; - -phys_size_t initdram (int board_type) -{ - long int msize; - volatile immap_t *immap = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint)); - - /* Configure SDRAM refresh */ - memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */ - - memctl->memc_mamr = (94 << 24) | CONFIG_SYS_MAMR; /* No refresh */ - udelay(200); - - /* Run precharge from location 0x15 */ - memctl->memc_mar = 0x0; - memctl->memc_mcr = 0x80002115; - udelay(200); - - /* Run 8 refresh cycles */ - memctl->memc_mcr = 0x80002830; - udelay(200); - - /* Run MRS pattern from location 0x16 */ - memctl->memc_mar = 0x88; - memctl->memc_mcr = 0x80002116; - udelay(200); - - memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */ - memctl->memc_or1 = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM; - memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V; - - msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE); - memctl->memc_or1 |= ~(msize - 1); - - return msize; -} - -int checkboard( void ) -{ - puts("Board: Adder"); -#if defined(CONFIG_MPC885_FAMILY) - puts("87x\n"); -#elif defined(CONFIG_MPC866_FAMILY) - puts("II\n"); -#endif - - return 0; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - -} -#endif diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds deleted file mode 100644 index 38567d1c6e..0000000000 --- a/board/adder/u-boot.lds +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by Yuli Barcohen <yuli@arabellasw.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} -ENTRY(_start) diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c index 7e1b16ac46..290dc1984a 100644 --- a/board/ait/cam_enc_4xx/cam_enc_4xx.c +++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c @@ -8,15 +8,15 @@ */ #include <common.h> +#include <cli.h> #include <errno.h> -#include <hush.h> #include <linux/mtd/nand.h> #include <nand.h> #include <miiphy.h> #include <netdev.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/nand_defs.h> +#include <asm/ti-common/davinci_nand.h> #include <asm/arch/davinci_misc.h> #ifdef CONFIG_DAVINCI_MMC #include <mmc.h> @@ -777,7 +777,7 @@ static void ait_menu_read_env(char *name) sprintf(output, "%s old: %s value: ", name, getenv(name)); memset(cbuf, 0, CONFIG_SYS_CBSIZE); - readret = readline_into_buffer(output, cbuf, 0); + readret = cli_readline_into_buffer(output, cbuf, 0); if (readret >= 0) { ret = setenv(name, cbuf); diff --git a/board/altera/common/sevenseg.c b/board/altera/common/sevenseg.c deleted file mode 100644 index 1f22c8524a..0000000000 --- a/board/altera/common/sevenseg.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> - * Stephan Linz <linz@li-pro.net> - * - * SPDX-License-Identifier: GPL-2.0+ - * - * common/sevenseg.c - * - * NIOS PIO based seven segment led support functions - */ - -#include <common.h> -#include <nios-io.h> - -#ifdef CONFIG_SEVENSEG - -#define SEVENDEG_MASK_DP ((SEVENSEG_DIGIT_DP << 8) | SEVENSEG_DIGIT_DP) - -#ifdef SEVENSEG_WRONLY /* emulate read access */ -#if (SEVENSEG_ACTIVE == 0) -static unsigned int sevenseg_portval = ~0; -#else -static unsigned int sevenseg_portval = 0; -#endif -#endif - -static int sevenseg_init_done = 0; - -static inline void __sevenseg_set_masked (unsigned int mask, int value) -{ - nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE; - -#ifdef SEVENSEG_WRONLY /* emulate read access */ - -#if (SEVENSEG_ACTIVE == 0) - if (value) - sevenseg_portval &= ~mask; - else - sevenseg_portval |= mask; -#else - if (value) - sevenseg_portval |= mask; - else - sevenseg_portval &= ~mask; -#endif - - piop->data = sevenseg_portval; - -#else /* !SEVENSEG_WRONLY */ - -#if (SEVENSEG_ACTIVE == 0) - if (value) - piop->data &= ~mask; - else - piop->data |= mask; -#else - if (value) - piop->data |= mask; - else - piop->data &= ~mask; -#endif - -#endif /* SEVENSEG_WRONLY */ -} - -static inline void __sevenseg_toggle_masked (unsigned int mask) -{ - nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE; - -#ifdef SEVENSEG_WRONLY /* emulate read access */ - - sevenseg_portval ^= mask; - piop->data = sevenseg_portval; - -#else /* !SEVENSEG_WRONLY */ - - piop->data ^= mask; - -#endif /* SEVENSEG_WRONLY */ -} - -static inline void __sevenseg_set (unsigned int value) -{ - nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE; - -#ifdef SEVENSEG_WRONLY /* emulate read access */ - -#if (SEVENSEG_ACTIVE == 0) - sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP) - | ((~value) & (~SEVENDEG_MASK_DP)); -#else - sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP) - | (value); -#endif - - piop->data = sevenseg_portval; - -#else /* !SEVENSEG_WRONLY */ - -#if (SEVENSEG_ACTIVE == 0) - piop->data = (piop->data & SEVENDEG_MASK_DP) - | ((~value) & (~SEVENDEG_MASK_DP)); -#else - piop->data = (piop->data & SEVENDEG_MASK_DP) - | (value); -#endif - -#endif /* SEVENSEG_WRONLY */ -} - -static inline void __sevenseg_init (void) -{ - nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE; - - __sevenseg_set(0); - -#ifndef SEVENSEG_WRONLY /* setup direction */ - - piop->direction |= mask; - -#endif /* SEVENSEG_WRONLY */ -} - - -void sevenseg_set(int value) -{ - unsigned char digits[] = { - SEVENSEG_DIGITS_0, - SEVENSEG_DIGITS_1, - SEVENSEG_DIGITS_2, - SEVENSEG_DIGITS_3, - SEVENSEG_DIGITS_4, - SEVENSEG_DIGITS_5, - SEVENSEG_DIGITS_6, - SEVENSEG_DIGITS_7, - SEVENSEG_DIGITS_8, - SEVENSEG_DIGITS_9, - SEVENSEG_DIGITS_A, - SEVENSEG_DIGITS_B, - SEVENSEG_DIGITS_C, - SEVENSEG_DIGITS_D, - SEVENSEG_DIGITS_E, - SEVENSEG_DIGITS_F - }; - - if (!sevenseg_init_done) { - __sevenseg_init(); - sevenseg_init_done++; - } - - switch (value & SEVENSEG_MASK_CTRL) { - - case SEVENSEG_RAW: - __sevenseg_set( ( - (digits[((value & SEVENSEG_MASK_VAL) >> 4)] << 8) | - digits[((value & SEVENSEG_MASK_VAL) & 0xf)] ) ); - return; - break; /* paranoia */ - - case SEVENSEG_OFF: - __sevenseg_set(0); - __sevenseg_set_masked(SEVENDEG_MASK_DP, 0); - return; - break; /* paranoia */ - - case SEVENSEG_SET_DPL: - __sevenseg_set_masked(SEVENSEG_DIGIT_DP, 1); - return; - break; /* paranoia */ - - case SEVENSEG_SET_DPH: - __sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 1); - return; - break; /* paranoia */ - - case SEVENSEG_RES_DPL: - __sevenseg_set_masked(SEVENSEG_DIGIT_DP, 0); - return; - break; /* paranoia */ - - case SEVENSEG_RES_DPH: - __sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 0); - return; - break; /* paranoia */ - - case SEVENSEG_TOG_DPL: - __sevenseg_toggle_masked(SEVENSEG_DIGIT_DP); - return; - break; /* paranoia */ - - case SEVENSEG_TOG_DPH: - __sevenseg_toggle_masked((SEVENSEG_DIGIT_DP << 8)); - return; - break; /* paranoia */ - - case SEVENSEG_LO: - case SEVENSEG_HI: - case SEVENSEG_STR: - default: - break; - } -} - -#endif /* CONFIG_SEVENSEG */ diff --git a/board/altera/common/sevenseg.h b/board/altera/common/sevenseg.h deleted file mode 100644 index 34348329ec..0000000000 --- a/board/altera/common/sevenseg.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> - * Stephan Linz <linz@li-pro.net> - * - * SPDX-License-Identifier: GPL-2.0+ - * - * common/sevenseg.h - * - * NIOS PIO based seven segment led support functions - */ - -#ifndef __DK1S10_SEVENSEG_H__ -#define __DK1S10_SEVENSEG_H__ - -#ifdef CONFIG_SEVENSEG - -/* - * 15 8 7 0 - * |-----------------------|--------| - * | controll value | value | - * ---------------------------------- - */ -#define SEVENSEG_RAW (int)(0) /* write out byte value (hex) */ -#define SEVENSEG_OFF (int)( 1 << 8) /* display switch off */ -#define SEVENSEG_SET_DPL (int)( 2 << 8) /* set dp low nibble */ -#define SEVENSEG_SET_DPH (int)( 3 << 8) /* set dp high nibble */ -#define SEVENSEG_RES_DPL (int)( 4 << 8) /* reset dp low nibble */ -#define SEVENSEG_RES_DPH (int)( 5 << 8) /* reset dp high nibble */ -#define SEVENSEG_TOG_DPL (int)( 6 << 8) /* toggle dp low nibble */ -#define SEVENSEG_TOG_DPH (int)( 7 << 8) /* toggle dp high nibble */ -#define SEVENSEG_LO (int)( 8 << 8) /* write out low nibble only */ -#define SEVENSEG_HI (int)( 9 << 8) /* write out high nibble only */ -#define SEVENSEG_STR (int)(10 << 8) /* write out a string */ - -#define SEVENSEG_MASK_VAL (0xff) /* only used by SEVENSEG_RAW */ -#define SEVENSEG_MASK_CTRL (~SEVENSEG_MASK_VAL) - -#ifdef SEVENSEG_DIGIT_HI_LO_EQUAL - -#define SEVENSEG_DIGITS_0 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F ) -#define SEVENSEG_DIGITS_1 ( SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C ) -#define SEVENSEG_DIGITS_2 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_3 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_4 ( SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_5 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_6 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_7 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C ) -#define SEVENSEG_DIGITS_8 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_9 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_A ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_B ( SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_C ( SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_D ( SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_E ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_F ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) - -#else /* !SEVENSEG_DIGIT_HI_LO_EQUAL */ -#error SEVENSEG: different pin asssignments not supported -#endif - -void sevenseg_set(int value); - -#endif /* CONFIG_SEVENSEG */ - -#endif /* __DK1S10_SEVENSEG_H__ */ diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile index 84690fe04d..aa362b3609 100644 --- a/board/altera/nios2-generic/Makefile +++ b/board/altera/nios2-generic/Makefile @@ -9,5 +9,4 @@ obj-y := nios2-generic.o obj-$(CONFIG_CMD_IDE) += ../common/cfide.o obj-$(CONFIG_EPLED) += ../common/epled.o -obj-$(CONFIG_SEVENSEG) += ../common/sevenseg.o obj-y += text_base.o diff --git a/board/altera/socfpga/iocsr_config.c b/board/altera/socfpga/iocsr_config.c new file mode 100644 index 0000000000..b4b5ff8972 --- /dev/null +++ b/board/altera/socfpga/iocsr_config.c @@ -0,0 +1,657 @@ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file is generated by Preloader Generator */ + +#include <iocsr_config.h> + +const unsigned long iocsr_scan_chain0_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00020080, + 0x08020000, + 0x08000000, + 0x00018020, + 0x00000000, + 0x00004000, + 0x00010040, + 0x04010000, + 0x04000000, + 0x00000010, + 0x00004010, + 0x00002000, + 0x00020000, + 0x02008000, + 0x02000000, + 0x00000008, + 0x00002008, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { + 0x000C0300, + 0x10040000, + 0x100000C0, + 0x00000040, + 0x00010040, + 0x00008000, + 0x00080000, + 0x18060000, + 0x18000000, + 0x00000060, + 0x00018060, + 0x00004000, + 0x00010040, + 0x10000000, + 0x04000000, + 0x00000010, + 0x00004010, + 0x00002000, + 0x06008020, + 0x02008000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x00004010, + 0x01004000, + 0x01000000, + 0x00003004, + 0x00001004, + 0x00000800, + 0x00000000, + 0x00000000, + 0x00800000, + 0x00000002, + 0x00002000, + 0x00000400, + 0x00000000, + 0x00401000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00600802, + 0x00000000, + 0x80200000, + 0x80000600, + 0x00000200, + 0x00000100, + 0x00300401, + 0xC0100400, + 0x40100000, + 0x40000300, + 0x000C0100, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { + 0x80040100, + 0x00000000, + 0x0FF00000, + 0x00000000, + 0x0C010040, + 0x00008000, + 0x18020080, + 0x00000000, + 0x08000000, + 0x00040020, + 0x06018060, + 0x00004000, + 0x0C010040, + 0x04010000, + 0x00000030, + 0x00000000, + 0x03004010, + 0x00002000, + 0x06008020, + 0x02008000, + 0x02000018, + 0x00006008, + 0x01802008, + 0x00001000, + 0x03004010, + 0x01004000, + 0x0100000C, + 0x00003004, + 0x00C01004, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[(( + CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { + 0x2C420D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000070, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x906808A2, + 0xA2834024, + 0x05141A00, + 0x808A20D0, + 0x34024906, + 0x01A00A28, + 0xA20D0000, + 0x24906808, + 0x00A28340, + 0xD000001A, + 0x06808A20, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000070, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x906808A2, + 0xA2834024, + 0x05141A00, + 0x808A20D0, + 0x34024906, + 0x01A00040, + 0xA20D0002, + 0x24906808, + 0x00A28340, + 0xD005141A, + 0x06808A20, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x000001C1, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC255F80, + 0xF1C71C71, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x04510680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC255F80, + 0xF1C71C71, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x8341D348, + 0x821A0124, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC255F80, + 0xF1C71C71, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x40120800, + 0x00000070, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC255F80, + 0xF1C71C71, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x001A1A1A, + 0x085506A0, + 0x0000E1D4, + 0x045506A0, + 0x0000E1D4, + 0x085506A0, + 0x8000E1D4, + 0x00000200, + 0x00000004, + 0x04000000, + 0x00000009, + 0x00002410, + 0x00000040, + 0x41000000, + 0x00002082, + 0x00000350, + 0x000000DA, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x022A8350, + 0x000070EA, + 0x86000000, + 0x08000004, + 0x00000000, + 0x00482000, + 0x21800000, + 0x00101061, + 0x021541A8, + 0x00003875, + 0x011541A8, + 0x00003875, + 0x021541A8, + 0x20003875, + 0x00000080, + 0x00000001, + 0x41000000, + 0x00000002, + 0x00FF0904, + 0x00000000, + 0x90400000, + 0x00000820, + 0xC0000001, + 0x38D612AF, + 0x86F8E38E, + 0x0A0A78B4, + 0x000D020A, + 0x00006800, + 0x028A4320, + 0xEC2CB23D, + 0x8F5D1451, + 0xA47A88A2, + 0x0001A0E9, + 0x00410D00, + 0x40000068, + 0x3D000003, + 0x51EC2CB2, + 0xA28F5D14, + 0xE9A47A88, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000540, + 0x000003A8, + 0x08AA0D40, + 0x8001C3A8, + 0x0000007F, + 0x00000000, + 0x00004060, + 0xE1208000, + 0x0000001F, + 0x00004100, +}; diff --git a/board/altera/socfpga/iocsr_config.h b/board/altera/socfpga/iocsr_config.h new file mode 100644 index 0000000000..490f109e4b --- /dev/null +++ b/board/altera/socfpga/iocsr_config.h @@ -0,0 +1,17 @@ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file is generated by Preloader Generator */ + +#ifndef _PRELOADER_IOCSR_CONFIG_H_ +#define _PRELOADER_IOCSR_CONFIG_H_ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764) +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955) +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) + +#endif /*_PRELOADER_IOCSR_CONFIG_H_*/ diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index a960eb6002..f36656505f 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -12,17 +12,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_DISPLAY_CPUINFO) -/* - * Print CPU information - */ -int print_cpuinfo(void) -{ - puts("CPU : Altera SOCFPGA Platform\n"); - return 0; -} -#endif - /* * Print Board information */ @@ -49,18 +38,6 @@ int board_init(void) return 0; } -int misc_init_r(void) -{ - return 0; -} - -#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) -int overwrite_console(void) -{ - return 0; -} -#endif - /* * DesignWare Ethernet initialization */ diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c index dc78b73731..c1724bf034 100644 --- a/board/amcc/yucca/cmd_yucca.c +++ b/board/amcc/yucca/cmd_yucca.c @@ -8,6 +8,7 @@ */ #include <common.h> +#include <cli.h> #include <command.h> #include "yucca.h" #include <i2c.h> @@ -51,7 +52,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, do { printf("enter sys clock frequency 33 or 66 MHz or quit to abort\n"); - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (strcmp(console_buffer, "quit") == 0) return 0; @@ -74,7 +75,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, printf("enter cpu clock frequency 400, 500, 533 MHz or quit to abort\n"); #endif } - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (strcmp(console_buffer, "quit") == 0) return 0; @@ -118,7 +119,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, printf("enter plb clock frequency 133, 166 MHz or quit to abort\n"); #endif - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (strcmp(console_buffer, "quit") == 0) return 0; @@ -142,7 +143,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, do { printf("enter Pci-X clock frequency 33, 66, 100 or 133 MHz or quit to abort\n"); - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (strcmp(console_buffer, "quit") == 0) return 0; @@ -163,13 +164,13 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, printf("Pci-X clk = %s MHz\n", pcixClock); do { - printf("\npress [y] to write I2C bootstrap \n"); - printf("or [n] to abort. \n"); - printf("Don't forget to set board switches \n"); - printf("according to your choice before re-starting \n"); - printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n"); + printf("\npress [y] to write I2C bootstrap\n"); + printf("or [n] to abort.\n"); + printf("Don't forget to set board switches\n"); + printf("according to your choice before re-starting\n"); + printf("(refer to 440spe_uboot_kit_um_1_01.pdf)\n"); - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (strcmp(console_buffer, "n") == 0) return 0; diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 2ec3bc9835..58973185ec 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -11,6 +11,7 @@ #include <netdev.h> #include <asm/io.h> #include <linux/compiler.h> +#include <asm/semihosting.h> DECLARE_GLOBAL_DATA_PTR; @@ -31,11 +32,6 @@ int dram_init(void) return 0; } -int timer_init(void) -{ - return 0; -} - /* * Board specific reset that is system reset. */ @@ -43,6 +39,101 @@ void reset_cpu(ulong addr) { } +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_SEMIHOSTING + /* + * Please refer to doc/README.semihosting for a more complete + * description. + * + * We require that the board include file defines these env variables: + * - kernel_name + * - kernel_addr_r + * - initrd_name + * - initrd_addr_r + * - fdt_name + * - fdt_addr_r + * + * For the "fdt chosen" startup macro, this code will then define: + * - initrd_end (based on initrd_addr_r plus actual initrd_size) + * + * We will then load the kernel, initrd, and fdt into the specified + * locations in memory in a similar way that the ATF fastmodel code + * uses semihosting calls to load other boot stages and u-boot itself. + */ + + /* Env variable strings */ + char *kernel_name = getenv("kernel_name"); + char *kernel_addr_str = getenv("kernel_addr_r"); + char *initrd_name = getenv("initrd_name"); + char *initrd_addr_str = getenv("initrd_addr_r"); + char *fdt_name = getenv("fdt_name"); + char *fdt_addr_str = getenv("fdt_addr_r"); + char initrd_end_str[64]; + + /* Actual addresses converted from env variables */ + void *kernel_addr_r; + void *initrd_addr_r; + void *fdt_addr_r; + + /* Actual initrd base and size */ + unsigned long initrd_base; + unsigned long initrd_size; + + /* Space available */ + int avail; + + /* Make sure the environment variables needed are set */ + if (!(kernel_addr_str && initrd_addr_str && fdt_addr_str)) { + printf("%s: Define {kernel/initrd/fdt}_addr_r\n", __func__); + return -1; + } + if (!(kernel_name && initrd_name && fdt_name)) { + printf("%s: Define {kernel/initrd/fdt}_name\n", __func__); + return -1; + } + + /* Get exact initrd_size */ + initrd_size = smh_len(initrd_name); + if (initrd_size == -1) { + printf("%s: Can't get file size for \'%s\'\n", __func__, + initrd_name); + return -1; + } + + /* Set initrd_end */ + initrd_base = simple_strtoul(initrd_addr_str, NULL, 16); + initrd_addr_r = (void *)initrd_base; + sprintf(initrd_end_str, "0x%lx", initrd_base + initrd_size - 1); + setenv("initrd_end", initrd_end_str); + + /* Load kernel to memory */ + fdt_addr_r = (void *)simple_strtoul(fdt_addr_str, NULL, 16); + kernel_addr_r = (void *)simple_strtoul(kernel_addr_str, NULL, 16); + + /* + * The kernel must be lower in memory than fdt and loading the + * kernel must not trample the fdt or vice versa. + */ + avail = fdt_addr_r - kernel_addr_r; + if (avail < 0) { + printf("%s: fdt must be after kernel\n", __func__); + return -1; + } + smh_load(kernel_name, kernel_addr_r, avail, 1); + + /* Load fdt to memory */ + smh_load(fdt_name, fdt_addr_r, 0x20000, 1); + + /* Load initrd to memory */ + smh_load(initrd_name, initrd_addr_r, initrd_size, 1); + +#endif /* CONFIG_SEMIHOSTING */ + return 0; +} +#endif /* CONFIG_BOARD_LATE_INIT */ + /* * Board specific ethernet initialization routine. */ diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c index 1d044d96a5..d1110dfd6e 100644 --- a/board/astro/mcf5373l/fpga.c +++ b/board/astro/mcf5373l/fpga.c @@ -100,7 +100,7 @@ int altera_done_fn(int cookie) * writing the complete buffer in one function is much faster, * then calling it for every bit */ -int altera_write_fn(void *buf, size_t len, int flush, int cookie) +int altera_write_fn(const void *buf, size_t len, int flush, int cookie) { size_t bytecount = 0; gpio_t *gpiop = (gpio_t *)MMAP_GPIO; diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c index daba32c9dc..7ec7cb378f 100644 --- a/board/astro/mcf5373l/mcf5373l.c +++ b/board/astro/mcf5373l/mcf5373l.c @@ -79,7 +79,7 @@ phys_size_t initdram(int board_type) * (Do not rely on the SDCS register(s) being set to 0x00000000 * during reset as stated in the data sheet.) */ - return get_ram_size((unsigned long *)CONFIG_SYS_SDRAM_BASE, + return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000 - CONFIG_SYS_SDRAM_BASE); } diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 3e8f062f89..a301d72e8c 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -133,20 +133,20 @@ static void at91sam9261ek_dm9000_hw_init(void) #ifdef CONFIG_LCD vidinfo_t panel_info = { - vl_col: 240, - vl_row: 320, - vl_clk: 4965000, - vl_sync: ATMEL_LCDC_INVLINE_INVERTED | - ATMEL_LCDC_INVFRAME_INVERTED, - vl_bpix: 3, - vl_tft: 1, - vl_hsync_len: 5, - vl_left_margin: 1, - vl_right_margin:33, - vl_vsync_len: 1, - vl_upper_margin:1, - vl_lower_margin:0, - mmio: ATMEL_BASE_LCDC, + .vl_col = 240, + .vl_row = 320, + .vl_clk = 4965000, + .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + .vl_bpix = 3, + .vl_tft = 1, + .vl_hsync_len = 5, + .vl_left_margin = 1, + .vl_right_margin = 33, + .vl_vsync_len = 1, + .vl_upper_margin = 1, + .vl_lower_margin = 0, + .mmio = ATMEL_BASE_LCDC, }; void lcd_enable(void) diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index db29879801..927adb0d38 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -111,20 +111,20 @@ static void at91sam9263ek_macb_hw_init(void) #ifdef CONFIG_LCD vidinfo_t panel_info = { - vl_col: 240, - vl_row: 320, - vl_clk: 4965000, - vl_sync: ATMEL_LCDC_INVLINE_INVERTED | - ATMEL_LCDC_INVFRAME_INVERTED, - vl_bpix: 3, - vl_tft: 1, - vl_hsync_len: 5, - vl_left_margin: 1, - vl_right_margin:33, - vl_vsync_len: 1, - vl_upper_margin:1, - vl_lower_margin:0, - mmio: ATMEL_BASE_LCDC, + .vl_col = 240, + .vl_row = 320, + .vl_clk = 4965000, + .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + .vl_bpix = 3, + .vl_tft = 1, + .vl_hsync_len = 5, + .vl_left_margin = 1, + .vl_right_margin = 33, + .vl_vsync_len = 1, + .vl_upper_margin = 1, + .vl_lower_margin = 0, + .mmio = ATMEL_BASE_LCDC, }; void lcd_enable(void) diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index b7e2efd2fc..b807ef9a42 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -16,6 +16,7 @@ #include <asm/arch/clk.h> #include <lcd.h> #include <atmel_lcdc.h> +#include <atmel_mci.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) #include <net.h> #endif @@ -120,20 +121,20 @@ static void at91sam9m10g45ek_macb_hw_init(void) #ifdef CONFIG_LCD vidinfo_t panel_info = { - vl_col: 480, - vl_row: 272, - vl_clk: 9000000, - vl_sync: ATMEL_LCDC_INVLINE_NORMAL | - ATMEL_LCDC_INVFRAME_NORMAL, - vl_bpix: 3, - vl_tft: 1, - vl_hsync_len: 45, - vl_left_margin: 1, - vl_right_margin:1, - vl_vsync_len: 1, - vl_upper_margin:40, - vl_lower_margin:1, - mmio : ATMEL_BASE_LCDC, + .vl_col = 480, + .vl_row = 272, + .vl_clk = 9000000, + .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | + ATMEL_LCDC_INVFRAME_NORMAL, + .vl_bpix = 3, + .vl_tft = 1, + .vl_hsync_len = 45, + .vl_left_margin = 1, + .vl_right_margin = 1, + .vl_vsync_len = 1, + .vl_upper_margin = 40, + .vl_lower_margin = 1, + .mmio = ATMEL_BASE_LCDC, }; @@ -217,6 +218,15 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif +#ifdef CONFIG_GENERIC_ATMEL_MCI +int board_mmc_init(bd_t *bis) +{ + at91_mci_hw_init(); + + return atmel_mci_init((void *)ATMEL_BASE_MCI0); +} +#endif + int board_early_init_f(void) { at91_seriald_hw_init(); diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index c700a9076b..56ca1d4f7e 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -78,20 +78,20 @@ static void at91sam9rlek_nand_hw_init(void) #ifdef CONFIG_LCD vidinfo_t panel_info = { - vl_col: 240, - vl_row: 320, - vl_clk: 4965000, - vl_sync: ATMEL_LCDC_INVLINE_INVERTED | - ATMEL_LCDC_INVFRAME_INVERTED, - vl_bpix: 3, - vl_tft: 1, - vl_hsync_len: 5, - vl_left_margin: 1, - vl_right_margin:33, - vl_vsync_len: 1, - vl_upper_margin:1, - vl_lower_margin:0, - mmio: ATMEL_BASE_LCDC, + .vl_col = 240, + .vl_row = 320, + .vl_clk = 4965000, + .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + .vl_bpix = 3, + .vl_tft = 1, + .vl_hsync_len = 5, + .vl_left_margin = 1, + .vl_right_margin = 33, + .vl_vsync_len = 1, + .vl_upper_margin = 1, + .vl_lower_margin = 0, + .mmio = ATMEL_BASE_LCDC, }; void lcd_enable(void) diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c index 39f2dc6475..92ed4e81d3 100644 --- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -17,6 +17,9 @@ #include <atmel_mci.h> #include <net.h> #include <netdev.h> +#include <spl.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/at91_wdt.h> DECLARE_GLOBAL_DATA_PTR; @@ -128,3 +131,87 @@ int board_mmc_init(bd_t *bis) return 0; } #endif + +/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ +#ifdef CONFIG_SYS_USE_MMC + sama5d3_xplained_mci0_hw_init(); +#elif CONFIG_SYS_USE_NANDFLASH + sama5d3_xplained_nand_hw_init(); +#endif +} + +static void ddr2_conf(struct atmel_mpddr *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_ENRDM_ON | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_NDQS_DISABLED | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + /* + * As the DDR2-SDRAm device requires a refresh time is 7.8125us + * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks + */ + ddr2->rtr = 0x411; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddr ddr2; + + ddr2_conf(&ddr2); + + /* enable MPDDR clock */ + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + writel(0x4, &pmc->scer); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_DDRCS, &ddr2); +} + +void at91_pmc_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 tmp; + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(43) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + writel(0x3 << 8, &pmc->pllicpr); + + tmp = AT91_PMC_MCKR_MDIV_4 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/board/cirrus/edb93xx/Makefile b/board/cirrus/edb93xx/Makefile new file mode 100644 index 0000000000..d03c498478 --- /dev/null +++ b/board/cirrus/edb93xx/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2013 +# Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru> +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de. +# +# * SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := edb93xx.o diff --git a/board/cirrus/edb93xx/edb93xx.c b/board/cirrus/edb93xx/edb93xx.c new file mode 100644 index 0000000000..8963d3a582 --- /dev/null +++ b/board/cirrus/edb93xx/edb93xx.c @@ -0,0 +1,382 @@ +/* + * Board initialization for EP93xx + * + * Copyright (C) 2013 + * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru> + * + * Copyright (C) 2009 + * Matthias Kaehlcke <matthias <at> kaehlcke.net> + * + * (C) Copyright 2002 2003 + * Network Audio Technologies, Inc. <www.netaudiotech.com> + * Adam Bezanson <bezanson <at> netaudiotech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/ep93xx.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * usb_div: 4, nbyp2: 1, pll2_en: 1 + * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000, + * pll2_x2: 384000000.000000, pll2_out: 192000000.000000 + */ +#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ + 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ + 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ + 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \ + SYSCON_CLKSET2_PLL2_EN | \ + SYSCON_CLKSET2_NBYP2 | \ + 3 << SYSCON_CLKSET2_USB_DIV_SHIFT) + +#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \ + SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \ + 1 << SMC_BCR_MW_SHIFT) + +/* delay execution before timers are initialized */ +static inline void early_udelay(uint32_t usecs) +{ + /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */ + register uint32_t loops = (usecs * 1000) / 20; + + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b" : "=r" (loops) : "0" (loops)); +} + +#ifndef CONFIG_EP93XX_NO_FLASH_CFG +static void flash_cfg(void) +{ + struct smc_regs *smc = (struct smc_regs *)SMC_BASE; + + writel(SMC_BCR6_VALUE, &smc->bcr6); +} +#else +#define flash_cfg() +#endif + +int board_init(void) +{ + /* + * Setup PLL2, PPL1 has been set during lowlevel init + */ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + writel(CLKSET2_VAL, &syscon->clkset2); + + /* + * the user's guide recommends to wait at least 1 ms for PLL2 to + * stabilize + */ + early_udelay(1000); + + /* Go to Async mode */ + __asm__ volatile ("mrc p15, 0, r0, c1, c0, 0"); + __asm__ volatile ("orr r0, r0, #0xc0000000"); + __asm__ volatile ("mcr p15, 0, r0, c1, c0, 0"); + + icache_enable(); + +#ifdef USE_920T_MMU + dcache_enable(); +#endif + + /* Machine number, as defined in linux/arch/arm/tools/mach-types */ + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* We have a console */ + gd->have_console = 1; + + enable_interrupts(); + + flash_cfg(); + + green_led_on(); + red_led_off(); + + return 0; +} + +int board_early_init_f(void) +{ + /* + * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of + * 14.7456/2 MHz + */ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt); + return 0; +} + +int board_eth_init(bd_t *bd) +{ + return ep93xx_eth_initialize(0, MAC_BASE); +} + +static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned dram_bank_cnt, + unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS]) +{ + if (dram_bank_cnt == 1) { + dram_bank_base[0] = PHYS_SDRAM_1; + } else { + /* Table lookup for holes in address space. Maximum memory + * for the single SDCS may be up to 256Mb. We start scanning + * banks from 1Mb, so it could be up to 128 banks theoretically. + * We need at maximum 7 bits for the loockup, 8 slots is + * enough for the worst case. + */ + unsigned tbl[8]; + unsigned i = dram_bank_cnt / 2; + unsigned j = 0x00100000; /* 1 Mb */ + unsigned *ptbl = tbl; + do { + while (!(dram_addr_mask & j)) { + j <<= 1; + } + *ptbl++ = j; + j <<= 1; + i >>= 1; + } while (i != 0); + + for (i = dram_bank_cnt, j = 0; + (i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) { + unsigned addr = PHYS_SDRAM_1; + unsigned k; + unsigned bit; + + for (k = 0, bit = 1; k < 8; k++, bit <<= 1) { + if (bit & j) + addr |= tbl[k]; + } + + dram_bank_base[j] = addr; + } + } +} + +/* called in board_init_f (before relocation) */ +static unsigned dram_init_banksize_int(int print) +{ + /* + * Collect information of banks that has been filled during lowlevel + * initialization + */ + unsigned i; + unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS]; + unsigned dram_total = 0; + unsigned dram_bank_size = *(unsigned *) + (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE); + unsigned dram_addr_mask = *(unsigned *) + (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK); + unsigned dram_bank_cnt = *(unsigned *) + (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT); + + dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt, dram_bank_base); + + for (i = 0; i < dram_bank_cnt; i++) { + gd->bd->bi_dram[i].start = dram_bank_base[i]; + gd->bd->bi_dram[i].size = dram_bank_size; + dram_total += dram_bank_size; + } + for (; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = 0; + gd->bd->bi_dram[i].size = 0; + } + + if (print) { + printf("DRAM mask: %08x\n", dram_addr_mask); + printf("DRAM total %u banks:\n", dram_bank_cnt); + printf("bank base-address size\n"); + + if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) { + printf("WARNING! UBoot was configured for %u banks,\n" + "but %u has been found. " + "Supressing extra memory banks\n", + CONFIG_NR_DRAM_BANKS, dram_bank_cnt); + dram_bank_cnt = CONFIG_NR_DRAM_BANKS; + } + + for (i = 0; i < dram_bank_cnt; i++) { + printf(" %u %08x %08x\n", + i, dram_bank_base[i], dram_bank_size); + } + printf(" ------------------------------------------\n" + "Total %9d\n\n", + dram_total); + } + + return dram_total; +} + +void dram_init_banksize(void) +{ + dram_init_banksize_int(0); +} + +/* called in board_init_f (before relocation) */ +int dram_init(void) +{ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + unsigned sec_id = readl(SECURITY_EXTENSIONID); + unsigned chip_id = readl(&syscon->chipid); + + printf("CPU: Cirrus Logic "); + switch (sec_id & 0x000001FE) { + case 0x00000008: + printf("EP9301"); + break; + case 0x00000004: + printf("EP9307"); + break; + case 0x00000002: + printf("EP931x"); + break; + case 0x00000000: + printf("EP9315"); + break; + default: + printf("<unknown>"); + break; + } + + printf(" - Rev. "); + switch (chip_id & 0xF0000000) { + case 0x00000000: + printf("A"); + break; + case 0x10000000: + printf("B"); + break; + case 0x20000000: + printf("C"); + break; + case 0x30000000: + printf("D0"); + break; + case 0x40000000: + printf("D1"); + break; + case 0x50000000: + printf("E0"); + break; + case 0x60000000: + printf("E1"); + break; + case 0x70000000: + printf("E2"); + break; + default: + printf("?"); + break; + } + printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id); + + gd->ram_size = dram_init_banksize_int(1); + return 0; +} + + +#ifdef CONFIG_EP93XX_SPI +#include <spi.h> + +/* + * EGIO0-EGIPO7 -> port A + * EGIO8-EGIP15 -> port B + */ + +static void ep93xx_set_epgio(unsigned num) +{ + struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE; + if (num < 8) + writel(readl(®s->padr) | (1<<num), ®s->padr); + else + writel(readl(®s->pbdr) | (1<<(num-8)), ®s->pbdr); +} + +static void ep93xx_clear_epgio(unsigned num) +{ + struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE; + if (num < 8) + writel(readl(®s->padr) & (~(1<<num)), ®s->padr); + else + writel(readl(®s->pbdr) & (~(1<<(num-8))), ®s->pbdr); +} + +static void ep93xx_dir_epgio_out(unsigned num) +{ + struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE; + if (num < 8) + writel(readl(®s->paddr) | (1<<num), ®s->paddr); + else + writel(readl(®s->pbddr) | (1<<(num-8)), ®s->pbddr); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + if (bus == 0 && cs < 16) + return 1; + + return 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + ep93xx_clear_epgio(slave->cs); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + ep93xx_set_epgio(slave->cs); +} + +#ifdef CONFIG_MMC_SPI +#include <mmc.h> + +#ifndef CONFIG_MMC_SPI_CS_EPGIO +# define CONFIG_MMC_SPI_CS_EPGIO 4 +#endif + +#ifndef CONFIG_MMC_SPI_SPEED +# define CONFIG_MMC_SPI_SPEED 25000000 +#endif + +#ifndef CONFIG_MMC_SPI_MODE +# define CONFIG_MMC_SPI_MODE SPI_MODE_0 +#endif + +int board_mmc_init(bd_t *bis) +{ + struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE; + + ep93xx_set_epgio(CONFIG_MMC_SPI_CS_EPGIO); + ep93xx_dir_epgio_out(CONFIG_MMC_SPI_CS_EPGIO); + +#ifdef CONFIG_MMC_SPI_POWER_EGPIO + ep93xx_dir_epgio_out(CONFIG_MMC_SPI_POWER_EGPIO); + ep93xx_set_epgio(CONFIG_MMC_SPI_POWER_EGPIO); +#elif defined(CONFIG_MMC_SPI_NPOWER_EGPIO) + ep93xx_dir_epgio_out(CONFIG_MMC_SPI_NPOWER_EGPIO); + ep93xx_clear_epgio(CONFIG_MMC_SPI_NPOWER_EGPIO); +#endif + struct mmc *mmc = mmc_spi_init(0, CONFIG_MMC_SPI_CS_EPGIO, + CONFIG_MMC_SPI_SPEED, CONFIG_MMC_SPI_MODE); + + if (!mmc) { + printf("Failed to create MMC Device\n"); + return 1; + } + mmc_init(mmc); + return 0; +} + + +#endif /* CONFIG_MMC_SPI */ +#endif /* CONFIG_EP93XX_SPI */ diff --git a/board/cirrus/edb93xx/u-boot.lds b/board/cirrus/edb93xx/u-boot.lds new file mode 100644 index 0000000000..b0d892a59f --- /dev/null +++ b/board/cirrus/edb93xx/u-boot.lds @@ -0,0 +1,115 @@ +/* + * + * Copyright (C) 2013 + * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru> + * + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : { + *(.__image_copy_start) + arch/arm/cpu/arm920t/start.o (.text*) + . = 0x1000; + + LONG(0x53555243) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + .end : + { + *(.__end) + } + + _image_binary_end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + .dynsym _image_binary_end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu.hash : { *(.gnu.hash) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } + .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) } +} diff --git a/board/compulab/cm_t335/u-boot.lds b/board/compulab/cm_t335/u-boot.lds index c8ab716cea..627583668a 100644 --- a/board/compulab/cm_t335/u-boot.lds +++ b/board/compulab/cm_t335/u-boot.lds @@ -62,6 +62,8 @@ SECTIONS *(.__rel_dyn_end) } + .hash : { *(.hash*) } + .end : { *(.__end) @@ -99,8 +101,6 @@ SECTIONS } .dynsym _image_binary_end : { *(.dynsym) } - .hash : { *(.hash) } - .got.plt : { *(.got.plt) } .dynbss : { *(.dynbss) } .dynstr : { *(.dynstr*) } .dynamic : { *(.dynamic*) } diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index 00bcf41bb3..0944903ec8 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -54,12 +54,12 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = { }; static u32 gpmc_nand_config[GPMC_MAX_REG] = { - SMNAND_GPMC_CONFIG1, - SMNAND_GPMC_CONFIG2, - SMNAND_GPMC_CONFIG3, - SMNAND_GPMC_CONFIG4, - SMNAND_GPMC_CONFIG5, - SMNAND_GPMC_CONFIG6, + M_NAND_GPMC_CONFIG1, + M_NAND_GPMC_CONFIG2, + M_NAND_GPMC_CONFIG3, + M_NAND_GPMC_CONFIG4, + M_NAND_GPMC_CONFIG5, + M_NAND_GPMC_CONFIG6, 0, }; diff --git a/board/cray/L1/Makefile b/board/cray/L1/Makefile index 55402981fd..716a5a316b 100644 --- a/board/cray/L1/Makefile +++ b/board/cray/L1/Makefile @@ -15,13 +15,9 @@ quiet_cmd_awk = AWK $@ $(obj)/bootscript.c: $(obj)/bootscript.image $(src)/x2c.awk $(call cmd,awk) -quiet_cmd_mkimage = MKIMAGE $@ -cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ - $(if $(KBUILD_VERBOSE:1=), >/dev/null) - MKIMAGEFLAGS_bootscript.image := -A ppc -O linux -T script -C none \ -a 0 -e 0 -n bootscript $(obj)/bootscript.image: $(src)/bootscript.hush $(call cmd,mkimage) -clean-files := bootscript.c bootscript.image
\ No newline at end of file +clean-files := bootscript.c bootscript.image diff --git a/board/davinci/da8xxevm/da830evm.c b/board/davinci/da8xxevm/da830evm.c index 4f5c780e54..c40587ff09 100644 --- a/board/davinci/da8xxevm/da830evm.c +++ b/board/davinci/da8xxevm/da830evm.c @@ -25,12 +25,11 @@ #include <net.h> #include <netdev.h> #include <asm/arch/hardware.h> -#include <asm/arch/emif_defs.h> #include <asm/arch/emac_defs.h> #include <asm/arch/pinmux_defs.h> #include <asm/io.h> #include <nand.h> -#include <asm/arch/nand_defs.h> +#include <asm/ti-common/davinci_nand.h> #include <asm/arch/davinci_misc.h> #ifdef CONFIG_DAVINCI_MMC diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 85b483096b..b9ca38e929 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -16,7 +16,7 @@ #include <spi.h> #include <spi_flash.h> #include <asm/arch/hardware.h> -#include <asm/arch/emif_defs.h> +#include <asm/ti-common/davinci_nand.h> #include <asm/arch/emac_defs.h> #include <asm/arch/pinmux_defs.h> #include <asm/io.h> diff --git a/board/davinci/dm355evm/dm355evm.c b/board/davinci/dm355evm/dm355evm.c index 10422b226b..e5a958f7e0 100644 --- a/board/davinci/dm355evm/dm355evm.c +++ b/board/davinci/dm355evm/dm355evm.c @@ -8,8 +8,7 @@ #include <nand.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/emif_defs.h> -#include <asm/arch/nand_defs.h> +#include <asm/ti-common/davinci_nand.h> #include <asm/arch/davinci_misc.h> #include <net.h> #include <netdev.h> diff --git a/board/davinci/dm355leopard/dm355leopard.c b/board/davinci/dm355leopard/dm355leopard.c index 534184329c..53902f996c 100644 --- a/board/davinci/dm355leopard/dm355leopard.c +++ b/board/davinci/dm355leopard/dm355leopard.c @@ -9,7 +9,7 @@ #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/gpio.h> -#include <asm/arch/nand_defs.h> +#include <asm/ti-common/davinci_nand.h> #include <asm/arch/davinci_misc.h> #include <net.h> #include <netdev.h> diff --git a/board/davinci/dm365evm/dm365evm.c b/board/davinci/dm365evm/dm365evm.c index ceffd4d603..24bec56d56 100644 --- a/board/davinci/dm365evm/dm365evm.c +++ b/board/davinci/dm365evm/dm365evm.c @@ -8,8 +8,7 @@ #include <nand.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/emif_defs.h> -#include <asm/arch/nand_defs.h> +#include <asm/ti-common/davinci_nand.h> #include <asm/arch/gpio.h> #include <netdev.h> #include <asm/arch/davinci_misc.h> diff --git a/board/davinci/dm6467evm/dm6467evm.c b/board/davinci/dm6467evm/dm6467evm.c index 469c9bac4b..e51cc9e638 100644 --- a/board/davinci/dm6467evm/dm6467evm.c +++ b/board/davinci/dm6467evm/dm6467evm.c @@ -8,7 +8,8 @@ #include <netdev.h> #include <asm/io.h> #include <nand.h> -#include <asm/arch/nand_defs.h> +#include <asm/arch/hardware.h> +#include <asm/ti-common/davinci_nand.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c index c4444c7c7f..66804d75bd 100644 --- a/board/davinci/ea20/ea20.c +++ b/board/davinci/ea20/ea20.c @@ -19,7 +19,7 @@ #include <net.h> #include <netdev.h> #include <asm/arch/hardware.h> -#include <asm/arch/emif_defs.h> +#include <asm/ti-common/davinci_nand.h> #include <asm/arch/emac_defs.h> #include <asm/io.h> #include <asm/arch/davinci_misc.h> diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c index aa04041246..f5c3258de5 100644 --- a/board/davinci/sonata/sonata.c +++ b/board/davinci/sonata/sonata.c @@ -14,7 +14,7 @@ #include <common.h> #include <nand.h> -#include <asm/arch/nand_defs.h> +#include <asm/ti-common/davinci_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/davinci_misc.h> diff --git a/board/eltec/elppc/misc.c b/board/eltec/elppc/misc.c index d80eaba2d0..2acf80047f 100644 --- a/board/eltec/elppc/misc.c +++ b/board/eltec/elppc/misc.c @@ -7,6 +7,7 @@ /* includes */ #include <common.h> +#include <cli.h> #include <linux/ctype.h> #include <pci.h> #include <net.h> @@ -113,7 +114,7 @@ int misc_init_r (void) printf ("Press key:\n <c> to copy current revision info to nvram.\n"); printf (" <r> to reenter revision info.\n"); printf ("=> "); - if (0 != readline (NULL)) { + if (0 != cli_readline(NULL)) { switch ((char) toupper (console_buffer[0])) { case 'C': copyNv = 1; @@ -130,7 +131,7 @@ int misc_init_r (void) memcpy (buf, &eerev.revision[0][0], 14); /* save all revision info */ printf ("Enter revision number (0-9): %c ", eerev.revision[0][0]); - if (0 != readline (NULL)) { + if (0 != cli_readline(NULL)) { eerev.revision[0][0] = (char) toupper (console_buffer[0]); memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */ @@ -138,14 +139,14 @@ int misc_init_r (void) printf ("Enter revision character (A-Z): %c ", eerev.revision[0][1]); - if (1 == readline (NULL)) { + if (1 == cli_readline(NULL)) { eerev.revision[0][1] = (char) toupper (console_buffer[0]); } printf ("Enter board name (V-XXXX-XXXX): %s ", (char *) &eerev.board); - if (11 == readline (NULL)) { + if (11 == cli_readline(NULL)) { for (i = 0; i < 11; i++) eerev.board[i] = (char) toupper (console_buffer[i]); @@ -153,14 +154,14 @@ int misc_init_r (void) } printf ("Enter serial number: %s ", (char *) &eerev.serial); - if (6 == readline (NULL)) { + if (6 == cli_readline(NULL)) { for (i = 0; i < 6; i++) eerev.serial[i] = console_buffer[i]; eerev.serial[6] = '\0'; } printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", eerev.etheraddr[0], eerev.etheraddr[1], eerev.etheraddr[2], eerev.etheraddr[3], eerev.etheraddr[4], eerev.etheraddr[5]); - if (12 == readline (NULL)) { + if (12 == cli_readline(NULL)) { for (i = 0; i < 12; i += 2) eerev.etheraddr[i >> 1] = (char) (16 * @@ -175,7 +176,7 @@ int misc_init_r (void) l = strlen ((char *) &eerev.text); printf ("Add to text section (max 64 chr): %s ", (char *) &eerev.text); - if (0 != readline (NULL)) { + if (0 != cli_readline(NULL)) { for (i = l; i < 63; i++) eerev.text[i] = console_buffer[i - l]; eerev.text[63] = '\0'; diff --git a/board/eltec/mhpc/mhpc.c b/board/eltec/mhpc/mhpc.c index f3f564ffe4..5781b2a54f 100644 --- a/board/eltec/mhpc/mhpc.c +++ b/board/eltec/mhpc/mhpc.c @@ -14,6 +14,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <cli.h> #include <linux/ctype.h> #include <commproc.h> #include "mpc8xx.h" @@ -146,21 +147,21 @@ int misc_init_r (void) if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) { printf ("Enter revision number (0-9): %c ", mhpcRevInfo.revision[0]); - if (0 != readline (NULL)) { + if (0 != cli_readline(NULL)) { mhpcRevInfo.revision[0] = (char) toupper (console_buffer[0]); } printf ("Enter revision character (A-Z): %c ", mhpcRevInfo.revision[1]); - if (1 == readline (NULL)) { + if (1 == cli_readline(NULL)) { mhpcRevInfo.revision[1] = (char) toupper (console_buffer[0]); } printf ("Enter board name (V-XXXX-XXXX): %s ", (char *) &mhpcRevInfo.board); - if (11 == readline (NULL)) { + if (11 == cli_readline(NULL)) { for (i = 0; i < 11; i++) { mhpcRevInfo.board[i] = (char) toupper (console_buffer[i]); @@ -177,7 +178,7 @@ int misc_init_r (void) do { printf ("\nEnter sensor number (0-255): %d ", (int) mhpcRevInfo.sensor); - if (0 != readline (NULL)) { + if (0 != cli_readline(NULL)) { mhpcRevInfo.sensor = (unsigned char) simple_strtoul (console_buffer, NULL, @@ -187,7 +188,7 @@ int misc_init_r (void) printf ("Enter serial number: %s ", (char *) &mhpcRevInfo.serial); - if (6 == readline (NULL)) { + if (6 == cli_readline(NULL)) { for (i = 0; i < 6; i++) { mhpcRevInfo.serial[i] = console_buffer[i]; } @@ -195,7 +196,7 @@ int misc_init_r (void) } printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]); - if (12 == readline (NULL)) { + if (12 == cli_readline(NULL)) { for (i = 0; i < 12; i += 2) { mhpcRevInfo.etheraddr[i >> 1] = (char) (16 * diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c index 39efe20bfd..53b8362147 100644 --- a/board/enbw/enbw_cmc/enbw_cmc.c +++ b/board/enbw/enbw_cmc/enbw_cmc.c @@ -29,7 +29,7 @@ #include <asm/io.h> #include <asm/arch/da850_lowlevel.h> #include <asm/arch/davinci_misc.h> -#include <asm/arch/emif_defs.h> +#include <asm/ti-common/davinci_nand.h> #include <asm/arch/emac_defs.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux_defs.h> diff --git a/board/ep8248/Makefile b/board/ep8248/Makefile deleted file mode 100644 index bfaf1c89d8..0000000000 --- a/board/ep8248/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := ep8248.o diff --git a/board/ep8248/ep8248.c b/board/ep8248/ep8248.c deleted file mode 100644 index 736c1806d1..0000000000 --- a/board/ep8248/ep8248.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Copyright (C) 2004 Arabella Software Ltd. - * Yuli Barcohen <yuli@arabellasw.com> - * - * Support for Embedded Planet EP8248 boards. - * Tested on EP8248E. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8260.h> -#include <ioports.h> - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -#define CONFIG_SYS_FCC1 (CONFIG_ETHER_ON_FCC1 == 1) -#define CONFIG_SYS_FCC2 (CONFIG_ETHER_ON_FCC2 == 1) - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ - /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ - /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ - /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ - /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ - /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */ - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK10) */ - /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK11) */ - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ - /* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK13) */ - /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */ - /* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */ - /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */ - /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ - /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ - /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ - } -}; - -int board_early_init_f (void) -{ - vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; - - bcsr[4] |= 0x30; /* Turn the LEDs off */ - -#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC) - bcsr[6] |= 0x10; -#endif -#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC) - bcsr[7] |= 0x10; -#endif - -#if CONFIG_SYS_FCC1 - bcsr[8] |= 0xC0; -#endif /* CONFIG_SYS_FCC1 */ -#if CONFIG_SYS_FCC2 - bcsr[8] |= 0x30; -#endif /* CONFIG_SYS_FCC2 */ - - return 0; -} - -phys_size_t initdram(int board_type) -{ - vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; - long int msize = 16L << (bcsr[2] & 3); - -#ifndef CONFIG_SYS_RAMBOOT - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE; - uchar c = 0xFF; - uint psdmr = CONFIG_SYS_PSDMR; - int i; - - immap->im_siu_conf.sc_ppc_acr = 0x02; - immap->im_siu_conf.sc_ppc_alrh = 0x30126745; - immap->im_siu_conf.sc_tescr1 = 0x00004000; - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - /* Initialise 60x bus SDRAM */ - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_or1 = CONFIG_SYS_SDRAM_OR; - memctl->memc_br1 = CONFIG_SYS_SDRAM_BR; - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ - for (i = 0; i < 8; i++) - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */ - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ - *ramaddr = c; -#endif /* !CONFIG_SYS_RAMBOOT */ - - /* Return total 60x bus SDRAM size */ - return msize * 1024 * 1024; -} - -int checkboard(void) -{ - vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; - - puts("Board: "); - switch (bcsr[0]) { - case 0x0C: - printf("EP8248E 1.0 CPLD revision %d\n", bcsr[1]); - break; - default: - printf("unknown: ID=%02X\n", bcsr[0]); - } - - return 0; -} - -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup( blob, bd); -} -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/etin/debris/Makefile b/board/etin/debris/Makefile deleted file mode 100644 index 2e74823ea6..0000000000 --- a/board/etin/debris/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = debris.o flash.o phantom.o diff --git a/board/etin/debris/debris.c b/board/etin/debris/debris.c deleted file mode 100644 index 0308fef6cf..0000000000 --- a/board/etin/debris/debris.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * (C) Copyright 2000 - * Sangmoon Kim, Etin Systems. dogoil@etinsys.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> -#include <net.h> -#include <pci.h> -#include <i2c.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard (void) -{ - /*TODO: Check processor type */ - - puts ( "Board: Debris " -#ifdef CONFIG_MPC8240 - "8240" -#endif -#ifdef CONFIG_MPC8245 - "8245" -#endif - " ##Test not implemented yet##\n"); - return 0; -} - -#if 0 /* NOT USED */ -int checkflash (void) -{ - /* TODO: XXX XXX XXX */ - printf ("## Test not implemented yet ##\n"); - - return (0); -} -#endif - -phys_size_t initdram (int board_type) -{ - int m, row, col, bank, i; - unsigned long start, end; - uint32_t mccr1; - uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0; - uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0; - uint8_t mber = 0; - - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - if (i2c_reg_read (0x50, 2) != 0x04) return 0; /* Memory type */ - m = i2c_reg_read (0x50, 5); /* # of physical banks */ - row = i2c_reg_read (0x50, 3); /* # of rows */ - col = i2c_reg_read (0x50, 4); /* # of columns */ - bank = i2c_reg_read (0x50, 17); /* # of logical banks */ - - CONFIG_READ_WORD(MCCR1, mccr1); - mccr1 &= 0xffff0000; - - start = CONFIG_SYS_SDRAM_BASE; - end = start + (1 << (col + row + 3) ) * bank - 1; - - for (i = 0; i < m; i++) { - mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2; - if (i < 4) { - msar1 |= ((start >> 20) & 0xff) << i * 8; - emsar1 |= ((start >> 28) & 0xff) << i * 8; - mear1 |= ((end >> 20) & 0xff) << i * 8; - emear1 |= ((end >> 28) & 0xff) << i * 8; - } else { - msar2 |= ((start >> 20) & 0xff) << (i-4) * 8; - emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8; - mear2 |= ((end >> 20) & 0xff) << (i-4) * 8; - emear2 |= ((end >> 28) & 0xff) << (i-4) * 8; - } - mber |= 1 << i; - start += (1 << (col + row + 3) ) * bank; - end += (1 << (col + row + 3) ) * bank; - } - for (; i < 8; i++) { - if (i < 4) { - msar1 |= 0xff << i * 8; - emsar1 |= 0x30 << i * 8; - mear1 |= 0xff << i * 8; - emear1 |= 0x30 << i * 8; - } else { - msar2 |= 0xff << (i-4) * 8; - emsar2 |= 0x30 << (i-4) * 8; - mear2 |= 0xff << (i-4) * 8; - emear2 |= 0x30 << (i-4) * 8; - } - } - - CONFIG_WRITE_WORD(MCCR1, mccr1); - CONFIG_WRITE_WORD(MSAR1, msar1); - CONFIG_WRITE_WORD(EMSAR1, emsar1); - CONFIG_WRITE_WORD(MEAR1, mear1); - CONFIG_WRITE_WORD(EMEAR1, emear1); - CONFIG_WRITE_WORD(MSAR2, msar2); - CONFIG_WRITE_WORD(EMSAR2, emsar2); - CONFIG_WRITE_WORD(MEAR2, mear2); - CONFIG_WRITE_WORD(EMEAR2, emear2); - CONFIG_WRITE_BYTE(MBER, mber); - - return (1 << (col + row + 3) ) * bank * m; -} - -/* - * Initialize PCI Devices, report devices found. - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_debris_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_debris_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} - -void *nvram_read(void *dest, const long src, size_t count) -{ - volatile uchar *d = (volatile uchar*) dest; - volatile uchar *s = (volatile uchar*) src; - while(count--) { - *d++ = *s++; - asm volatile("sync"); - } - return dest; -} - -void nvram_write(long dest, const void *src, size_t count) -{ - volatile uchar *d = (volatile uchar*)dest; - volatile uchar *s = (volatile uchar*)src; - while(count--) { - *d++ = *s++; - asm volatile("sync"); - } -} - -int misc_init_r(void) -{ - uchar ethaddr[6]; - - if (eth_getenv_enetaddr("ethaddr", ethaddr)) - /* Write ethernet addr in NVRAM for VxWorks */ - nvram_write(CONFIG_ENV_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS, - ethaddr, 6); - - return 0; -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/etin/debris/flash.c b/board/etin/debris/flash.c deleted file mode 100644 index 26579588dd..0000000000 --- a/board/etin/debris/flash.c +++ /dev/null @@ -1,705 +0,0 @@ -/* - * board/eva/flash.c - * - * (C) Copyright 2002 - * Sangmoon Kim, Etin Systems, dogoil@etinsys.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/pci_io.h> -#include <mpc824x.h> -#include <asm/mmu.h> - -int (*do_flash_erase)(flash_info_t*, uint32_t, uint32_t); -int (*write_dword)(flash_info_t*, ulong, uint64_t); - -typedef uint64_t cfi_word; - -#define cfi_read(flash, addr) *((volatile cfi_word*)(flash->start[0] + addr)) - -#define cfi_write(flash, val, addr) \ - move64((cfi_word*)&val, \ - (cfi_word*)(flash->start[0] + addr)) - -#define CMD(x) ((((cfi_word)x)<<48)|(((cfi_word)x)<<32)|(((cfi_word)x)<<16)|(((cfi_word)x))) - -static void write32(unsigned long addr, uint32_t value) -{ - *(volatile uint32_t*)(addr) = value; - asm volatile("sync"); -} - -static uint32_t read32(unsigned long addr) -{ - uint32_t value; - value = *(volatile uint32_t*)addr; - asm volatile("sync"); - return value; -} - -static cfi_word cfi_cmd(flash_info_t *flash, uint8_t cmd, uint32_t addr) -{ - uint32_t base = flash->start[0]; - uint32_t val=(cmd << 16) | cmd; - addr <<= 3; - write32(base + addr, val); - return addr; -} - -static uint16_t cfi_read_query(flash_info_t *flash, uint32_t addr) -{ - uint32_t base = flash->start[0]; - addr <<= 3; - return (uint16_t)read32(base + addr); -} - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -static void move64(uint64_t *src, uint64_t *dest) -{ - asm volatile("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0" ); /* Clobbers fr0 */ - return; -} - -static int cfi_write_dword(flash_info_t *flash, ulong dest, cfi_word data) -{ - unsigned long start; - cfi_word status = 0; - - status = cfi_read(flash, dest); - data &= status; - - cfi_cmd(flash, 0x40, 0); - cfi_write(flash, data, dest); - - udelay(10); - start = get_timer (0); - for(;;) { - status = cfi_read(flash, dest); - status &= CMD(0x80); - if(status == CMD(0x80)) - break; - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - cfi_cmd(flash, 0xff, 0); - return 1; - } - udelay(1); - } - cfi_cmd(flash, 0xff, 0); - - return 0; -} - -static int jedec_write_dword (flash_info_t *flash, ulong dest, cfi_word data) -{ - ulong start; - cfi_word status = 0; - - status = cfi_read(flash, dest); - if(status != CMD(0xffff)) return 2; - - cfi_cmd(flash, 0xaa, 0x555); - cfi_cmd(flash, 0x55, 0x2aa); - cfi_cmd(flash, 0xa0, 0x555); - - cfi_write(flash, data, dest); - - udelay(10); - start = get_timer (0); - status = ~data; - while(status != data) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return 1; - status = cfi_read(flash, dest); - udelay(1); - } - return 0; -} - -static __inline__ unsigned long get_msr(void) -{ - unsigned long msr; - __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void set_msr(unsigned long msr) -{ - __asm__ __volatile__ ("mtmsr %0" : : "r" (msr)); -} - -int write_buff (flash_info_t *flash, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - int i, s, l, rc; - cfi_word data; - uint8_t *t = (uint8_t*)&data; - unsigned long base = flash->start[0]; - uint32_t msr; - - if (flash->flash_id == FLASH_UNKNOWN) - return 4; - - if (cnt == 0) - return 0; - - addr -= base; - - msr = get_msr(); - set_msr(msr|MSR_FP); - - wp = (addr & ~7); /* get lower word aligned address */ - - if((addr-wp) != 0) { - data = cfi_read(flash, wp); - s = addr & 7; - l = ( cnt < (8-s) ) ? cnt : (8-s); - for(i = 0; i < l; i++) - t[s+i] = *src++; - if ((rc = write_dword(flash, wp, data)) != 0) - goto DONE; - wp += 8; - cnt -= l; - } - - while (cnt >= 8) { - for (i = 0; i < 8; i++) - t[i] = *src++; - if ((rc = write_dword(flash, wp, data)) != 0) - goto DONE; - wp += 8; - cnt -= 8; - } - - if (cnt == 0) { - rc = 0; - goto DONE; - } - - data = cfi_read(flash, wp); - for(i = 0; i < cnt; i++) - t[i] = *src++; - rc = write_dword(flash, wp, data); -DONE: - set_msr(msr); - return rc; -} - -static int cfi_erase_oneblock(flash_info_t *flash, uint32_t sect) -{ - int sa; - int flag; - ulong start, last, now; - cfi_word status; - - flag = disable_interrupts(); - - sa = (flash->start[sect] - flash->start[0]); - write32(flash->start[sect], 0x00200020); - write32(flash->start[sect], 0x00d000d0); - - if (flag) - enable_interrupts(); - - udelay(1000); - start = get_timer (0); - last = start; - - for (;;) { - status = cfi_read(flash, sa); - status &= CMD(0x80); - if (status == CMD(0x80)) - break; - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - cfi_cmd(flash, 0xff, 0); - printf ("Timeout\n"); - return ERR_TIMOUT; - } - - if ((now - last) > 1000) { - serial_putc ('.'); - last = now; - } - udelay(10); - } - cfi_cmd(flash, 0xff, 0); - return ERR_OK; -} - -static int cfi_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last) -{ - int sect; - int rc = ERR_OK; - - for (sect = s_first; sect <= s_last; sect++) { - if (flash->protect[sect] == 0) { - rc = cfi_erase_oneblock(flash, sect); - if (rc != ERR_OK) break; - } - } - printf (" done\n"); - return rc; -} - -static int jedec_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last) -{ - int sect; - cfi_word status; - int sa = -1; - int flag; - ulong start, last, now; - - flag = disable_interrupts(); - - cfi_cmd(flash, 0xaa, 0x555); - cfi_cmd(flash, 0x55, 0x2aa); - cfi_cmd(flash, 0x80, 0x555); - cfi_cmd(flash, 0xaa, 0x555); - cfi_cmd(flash, 0x55, 0x2aa); - for ( sect = s_first; sect <= s_last; sect++) { - if (flash->protect[sect] == 0) { - sa = flash->start[sect] - flash->start[0]; - write32(flash->start[sect], 0x00300030); - } - } - if (flag) - enable_interrupts(); - - if (sa < 0) - goto DONE; - - udelay (1000); - start = get_timer (0); - last = start; - for(;;) { - status = cfi_read(flash, sa); - if (status == CMD(0xffff)) - break; - - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return ERR_TIMOUT; - } - - if ((now - last) > 1000) { - serial_putc ('.'); - last = now; - } - udelay(10); - } -DONE: - cfi_cmd(flash, 0xf0, 0); - - printf (" done\n"); - - return ERR_OK; -} - -int flash_erase (flash_info_t *flash, int s_first, int s_last) -{ - int sect; - int prot; - - if ((s_first < 0) || (s_first > s_last)) { - if (flash->flash_id == FLASH_UNKNOWN) - printf ("- missing\n"); - else - printf ("- no sectors to erase\n"); - return ERR_NOT_ERASED; - } - if (flash->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return ERR_NOT_ERASED; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) - if (flash->protect[sect]) prot++; - - if (prot) - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - else - printf ("\n"); - - return do_flash_erase(flash, s_first, s_last); -} - -struct jedec_flash_info { - const uint16_t mfr_id; - const uint16_t dev_id; - const char *name; - const int DevSize; - const int InterfaceDesc; - const int NumEraseRegions; - const ulong regions[4]; -}; - -#define ERASEINFO(size,blocks) (size<<8)|(blocks-1) - -#define SIZE_1MiB 20 -#define SIZE_2MiB 21 -#define SIZE_4MiB 22 - -static const struct jedec_flash_info jedec_table[] = { - { - mfr_id: (uint16_t)AMD_MANUFACT, - dev_id: (uint16_t)AMD_ID_LV800T, - name: "AMD AM29LV800T", - DevSize: SIZE_1MiB, - NumEraseRegions: 4, - regions: {ERASEINFO(0x10000,15), - ERASEINFO(0x08000,1), - ERASEINFO(0x02000,2), - ERASEINFO(0x04000,1) - } - }, { - mfr_id: (uint16_t)AMD_MANUFACT, - dev_id: (uint16_t)AMD_ID_LV800B, - name: "AMD AM29LV800B", - DevSize: SIZE_1MiB, - NumEraseRegions: 4, - regions: {ERASEINFO(0x10000,15), - ERASEINFO(0x08000,1), - ERASEINFO(0x02000,2), - ERASEINFO(0x04000,1) - } - }, { - mfr_id: (uint16_t)AMD_MANUFACT, - dev_id: (uint16_t)AMD_ID_LV160T, - name: "AMD AM29LV160T", - DevSize: SIZE_2MiB, - NumEraseRegions: 4, - regions: {ERASEINFO(0x10000,31), - ERASEINFO(0x08000,1), - ERASEINFO(0x02000,2), - ERASEINFO(0x04000,1) - } - }, { - mfr_id: (uint16_t)AMD_MANUFACT, - dev_id: (uint16_t)AMD_ID_LV160B, - name: "AMD AM29LV160B", - DevSize: SIZE_2MiB, - NumEraseRegions: 4, - regions: {ERASEINFO(0x04000,1), - ERASEINFO(0x02000,2), - ERASEINFO(0x08000,1), - ERASEINFO(0x10000,31) - } - }, { - mfr_id: (uint16_t)AMD_MANUFACT, - dev_id: (uint16_t)AMD_ID_LV320T, - name: "AMD AM29LV320T", - DevSize: SIZE_4MiB, - NumEraseRegions: 2, - regions: {ERASEINFO(0x10000,63), - ERASEINFO(0x02000,8) - } - - }, { - mfr_id: (uint16_t)AMD_MANUFACT, - dev_id: (uint16_t)AMD_ID_LV320B, - name: "AMD AM29LV320B", - DevSize: SIZE_4MiB, - NumEraseRegions: 2, - regions: {ERASEINFO(0x02000,8), - ERASEINFO(0x10000,63) - } - } -}; - -static ulong cfi_init(uint32_t base, flash_info_t *flash) -{ - int sector; - int block; - int block_count; - int offset = 0; - int reverse = 0; - int primary; - int mfr_id; - int dev_id; - - flash->start[0] = base; - cfi_cmd(flash, 0xF0, 0); - cfi_cmd(flash, 0x98, 0); - if ( !( cfi_read_query(flash, 0x10) == 'Q' && - cfi_read_query(flash, 0x11) == 'R' && - cfi_read_query(flash, 0x12) == 'Y' )) { - cfi_cmd(flash, 0xff, 0); - return 0; - } - - flash->size = 1 << cfi_read_query(flash, 0x27); - flash->size *= 4; - block_count = cfi_read_query(flash, 0x2c); - primary = cfi_read_query(flash, 0x15); - if ( cfi_read_query(flash, primary + 4) == 0x30) - reverse = (cfi_read_query(flash, 0x1) & 0x01); - else - reverse = (cfi_read_query(flash, primary+15) == 3); - - flash->sector_count = 0; - - for ( block = reverse ? block_count - 1 : 0; - reverse ? block >= 0 : block < block_count; - reverse ? block-- : block ++) { - int sector_size = - (cfi_read_query(flash, 0x2d + block*4+2) | - (cfi_read_query(flash, 0x2d + block*4+3) << 8)) << 8; - int sector_count = - (cfi_read_query(flash, 0x2d + block*4+0) | - (cfi_read_query(flash, 0x2d + block*4+1) << 8)) + 1; - for(sector = 0; sector < sector_count; sector++) { - flash->start[flash->sector_count++] = base + offset; - offset += sector_size * 4; - } - } - mfr_id = cfi_read_query(flash, 0x00); - dev_id = cfi_read_query(flash, 0x01); - - cfi_cmd(flash, 0xff, 0); - - flash->flash_id = (mfr_id << 16) | dev_id; - - for (sector = 0; sector < flash->sector_count; sector++) { - write32(flash->start[sector], 0x00600060); - write32(flash->start[sector], 0x00d000d0); - } - cfi_cmd(flash, 0xff, 0); - - for (sector = 0; sector < flash->sector_count; sector++) - flash->protect[sector] = 0; - - do_flash_erase = cfi_erase; - write_dword = cfi_write_dword; - - return flash->size; -} - -static ulong jedec_init(unsigned long base, flash_info_t *flash) -{ - int i; - int block, block_count; - int sector, offset; - int mfr_id, dev_id; - flash->start[0] = base; - cfi_cmd(flash, 0xF0, 0x000); - cfi_cmd(flash, 0xAA, 0x555); - cfi_cmd(flash, 0x55, 0x2AA); - cfi_cmd(flash, 0x90, 0x555); - mfr_id = cfi_read_query(flash, 0x000); - dev_id = cfi_read_query(flash, 0x0001); - cfi_cmd(flash, 0xf0, 0x000); - - for(i=0; i<sizeof(jedec_table)/sizeof(struct jedec_flash_info); i++) { - if((jedec_table[i].mfr_id == mfr_id) && - (jedec_table[i].dev_id == dev_id)) { - - flash->flash_id = (mfr_id << 16) | dev_id; - flash->size = 1 << jedec_table[0].DevSize; - flash->size *= 4; - block_count = jedec_table[i].NumEraseRegions; - offset = 0; - flash->sector_count = 0; - for (block = 0; block < block_count; block++) { - int sector_size = jedec_table[i].regions[block]; - int sector_count = (sector_size & 0xff) + 1; - sector_size >>= 8; - for (sector=0; sector<sector_count; sector++) { - flash->start[flash->sector_count++] = - base + offset; - offset += sector_size * 4; - } - } - break; - } - } - - for (sector = 0; sector < flash->sector_count; sector++) - flash->protect[sector] = 0; - - do_flash_erase = jedec_erase; - write_dword = jedec_write_dword; - - return flash->size; -} - -inline void mtibat1u(unsigned int x) -{ - __asm__ __volatile__ ("mtspr 530, %0" :: "r" (x)); -} - -inline void mtibat1l(unsigned int x) -{ - __asm__ __volatile__ ("mtspr 531, %0" :: "r" (x)); -} - -inline void mtdbat1u(unsigned int x) -{ - __asm__ __volatile__ ("mtspr 538, %0" :: "r" (x)); -} - -inline void mtdbat1l(unsigned int x) -{ - __asm__ __volatile__ ("mtspr 539, %0" :: "r" (x)); -} - -unsigned long flash_init (void) -{ - unsigned long size = 0; - int i; - unsigned int msr; - - /* BAT1 */ - CONFIG_WRITE_WORD(ERCR3, 0x0C00000C); - CONFIG_WRITE_WORD(ERCR4, 0x0800000C); - msr = get_msr(); - set_msr(msr & ~(MSR_IR | MSR_DR)); - mtibat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT); - mtibat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP); - mtdbat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT); - mtdbat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP); - set_msr(msr); - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) - flash_info[i].flash_id = FLASH_UNKNOWN; - size = cfi_init(FLASH_BASE0_PRELIM, &flash_info[0]); - if (!size) - size = jedec_init(FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) - printf ("# Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", - size, size<<20); - - return size; -} - -void flash_print_info (flash_info_t *flash) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *p; - - if (flash->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - flash_init(); - } - - if (flash->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (((flash->flash_id) >> 16) & 0xff) { - case 0x01: - printf ("AMD "); - break; - case 0x04: - printf("FUJITSU "); - break; - case 0x20: - printf("STM "); - break; - case 0xBF: - printf("SST "); - break; - case 0x89: - case 0xB0: - printf("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch ((flash->flash_id) & 0xffff) { - case (uint16_t)AMD_ID_LV800T: - printf ("AM29LV800T\n"); - break; - case (uint16_t)AMD_ID_LV800B: - printf ("AM29LV800B\n"); - break; - case (uint16_t)AMD_ID_LV160T: - printf ("AM29LV160T\n"); - break; - case (uint16_t)AMD_ID_LV160B: - printf ("AM29LV160B\n"); - break; - case (uint16_t)AMD_ID_LV320T: - printf ("AM29LV320T\n"); - break; - case (uint16_t)AMD_ID_LV320B: - printf ("AM29LV320B\n"); - break; - case (uint16_t)INTEL_ID_28F800C3T: - printf ("28F800C3T\n"); - break; - case (uint16_t)INTEL_ID_28F800C3B: - printf ("28F800C3B\n"); - break; - case (uint16_t)INTEL_ID_28F160C3T: - printf ("28F160C3T\n"); - break; - case (uint16_t)INTEL_ID_28F160C3B: - printf ("28F160C3B\n"); - break; - case (uint16_t)INTEL_ID_28F320C3T: - printf ("28F320C3T\n"); - break; - case (uint16_t)INTEL_ID_28F320C3B: - printf ("28F320C3B\n"); - break; - case (uint16_t)INTEL_ID_28F640C3T: - printf ("28F640C3T\n"); - break; - case (uint16_t)INTEL_ID_28F640C3B: - printf ("28F640C3B\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - if (flash->size >= (1 << 20)) { - printf (" Size: %ld MB in %d Sectors\n", - flash->size >> 20, flash->sector_count); - } else { - printf (" Size: %ld kB in %d Sectors\n", - flash->size >> 10, flash->sector_count); - } - - printf (" Sector Start Addresses:"); - for (i = 0; i < flash->sector_count; ++i) { - /* Check if whole sector is erased*/ - if (i != (flash->sector_count-1)) - size = flash->start[i+1] - flash->start[i]; - else - size = flash->start[0] + flash->size - flash->start[i]; - - erased = 1; - p = (volatile unsigned long *)flash->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; k<size; k++) { - if (*p++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); - - printf (" %08lX%s%s", - flash->start[i], - erased ? " E" : " ", - flash->protect[i] ? "RO " : " "); - } - printf ("\n"); -} diff --git a/board/etin/debris/phantom.c b/board/etin/debris/phantom.c deleted file mode 100644 index 3d5aa14086..0000000000 --- a/board/etin/debris/phantom.c +++ /dev/null @@ -1,301 +0,0 @@ -/* - * board/eva/phantom.c - * - * Phantom RTC device driver for EVA - * - * Author: Sangmoon Kim - * dogoil@etinsys.com - * - * Copyright 2002 Etinsys Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <rtc.h> - -#if defined(CONFIG_CMD_DATE) - -#define RTC_BASE (CONFIG_SYS_NVRAM_BASE_ADDR + 0x7fff8) - -#define RTC_YEAR ( RTC_BASE + 7 ) -#define RTC_MONTH ( RTC_BASE + 6 ) -#define RTC_DAY_OF_MONTH ( RTC_BASE + 5 ) -#define RTC_DAY_OF_WEEK ( RTC_BASE + 4 ) -#define RTC_HOURS ( RTC_BASE + 3 ) -#define RTC_MINUTES ( RTC_BASE + 2 ) -#define RTC_SECONDS ( RTC_BASE + 1 ) -#define RTC_CENTURY ( RTC_BASE + 0 ) - -#define RTC_CONTROLA RTC_CENTURY -#define RTC_CONTROLB RTC_SECONDS -#define RTC_CONTROLC RTC_DAY_OF_WEEK - -#define RTC_CA_WRITE 0x80 -#define RTC_CA_READ 0x40 - -#define RTC_CB_OSC_DISABLE 0x80 - -#define RTC_CC_BATTERY_FLAG 0x80 -#define RTC_CC_FREQ_TEST 0x40 - - -static int phantom_flag = -1; -static int century_flag = -1; - -static uchar rtc_read(unsigned int addr) -{ - return *(volatile unsigned char *)(addr); -} - -static void rtc_write(unsigned int addr, uchar val) -{ - *(volatile unsigned char *)(addr) = val; -} - -static unsigned char phantom_rtc_sequence[] = { - 0xc5, 0x3a, 0xa3, 0x5c, 0xc5, 0x3a, 0xa3, 0x5c -}; - -static unsigned char* phantom_rtc_read(int addr, unsigned char rtc[8]) -{ - int i, j; - unsigned char v; - unsigned char save = rtc_read(addr); - - for (j = 0; j < 8; j++) { - v = phantom_rtc_sequence[j]; - for (i = 0; i < 8; i++) { - rtc_write(addr, v & 1); - v >>= 1; - } - } - for (j = 0; j < 8; j++) { - v = 0; - for (i = 0; i < 8; i++) { - if(rtc_read(addr) & 1) - v |= 1 << i; - } - rtc[j] = v; - } - rtc_write(addr, save); - return rtc; -} - -static void phantom_rtc_write(int addr, unsigned char rtc[8]) -{ - int i, j; - unsigned char v; - unsigned char save = rtc_read(addr); - for (j = 0; j < 8; j++) { - v = phantom_rtc_sequence[j]; - for (i = 0; i < 8; i++) { - rtc_write(addr, v & 1); - v >>= 1; - } - } - for (j = 0; j < 8; j++) { - v = rtc[j]; - for (i = 0; i < 8; i++) { - rtc_write(addr, v & 1); - v >>= 1; - } - } - rtc_write(addr, save); -} - -static int get_phantom_flag(void) -{ - int i; - unsigned char rtc[8]; - - phantom_rtc_read(RTC_BASE, rtc); - - for(i = 1; i < 8; i++) { - if (rtc[i] != rtc[0]) - return 1; - } - return 0; -} - -void rtc_reset(void) -{ - if (phantom_flag < 0) - phantom_flag = get_phantom_flag(); - - if (phantom_flag) { - unsigned char rtc[8]; - phantom_rtc_read(RTC_BASE, rtc); - if(rtc[4] & 0x30) { - printf( "real-time-clock was stopped. Now starting...\n" ); - rtc[4] &= 0x07; - phantom_rtc_write(RTC_BASE, rtc); - } - } else { - uchar reg_a, reg_b, reg_c; - reg_a = rtc_read( RTC_CONTROLA ); - reg_b = rtc_read( RTC_CONTROLB ); - - if ( reg_b & RTC_CB_OSC_DISABLE ) - { - printf( "real-time-clock was stopped. Now starting...\n" ); - reg_a |= RTC_CA_WRITE; - reg_b &= ~RTC_CB_OSC_DISABLE; - rtc_write( RTC_CONTROLA, reg_a ); - rtc_write( RTC_CONTROLB, reg_b ); - } - - /* make sure read/write clock register bits are cleared */ - reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ ); - rtc_write( RTC_CONTROLA, reg_a ); - - reg_c = rtc_read( RTC_CONTROLC ); - if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 ) - printf( "RTC battery low. Clock setting may not be reliable.\n"); - } -} - -static int get_century_flag(void) -{ - int flag = 0; - int bcd, century; - bcd = rtc_read( RTC_CENTURY ); - century = bcd2bin( bcd & 0x3F ); - rtc_write( RTC_CENTURY, bin2bcd(century+1)); - if (bcd == rtc_read( RTC_CENTURY )) - flag = 1; - rtc_write( RTC_CENTURY, bcd); - return flag; -} - -int rtc_get( struct rtc_time *tmp) -{ - if (phantom_flag < 0) - phantom_flag = get_phantom_flag(); - - if (phantom_flag) - { - unsigned char rtc[8]; - - phantom_rtc_read(RTC_BASE, rtc); - - tmp->tm_sec = bcd2bin(rtc[1] & 0x7f); - tmp->tm_min = bcd2bin(rtc[2] & 0x7f); - tmp->tm_hour = bcd2bin(rtc[3] & 0x1f); - tmp->tm_wday = bcd2bin(rtc[4] & 0x7); - tmp->tm_mday = bcd2bin(rtc[5] & 0x3f); - tmp->tm_mon = bcd2bin(rtc[6] & 0x1f); - tmp->tm_year = bcd2bin(rtc[7]) + 1900; - tmp->tm_yday = 0; - tmp->tm_isdst = 0; - - if( (rtc[3] & 0x80) && (rtc[3] & 0x40) ) tmp->tm_hour += 12; - if (tmp->tm_year < 1970) tmp->tm_year += 100; - } else { - uchar sec, min, hour; - uchar mday, wday, mon, year; - - int century; - - uchar reg_a; - - if (century_flag < 0) - century_flag = get_century_flag(); - - reg_a = rtc_read( RTC_CONTROLA ); - /* lock clock registers for read */ - rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ )); - - sec = rtc_read( RTC_SECONDS ); - min = rtc_read( RTC_MINUTES ); - hour = rtc_read( RTC_HOURS ); - mday = rtc_read( RTC_DAY_OF_MONTH ); - wday = rtc_read( RTC_DAY_OF_WEEK ); - mon = rtc_read( RTC_MONTH ); - year = rtc_read( RTC_YEAR ); - century = rtc_read( RTC_CENTURY ); - - /* unlock clock registers after read */ - rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ )); - - tmp->tm_sec = bcd2bin( sec & 0x7F ); - tmp->tm_min = bcd2bin( min & 0x7F ); - tmp->tm_hour = bcd2bin( hour & 0x3F ); - tmp->tm_mday = bcd2bin( mday & 0x3F ); - tmp->tm_mon = bcd2bin( mon & 0x1F ); - tmp->tm_wday = bcd2bin( wday & 0x07 ); - - if (century_flag) { - tmp->tm_year = bcd2bin( year ) + - ( bcd2bin( century & 0x3F ) * 100 ); - } else { - tmp->tm_year = bcd2bin( year ) + 1900; - if (tmp->tm_year < 1970) tmp->tm_year += 100; - } - - tmp->tm_yday = 0; - tmp->tm_isdst= 0; - } - - return 0; -} - -int rtc_set( struct rtc_time *tmp ) -{ - if (phantom_flag < 0) - phantom_flag = get_phantom_flag(); - - if (phantom_flag) { - uint year; - unsigned char rtc[8]; - - year = tmp->tm_year; - year -= (year < 2000) ? 1900 : 2000; - - rtc[0] = bin2bcd(0); - rtc[1] = bin2bcd(tmp->tm_sec); - rtc[2] = bin2bcd(tmp->tm_min); - rtc[3] = bin2bcd(tmp->tm_hour); - rtc[4] = bin2bcd(tmp->tm_wday); - rtc[5] = bin2bcd(tmp->tm_mday); - rtc[6] = bin2bcd(tmp->tm_mon); - rtc[7] = bin2bcd(year); - - phantom_rtc_write(RTC_BASE, rtc); - } else { - uchar reg_a; - if (century_flag < 0) - century_flag = get_century_flag(); - - /* lock clock registers for write */ - reg_a = rtc_read( RTC_CONTROLA ); - rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE )); - - rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon )); - - rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday )); - rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday )); - rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour )); - rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min )); - rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec )); - - /* break year up into century and year in century */ - if (century_flag) { - rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 )); - rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 )); - reg_a &= 0xc0; - reg_a |= bin2bcd( tmp->tm_year / 100 ); - } else { - rtc_write(RTC_YEAR, bin2bcd(tmp->tm_year - - ((tmp->tm_year < 2000) ? 1900 : 2000))); - } - - /* unlock clock registers after read */ - rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE )); - } - - return 0; -} - -#endif diff --git a/board/etin/kvme080/Makefile b/board/etin/kvme080/Makefile deleted file mode 100644 index d1b6f30440..0000000000 --- a/board/etin/kvme080/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = kvme080.o multiverse.o diff --git a/board/etin/kvme080/kvme080.c b/board/etin/kvme080/kvme080.c deleted file mode 100644 index baf4cbc4da..0000000000 --- a/board/etin/kvme080/kvme080.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * (C) Copyright 2005 - * Sangmoon Kim, Etin Systems. dogoil@etinsys.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> -#include <pci.h> -#include <i2c.h> -#include <netdev.h> -#include <asm/processor.h> -#include <asm/mmu.h> - -int checkboard(void) -{ - puts ("Board: KVME080\n"); - return 0; -} - -unsigned long setdram(int m, int row, int col, int bank) -{ - int i; - unsigned long start, end; - uint32_t mccr1; - uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0; - uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0; - uint8_t mber = 0; - - CONFIG_READ_WORD(MCCR1, mccr1); - mccr1 &= 0xffff0000; - - start = CONFIG_SYS_SDRAM_BASE; - end = start + (1 << (col + row + 3) ) * bank - 1; - - for (i = 0; i < m; i++) { - mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2; - if (i < 4) { - msar1 |= ((start >> 20) & 0xff) << i * 8; - emsar1 |= ((start >> 28) & 0xff) << i * 8; - mear1 |= ((end >> 20) & 0xff) << i * 8; - emear1 |= ((end >> 28) & 0xff) << i * 8; - } else { - msar2 |= ((start >> 20) & 0xff) << (i-4) * 8; - emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8; - mear2 |= ((end >> 20) & 0xff) << (i-4) * 8; - emear2 |= ((end >> 28) & 0xff) << (i-4) * 8; - } - mber |= 1 << i; - start += (1 << (col + row + 3) ) * bank; - end += (1 << (col + row + 3) ) * bank; - } - for (; i < 8; i++) { - if (i < 4) { - msar1 |= 0xff << i * 8; - emsar1 |= 0x30 << i * 8; - mear1 |= 0xff << i * 8; - emear1 |= 0x30 << i * 8; - } else { - msar2 |= 0xff << (i-4) * 8; - emsar2 |= 0x30 << (i-4) * 8; - mear2 |= 0xff << (i-4) * 8; - emear2 |= 0x30 << (i-4) * 8; - } - } - - CONFIG_WRITE_WORD(MCCR1, mccr1); - CONFIG_WRITE_WORD(MSAR1, msar1); - CONFIG_WRITE_WORD(EMSAR1, emsar1); - CONFIG_WRITE_WORD(MEAR1, mear1); - CONFIG_WRITE_WORD(EMEAR1, emear1); - CONFIG_WRITE_WORD(MSAR2, msar2); - CONFIG_WRITE_WORD(EMSAR2, emsar2); - CONFIG_WRITE_WORD(MEAR2, mear2); - CONFIG_WRITE_WORD(EMEAR2, emear2); - CONFIG_WRITE_BYTE(MBER, mber); - - return (1 << (col + row + 3) ) * bank * m; -} - -phys_size_t initdram(int board_type) -{ - unsigned int msr; - long int size = 0; - - msr = mfmsr(); - mtmsr(msr & ~(MSR_IR | MSR_DR)); - mtspr(IBAT2L, CONFIG_SYS_IBAT0L + 0x10000000); - mtspr(IBAT2U, CONFIG_SYS_IBAT0U + 0x10000000); - mtspr(DBAT2L, CONFIG_SYS_DBAT0L + 0x10000000); - mtspr(DBAT2U, CONFIG_SYS_DBAT0U + 0x10000000); - mtmsr(msr); - - if (setdram(2,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x20000000)) - size = 0x20000000; /* 512MB */ - else if (setdram(1,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000)) - size = 0x10000000; /* 256MB */ - else if (setdram(2,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000)) - size = 0x10000000; /* 256MB */ - else if (setdram(1,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000)) - size = 0x08000000; /* 128MB */ - else if (setdram(2,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000)) - size = 0x08000000; /* 128MB */ - else if (setdram(1,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x04000000)) - size = 0x04000000; /* 64MB */ - - msr = mfmsr(); - mtmsr(msr & ~(MSR_IR | MSR_DR)); - mtspr(IBAT2L, CONFIG_SYS_IBAT2L); - mtspr(IBAT2U, CONFIG_SYS_IBAT2U); - mtspr(DBAT2L, CONFIG_SYS_DBAT2L); - mtspr(DBAT2U, CONFIG_SYS_DBAT2U); - mtmsr(msr); - - return size; -} - -struct pci_controller hose; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} - -int board_early_init_f(void) -{ - *(volatile unsigned char *)(0xff080120) = 0xfb; - - return 0; -} - -int board_early_init_r(void) -{ - unsigned int msr; - - CONFIG_WRITE_WORD(ERCR1, 0x95ff8000); - CONFIG_WRITE_WORD(ERCR3, 0x0c00000e); - CONFIG_WRITE_WORD(ERCR4, 0x0800000e); - - msr = mfmsr(); - mtmsr(msr & ~(MSR_IR | MSR_DR)); - mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT); - mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP); - mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT); - mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP); - mtmsr(msr); - - return 0; -} - -extern int multiverse_init(void); - -int misc_init_r(void) -{ - multiverse_init(); - return 0; -} - -void *nvram_read(void *dest, const long src, size_t count) -{ - volatile uchar *d = (volatile uchar*) dest; - volatile uchar *s = (volatile uchar*) src; - while(count--) { - *d++ = *s++; - asm volatile("sync"); - } - return dest; -} - -void nvram_write(long dest, const void *src, size_t count) -{ - volatile uchar *d = (volatile uchar*)dest; - volatile uchar *s = (volatile uchar*)src; - while(count--) { - *d++ = *s++; - asm volatile("sync"); - } -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/etin/kvme080/multiverse.c b/board/etin/kvme080/multiverse.c deleted file mode 100644 index 2bcfe2ea04..0000000000 --- a/board/etin/kvme080/multiverse.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * multiverse.c - * - * VME driver for Multiverse - * - * Author : Sangmoon Kim - * dogoil@etinsys.com - * - * Copyright 2005 ETIN SYSTEMS Co.,Ltd. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <pci.h> -#include <linux/compiler.h> - -#include "multiverse.h" - -static unsigned long vme_asi_addr; -static unsigned long vme_iack_addr; -static unsigned long pci_reg_addr; -static unsigned long vme_reg_addr; - -int multiv_reset(unsigned long base) -{ - writeb(0x09, base + VME_SLAVE32_AM); - writeb(0x39, base + VME_SLAVE24_AM); - writeb(0x29, base + VME_SLAVE16_AM); - writeb(0x2f, base + VME_SLAVE_REG_AM); - writeb((VME_A32_SLV_BUS >> 24) & 0xff, base + VME_SLAVE32_A); - writeb((VME_A24_SLV_BUS >> 16) & 0xff, base + VME_SLAVE24_A); - writeb((VME_A16_SLV_BUS >> 8 ) & 0xff, base + VME_SLAVE16_A); -#ifdef A32_SLV_WINDOW - if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) { - writeb(((~(VME_A32_SLV_SIZE-1)) >> 24) & 0xff, - base + VME_SLAVE32_MASK); - writeb(0x01, base + VME_SLAVE32_EN); - } else { - writeb(0xff, base + VME_SLAVE32_MASK); - writeb(0x00, base + VME_SLAVE32_EN); - } -#else - writeb(0xff, base + VME_SLAVE32_MASK); - writeb(0x00, base + VME_SLAVE32_EN); -#endif -#ifdef A24_SLV_WINDOW - if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) { - writeb(((~(VME_A24_SLV_SIZE-1)) >> 16) & 0xff, - base + VME_SLAVE24_MASK); - writeb(0x01, base + VME_SLAVE24_EN); - } else { - writeb(0xff, base + VME_SLAVE24_MASK); - writeb(0x00, base + VME_SLAVE24_EN); - } -#else - writeb(0xff, base + VME_SLAVE24_MASK); - writeb(0x00, base + VME_SLAVE24_EN); -#endif -#ifdef A16_SLV_WINDOW - if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) { - writeb(((~(VME_A16_SLV_SIZE-1)) >> 8) & 0xff, - base + VME_SLAVE16_MASK); - writeb(0x01, base + VME_SLAVE16_EN); - } else { - writeb(0xff, base + VME_SLAVE16_MASK); - writeb(0x00, base + VME_SLAVE16_EN); - } -#else - writeb(0xff, base + VME_SLAVE16_MASK); - writeb(0x00, base + VME_SLAVE16_EN); -#endif -#ifdef REG_SLV_WINDOW - if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) { - writeb(((~(VME_REG_SLV_SIZE-1)) >> 16) & 0xff, - base + VME_SLAVE_REG_MASK); - writeb(0x01, base + VME_SLAVE_REG_EN); - } else { - writeb(0xf8, base + VME_SLAVE_REG_MASK); - } -#else - writeb(0xf8, base + VME_SLAVE_REG_MASK); -#endif - writeb(0x09, base + VME_MASTER32_AM); - writeb(0x39, base + VME_MASTER24_AM); - writeb(0x29, base + VME_MASTER16_AM); - writeb(0x2f, base + VME_MASTER_REG_AM); - writel(0x00000000, base + VME_RMW_ADRS); - writeb(0x00, base + VME_IRQ); - writeb(0x00, base + VME_INT_EN); - writel(0x00000000, base + VME_IRQ1_REG); - writel(0x00000000, base + VME_IRQ2_REG); - writel(0x00000000, base + VME_IRQ3_REG); - writel(0x00000000, base + VME_IRQ4_REG); - writel(0x00000000, base + VME_IRQ5_REG); - writel(0x00000000, base + VME_IRQ6_REG); - writel(0x00000000, base + VME_IRQ7_REG); - return 0; -} - -void multiv_auto_slot_id(unsigned long base) -{ - __maybe_unused unsigned int vector; - int slot_id = 1; - if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) { - *(volatile unsigned int*)(base + VME_IRQ2_REG) = 0xfe; - writeb(readb(base + VME_IRQ) | 0x04, base + VME_IRQ); - writeb(readb(base + VME_CTRL) & ~VME_CTRL_SYSFAIL, - base + VME_CTRL); - while (readb(base + VME_STATUS) & VME_STATUS_SYSFAIL); - if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) { - while (readb(base + VME_INT) & 0x04) { - vector = *(volatile unsigned int*) - (vme_iack_addr + VME_IACK2); - *(unsigned char*)(vme_asi_addr + 0x7ffff) - = (slot_id << 3) & 0xff; - slot_id ++; - if (slot_id > 31) - break; - } - } - } -} - -int multiverse_init(void) -{ - int i; - pci_dev_t pdev; - unsigned int bar[6]; - - pdev = pci_find_device(0x1895, 0x0001, 0); - - if (pdev == 0) - return -1; - - for (i = 0; i < 6; i++) - pci_read_config_dword (pdev, - PCI_BASE_ADDRESS_0 + i * 4, &bar[i]); - - pci_reg_addr = bar[0]; - vme_reg_addr = bar[1] + 0x00F00000; - vme_iack_addr = bar[1] + 0x00200000; - vme_asi_addr = bar[3]; - - pci_write_config_dword (pdev, PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - - writel(0xFF000000, pci_reg_addr + P_TA1); - writel(0x04, pci_reg_addr + P_IMG_CTRL1); - writel(0xf0000000, pci_reg_addr + P_TA2); - writel(0x04, pci_reg_addr + P_IMG_CTRL2); - writel(0xF1000000, pci_reg_addr + P_TA3); - writel(0x04, pci_reg_addr + P_IMG_CTRL3); - writel(VME_A32_MSTR_BUS, pci_reg_addr + P_TA5); - writel(~(VME_A32_MSTR_SIZE-1), pci_reg_addr + P_AM5); - writel(0x04, pci_reg_addr + P_IMG_CTRL5); - - writel(VME_A32_SLV_BUS, pci_reg_addr + W_BA1); - writel(~(VME_A32_SLV_SIZE-1), pci_reg_addr + W_AM1); - writel(VME_A32_SLV_LOCAL, pci_reg_addr + W_TA1); - writel(0x04, pci_reg_addr + W_IMG_CTRL1); - - writel(0xF0000000, pci_reg_addr + W_BA2); - writel(0xFF000000, pci_reg_addr + W_AM2); - writel(VME_A24_SLV_LOCAL, pci_reg_addr + W_TA2); - writel(0x04, pci_reg_addr + W_IMG_CTRL2); - - writel(0xFF000000, pci_reg_addr + W_BA3); - writel(0xFF000000, pci_reg_addr + W_AM3); - writel(VME_A16_SLV_LOCAL, pci_reg_addr + W_TA3); - writel(0x04, pci_reg_addr + W_IMG_CTRL3); - - writel(0x00000001, pci_reg_addr + W_ERR_CS); - writel(0x00000001, pci_reg_addr + P_ERR_CS); - - multiv_reset(vme_reg_addr); - writeb(readb(vme_reg_addr + VME_CTRL) | VME_CTRL_SHORT_D, - vme_reg_addr + VME_CTRL); - - multiv_auto_slot_id(vme_reg_addr); - - return 0; -} diff --git a/board/etin/kvme080/multiverse.h b/board/etin/kvme080/multiverse.h deleted file mode 100644 index b3b79b7ee3..0000000000 --- a/board/etin/kvme080/multiverse.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * multiverse.h - * - * VME driver for Multiverse - * - * Author : Sangmoon Kim - * dogoil@etinsys.com - * - * Copyright 2005 ETIN SYSTEMS Co.,Ltd. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MULTIVERSE_H__ -#define __MULTIVERSE_H__ - -#define VME_A32_MSTR_BUS 0x90000000 -#define VME_A32_MSTR_SIZE 0x01000000 - -#define VME_A32_SLV_SIZE 0x01000000 - -#define VME_A32_SLV_BUS 0x90000000 -#define VME_A24_SLV_BUS 0x00000000 -#define VME_A16_SLV_BUS 0x00000000 - -#define VME_A32_SLV_LOCAL 0x00000000 -#define VME_A24_SLV_LOCAL 0x00000000 -#define VME_A16_SLV_LOCAL 0x00000000 - -#define A32_SLV_WINDOW -#undef A24_SLV_WINDOW -#undef A16_SLV_WINDOW -#undef REG_SLV_WINDOW - -/* PCI Registers */ - -#define P_IMG_CTRL0 0x100 -#define P_BA0 0x104 -#define P_AM0 0x108 -#define P_TA0 0x10C -#define P_IMG_CTRL1 0x110 -#define P_BA1 0x114 -#define P_AM1 0x118 -#define P_TA1 0x11C -#define P_IMG_CTRL2 0x120 -#define P_BA2 0x124 -#define P_AM2 0x128 -#define P_TA2 0x12C -#define P_IMG_CTRL3 0x130 -#define P_BA3 0x134 -#define P_AM3 0x138 -#define P_TA3 0x13C -#define P_IMG_CTRL4 0x140 -#define P_BA4 0x144 -#define P_AM4 0x148 -#define P_TA4 0x14C -#define P_IMG_CTRL5 0x150 -#define P_BA5 0x154 -#define P_AM5 0x158 -#define P_TA5 0x15C -#define P_ERR_CS 0x160 -#define P_ERR_ADDR 0x164 -#define P_ERR_DATA 0x168 - -#define WB_CONF_SPC_BAR 0x180 -#define W_IMG_CTRL1 0x184 -#define W_BA1 0x188 -#define W_AM1 0x18C -#define W_TA1 0x190 -#define W_IMG_CTRL2 0x194 -#define W_BA2 0x198 -#define W_AM2 0x19C -#define W_TA2 0x1A0 -#define W_IMG_CTRL3 0x1A4 -#define W_BA3 0x1A8 -#define W_AM3 0x1AC -#define W_TA3 0x1B0 -#define W_IMG_CTRL4 0x1B4 -#define W_BA4 0x1B8 -#define W_AM4 0x1BC -#define W_TA4 0x1C0 -#define W_IMG_CTRL5 0x1C4 -#define W_BA5 0x1C8 -#define W_AM5 0x1CC -#define W_TA5 0x1D0 -#define W_ERR_CS 0x1D4 -#define W_ERR_ADDR 0x1D8 -#define W_ERR_DATA 0x1DC -#define CNF_ADDR 0x1E0 -#define CNF_DATA 0x1E4 -#define INT_ACK 0x1E8 -#define ICR 0x1EC -#define ISR 0x1F0 - -/* VME registers */ - -#define VME_SLAVE32_AM 0x03 -#define VME_SLAVE24_AM 0x02 -#define VME_SLAVE16_AM 0x01 -#define VME_SLAVE_REG_AM 0x00 -#define VME_SLAVE32_A 0x07 -#define VME_SLAVE24_A 0x06 -#define VME_SLAVE16_A 0x05 -#define VME_SLAVE_REG_A 0x04 -#define VME_SLAVE32_MASK 0x0B -#define VME_SLAVE24_MASK 0x0A -#define VME_SLAVE16_MASK 0x09 -#define VME_SLAVE_REG_MASK 0x08 -#define VME_SLAVE32_EN 0x0F -#define VME_SLAVE24_EN 0x0E -#define VME_SLAVE16_EN 0x0D -#define VME_SLAVE_REG_EN 0x0C -#define VME_MASTER32_AM 0x13 -#define VME_MASTER24_AM 0x12 -#define VME_MASTER16_AM 0x11 -#define VME_MASTER_REG_AM 0x10 -#define VME_RMW_ADRS 0x14 -#define VME_MBOX 0x18 -#define VME_STATUS 0x1E -#define VME_CTRL 0x1C -#define VME_IRQ 0x20 -#define VME_INT_EN 0x21 -#define VME_INT 0x22 -#define VME_IRQ1_REG 0x24 -#define VME_IRQ2_REG 0x28 -#define VME_IRQ3_REG 0x2C -#define VME_IRQ4_REG 0x30 -#define VME_IRQ5_REG 0x34 -#define VME_IRQ6_REG 0x38 -#define VME_IRQ7_REG 0x3C - -/* VME control register */ - -#define VME_CTRL_BRDRST 0x01 -#define VME_CTRL_SYSRST 0x02 -#define VME_CTRL_RMW 0x04 -#define VME_CTRL_SHORT_D 0x08 -#define VME_CTRL_SYSFAIL 0x10 -#define VME_CTRL_VOWN 0x20 -#define VME_CTRL_A16_REG_MODE 0x40 - -/* VME status register */ - -#define VME_STATUS_SYSCON 0x01 -#define VME_STATUS_SYSFAIL 0x02 -#define VME_STATUS_ACFAIL 0x04 -#define VME_STATUS_SYSRST 0x08 -#define VME_STATUS_VOWN 0x10 - -/* Interrupt types */ - -#define LVL1 0x0002 -#define LVL2 0x0004 -#define LVL3 0x0008 -#define LVL4 0x0010 -#define LVL5 0x0020 -#define LVL6 0x0040 -#define LVL7 0x0080 -#define MULTIVERSE_INTI_INT 0x0100 -#define MULTIVERSE_WB_INT 0x0200 -#define MULTIVERSE_PCI_INT 0x0400 - -/* interrupt acknowledge */ - -#define VME_IACK1 0x04 -#define VME_IACK2 0x08 -#define VME_IACK3 0x0c -#define VME_IACK4 0x10 -#define VME_IACK5 0x14 -#define VME_IACK6 0x18 -#define VME_IACK7 0x1c - -#endif /* __MULTIVERSE_H__ */ diff --git a/board/fads/Makefile b/board/fads/Makefile deleted file mode 100644 index ea8b5c0d81..0000000000 --- a/board/fads/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = fads.o flash.o lamp.o pcmcia.o diff --git a/board/fads/README b/board/fads/README deleted file mode 100644 index 0873682787..0000000000 --- a/board/fads/README +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2000 - * Dave Ellis, SIXNET, dge@sixnetio.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -Using the Motorola MPC8XXFADS development board -=============================================== - -CONFIGURATIONS --------------- - -There are ready-to-use default configurations available for the -FADS823, FADS850SAR and FADS860T. The FADS860T configuration also -works for the 855T processor. - -LOADING U-Boot INTO FADS FLASH MEMORY --------------------------------------- - -MPC8BUG can load U-Boot into the FLASH memory using LOADF. - - loadf u-boot.srec 100000 - - -STARTING U-Boot FROM MPC8BUG ------------------------------ - -To start U-Boot from MPC8BUG: - -1. Reset the board: - reset :h - -2. Change BR0 and OR0 back to their values at reset: - rms memc br0 00000001 - rms memc or0 00000d34 - -3. Modify DER so MPC8BUG gets control only when it should: - rms der 2002000f - -4. Start as if from reset: - go 100 - -This is NOT exactly the same as starting U-Boot without -MPC8BUG. MPC8BUG turns off the watchdog as part of the hard reset. -After it does the reset it writes SYPCR (to disable the watchdog) -and sets BR0 and OR0 to map the FLASH at 0x02800000 (and does lots -of other initialization). That is why it is necessary to set BR0 -and OR0 to map the FLASH everywhere. U-Boot can't turn on the -watchdog after that, since MPC8BUG has used the only chance to write -to SYPCR. - -Here is a bizarre sequence of MPC8BUG and U-Boot commands that lets -U-Boot write to SYPCR. It works with MPC8BUG 1.5 and an 855T -processor (your mileage may vary). It is probably better (and a lot -easier) just to accept having the watchdog disabled when the debug -cable is connected. - -in MPC8BUG: - reset :h - rms memc br0 00000001 - rms memc or0 00000d34 - rms der 2000f - go 100 - -Now U-Boot is running with the MPC8BUG value for SYPCR. Use the -U-Boot 'reset' command to reset the board. - =>reset -Next, in MPC8BUG: - rms der 2000f - go - -Now U-Boot is running with the U-Boot value for SYPCR. diff --git a/board/fads/fads.c b/board/fads/fads.c deleted file mode 100644 index fdb46b1f35..0000000000 --- a/board/fads/fads.c +++ /dev/null @@ -1,870 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <mpc8xx.h> -#include <pcmcia.h> - -#define _NOT_USED_ 0xFFFFFFFF - -/* ========================================================================= */ - -#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */ - -#if defined(CONFIG_DRAM_50MHZ) -/* 50MHz tables */ -static const uint dram_60ns[] = -{ 0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04, - 0x00ffec00, 0x37ffec47, _NOT_USED_, _NOT_USED_, - 0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c, - 0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44, - 0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00, - 0x3fffc847, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06, - 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint dram_70ns[] = -{ 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04, - 0x00ffcc00, 0x37ffcc47, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04, - 0x00ffcc08, 0x0cffcc44, 0x00ffec0c, 0x03ffec00, - 0x00ffec44, 0x00ffcc08, 0x0cffcc44, 0x00ffec04, - 0x00ffec00, 0x3fffec47, _NOT_USED_, _NOT_USED_, - 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04, - 0x7fffcc06, 0xffffcc85, 0xffffcc05, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint edo_60ns[] = -{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04, - 0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_, - 0x8fffec24, 0x0ffbec04, 0x0cf3ec04, 0x00f3ec0c, - 0x0cf3ec00, 0x00f3ec4c, 0x0cf3ec00, 0x00f3ec4c, - 0x0cf3ec00, 0x00f3ec44, 0x03f3ec00, 0x3ff7ec47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06, - 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint edo_70ns[] = -{ 0x8ffbcc24, 0x0ff3cc04, 0x0cf3cc04, 0x00f3cc04, - 0x00f3cc00, 0x37f7cc47, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc0c, - 0x03f3cc00, 0x00f3cc44, 0x00f3ec0c, 0x0cf3ec00, - 0x00f3ec4c, 0x03f3ec00, 0x00f3ec44, 0x00f3cc00, - 0x33f7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x33bfcc47, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04, - 0x7fffcc04, 0xffffcc86, 0xffffcc05, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -#elif defined(CONFIG_DRAM_25MHZ) - -/* 25MHz tables */ - -static const uint dram_60ns[] = -{ 0x0fffcc04, 0x08ffcc00, 0x33ffcc47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c, - 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c, - 0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, - 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, - 0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint dram_70ns[] = -{ 0x0fffec04, 0x08ffec04, 0x00ffec00, 0x3fffcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c, - 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c, - 0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, - 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, - 0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint edo_60ns[] = -{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0ffbcc04, 0x09f3cc0c, 0x09f3cc0c, 0x09f3cc0c, - 0x08f3cc00, 0x3ff7cc47, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fefcc04, 0x08afcc00, 0x07afcc48, 0x08afcc48, - 0x08afcc48, 0x39bfcc47, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint edo_70ns[] = -{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0ffbec04, 0x08f3ec04, 0x03f3ec48, 0x08f3cc00, - 0x0ff3cc4c, 0x08f3cc00, 0x0ff3cc4c, 0x08f3cc00, - 0x3ff7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fefcc04, 0x08afcc00, 0x07afcc4c, 0x08afcc00, - 0x07afcc4c, 0x08afcc00, 0x07afcc4c, 0x08afcc00, - 0x37bfcc47, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; -#else -#error dram not correctly defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ -#endif - -/* ------------------------------------------------------------------------- */ -static int _draminit (uint base, uint noMbytes, uint edo, uint delay) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* init upm */ - - switch (delay) { - case 70: - if (edo) { - upmconfig (UPMA, (uint *) edo_70ns, - sizeof (edo_70ns) / sizeof (uint)); - } else { - upmconfig (UPMA, (uint *) dram_70ns, - sizeof (dram_70ns) / sizeof (uint)); - } - - break; - - case 60: - if (edo) { - upmconfig (UPMA, (uint *) edo_60ns, - sizeof (edo_60ns) / sizeof (uint)); - } else { - upmconfig (UPMA, (uint *) dram_60ns, - sizeof (dram_60ns) / sizeof (uint)); - } - - break; - - default: - return -1; - } - - memctl->memc_mptpr = 0x0400; /* divide by 16 */ - - switch (noMbytes) { - case 4: /* 4 Mbyte uses only CS2 */ - memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */ - memctl->memc_or2 = 0xffc00800; /* 4M */ - break; - - case 8: /* 8 Mbyte uses both CS3 and CS2 */ - memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */ - memctl->memc_or3 = 0xffc00800; /* 4M */ - memctl->memc_br3 = 0x00400081 + base; - memctl->memc_or2 = 0xffc00800; /* 4M */ - break; - - case 16: /* 16 Mbyte uses only CS2 */ - memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */ - memctl->memc_or2 = 0xff000800; /* 16M */ - break; - - case 32: /* 32 Mbyte uses both CS3 and CS2 */ - memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */ - memctl->memc_or3 = 0xff000800; /* 16M */ - memctl->memc_br3 = 0x01000081 + base; - memctl->memc_or2 = 0xff000800; /* 16M */ - break; - - default: - return -1; - } - - memctl->memc_br2 = 0x81 + base; /* use upma */ - - *((uint *) BCSR1) &= ~BCSR1_DRAM_EN; /* enable dram */ - - /* if no dimm is inserted, noMbytes is still detected as 8m, so - * sanity check top and bottom of memory */ - - /* check bytes / 2 because get_ram_size tests at base+bytes, which - * is not mapped */ - if (noMbytes == 8) - if (get_ram_size ((long *) base, noMbytes << 19) != noMbytes << 19) { - *((uint *) BCSR1) |= BCSR1_DRAM_EN; /* disable dram */ - return -1; - } - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -static void _dramdisable(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_br2 = 0x00000000; - memctl->memc_br3 = 0x00000000; - - /* maybe we should turn off upma here or something */ -} -#endif /* !CONFIG_MPC885ADS */ - -/* ========================================================================= */ - -#ifdef CONFIG_FADS /* SDRAM exists on FADS and newer boards */ - -#if defined(CONFIG_SDRAM_100MHZ) - -/* ------------------------------------------------------------------------- */ -/* sdram table by Dan Malek */ - -/* This has the stretched early timing so the 50 MHz - * processor can make the 100 MHz timing. This will - * work at all processor speeds. - */ - -#ifdef SDRAM_ALT_INIT_SEQENCE -# define SDRAM_MBMRVALUE0 0xc3802114 /* PTx=195,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */ -#define SDRAM_MBMRVALUE1 SDRAM_MBMRVALUE0 -# define SDRAM_MCRVALUE0 0x80808111 /* run upmb cs4 loop 1 addr 0x11 MRS */ -# define SDRAM_MCRVALUE1 SDRAM_MCRVALUE0 /* ??? why not 0x80808130? */ -#else -# define SDRAM_MxMR_PTx 195 -# define UPM_MRS_ADDR 0x11 -# define UPM_REFRESH_ADDR 0x30 /* or 0x11 if we want to be like above? */ -#endif /* !SDRAM_ALT_INIT_SEQUENCE */ - -static const uint sdram_table[] = -{ - /* single read. (offset 0 in upm RAM) */ - 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x11adfc04, - 0xefbbbc00, 0x1ff77c45, _NOT_USED_, _NOT_USED_, - - /* burst read. (offset 8 in upm RAM) */ - 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x10adfc04, - 0xf0affc00, 0xf0affc00, 0xf1affc00, 0xefbbbc00, - 0x1ff77c45, - - /* precharge + MRS. (offset 11 in upm RAM) */ - 0xeffbbc04, 0x1ff77c34, 0xefeabc34, - 0x1fb57c35, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* single write. (offset 18 in upm RAM) */ - 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x01b93c04, - 0x1ff77c45, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* burst write. (offset 20 in upm RAM) */ - 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, - 0xf0affc00, 0xf0affc00, 0xe1bbbc04, 0x1ff77c45, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* refresh. (offset 30 in upm RAM) */ - 0xeffafc84, 0x1ff5fc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* exception. (offset 3c in upm RAM) */ - 0xeffffc06, 0x1ffffc07, _NOT_USED_, _NOT_USED_ }; - -#elif defined(CONFIG_SDRAM_50MHZ) - -/* ------------------------------------------------------------------------- */ -/* sdram table stolen from the fads manual */ -/* for chip MB811171622A-100 */ - -/* this table is for 32-50MHz operation */ -#ifdef SDRAM_ALT_INIT_SEQENCE -# define SDRAM_MBMRVALUE0 0x80802114 /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */ -# define SDRAM_MBMRVALUE1 0x80802118 /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=8 */ -# define SDRAM_MCRVALUE0 0x80808105 /* run upmb cs4 loop 1 addr 0x5 MRS */ -# define SDRAM_MCRVALUE1 0x80808130 /* run upmb cs4 loop 1 addr 0x30 REFRESH */ -# define SDRAM_MPTRVALUE 0x400 -#define SDRAM_MARVALUE 0x88 -#else -# define SDRAM_MxMR_PTx 128 -# define UPM_MRS_ADDR 0x5 -# define UPM_REFRESH_ADDR 0x30 -#endif /* !SDRAM_ALT_INIT_SEQUENCE */ - -static const uint sdram_table[] = -{ - /* single read. (offset 0 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, - - /* precharge + MRS. (offset 5 in upm RAM) */ - 0x1ff77c34, 0xefeabc34, 0x1fb57c35, - - /* burst read. (offset 8 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* single write. (offset 18 in upm RAM) */ - 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* burst write. (offset 20 in upm RAM) */ - 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* refresh. (offset 30 in upm RAM) */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* exception. (offset 3c in upm RAM) */ - 0x7ffffc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -/* ------------------------------------------------------------------------- */ -#else -#error SDRAM not correctly configured -#endif -/* ------------------------------------------------------------------------- */ - -/* - * Memory Periodic Timer Prescaler - */ - -#define SDRAM_OR4VALUE 0x00000a00 /* SAM,GL5A/S=01,addr mask or'ed on later */ -#define SDRAM_BR4VALUE 0x000000c1 /* UPMB,base addr or'ed on later */ - -/* ------------------------------------------------------------------------- */ -#ifdef SDRAM_ALT_INIT_SEQENCE -/* ------------------------------------------------------------------------- */ - -static int _initsdram(uint base, uint noMbytes) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint)); - - memctl->memc_mptpr = SDRAM_MPTPRVALUE; - - /* Configure the refresh (mostly). This needs to be - * based upon processor clock speed and optimized to provide - * the highest level of performance. For multiple banks, - * this time has to be divided by the number of banks. - * Although it is not clear anywhere, it appears the - * refresh steps through the chip selects for this UPM - * on each refresh cycle. - * We have to be careful changing - * UPM registers after we ask it to run these commands. - */ - - memctl->memc_mbmr = SDRAM_MBMRVALUE0; /* TLF 4 */ - memctl->memc_mar = SDRAM_MARVALUE; /* MRS code */ - - udelay(200); - - /* Now run the precharge/nop/mrs commands. - */ - - memctl->memc_mcr = 0x80808111; /* run umpb cs4 1 count 1, addr 0x11 ??? (50MHz) */ - /* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100MHz) */ - udelay(200); - - /* Run 8 refresh cycles */ - - memctl->memc_mcr = SDRAM_MCRVALUE0; /* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 MHz)*/ - /* run upmb cs4 loop 1 addr 0x11 precharge+MRS (100MHz) */ - - udelay(200); - - memctl->memc_mbmr = SDRAM_MBMRVALUE1; /* TLF 4 (100 MHz) or TLF 8 (50MHz) */ - memctl->memc_mcr = SDRAM_MCRVALUE1; /* run upmb cs4 loop 1 addr 0x30 refr (50 MHz) */ - /* run upmb cs4 loop 1 addr 0x11 precharge+MRS ??? (100MHz) */ - - udelay(200); - - memctl->memc_mbmr = SDRAM_MBMRVALUE0; /* TLF 4 */ - - memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1); - memctl->memc_br4 = SDRAM_BR4VALUE | base; - - return 0; -} - -/* ------------------------------------------------------------------------- */ -#else /* !SDRAM_ALT_INIT_SEQUENCE */ -/* ------------------------------------------------------------------------- */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -# define MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -# define MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -# define MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -# define MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MxMR settings for SDRAM - */ - -/* 8 column SDRAM */ -# define SDRAM_MxMR_8COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT) | MBMR_PTBE | \ - MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) -/* 9 column SDRAM */ -# define SDRAM_MxMR_9COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT) | MBMR_PTAE | \ - MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) - -static int _initsdram(uint base, uint noMbytes) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint)); - - memctl->memc_mptpr = MPTPR_2BK_4K; - memctl->memc_mbmr = SDRAM_MxMR_8COL & (~(MBMR_PTBE)); /* no refresh yet */ - - /* map CS 4 */ - memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1); - memctl->memc_br4 = SDRAM_BR4VALUE | base; - - /* Perform SDRAM initilization */ -# ifdef UPM_NOP_ADDR /* not currently in UPM table */ - /* step 1: nop */ - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | - MCR_MLCF(0) | UPM_NOP_ADDR; -# endif - - /* step 2: delay */ - udelay(200); - -# ifdef UPM_PRECHARGE_ADDR /* merged with MRS in UPM table */ - /* step 3: precharge */ - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | - MCR_MLCF(4) | UPM_PRECHARGE_ADDR; -# endif - - /* step 4: refresh */ - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | - MCR_MLCF(2) | UPM_REFRESH_ADDR; - - /* - * note: for some reason, the UPM values we are using include - * precharge with MRS - */ - - /* step 5: mrs */ - memctl->memc_mar = 0x00000088; - memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | - MCR_MLCF(1) | UPM_MRS_ADDR; - -# ifdef UPM_NOP_ADDR - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | - MCR_MLCF(0) | UPM_NOP_ADDR; -# endif - /* - * Enable refresh - */ - - memctl->memc_mbmr |= MBMR_PTBE; - return 0; -} -#endif /* !SDRAM_ALT_INIT_SEQUENCE */ - -/* ------------------------------------------------------------------------- */ - -static void _sdramdisable(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_br4 = 0x00000000; - - /* maybe we should turn off upmb here or something */ -} - -/* ------------------------------------------------------------------------- */ - -static int initsdram(uint base, uint *noMbytes) -{ - uint m = CONFIG_SYS_SDRAM_SIZE>>20; - - /* _initsdram needs access to sdram */ - *((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */ - - if(!_initsdram(base, m)) - { - *noMbytes += m; - return 0; - } - else - { - *((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */ - - _sdramdisable(); - - return -1; - } -} - -#endif /* CONFIG_FADS */ - -/* ========================================================================= */ - -phys_size_t initdram (int board_type) -{ - uint sdramsz = 0; /* size of sdram in Mbytes */ - uint m = 0; /* size of dram in Mbytes */ -#ifndef CONFIG_MPC885ADS - uint base = 0; /* base of dram in bytes */ - uint k, s; -#endif - -#ifdef CONFIG_FADS - if (!initsdram (0x00000000, &sdramsz)) { -#ifndef CONFIG_MPC885ADS - base = sdramsz << 20; -#endif - printf ("(%u MB SDRAM) ", sdramsz); - } -#endif -#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */ - k = (*((uint *) BCSR2) >> 23) & 0x0f; - - switch (k & 0x3) { - /* "MCM36100 / MT8D132X" */ - case 0x00: - m = 4; - break; - - /* "MCM36800 / MT16D832X" */ - case 0x01: - m = 32; - break; - /* "MCM36400 / MT8D432X" */ - case 0x02: - m = 16; - break; - /* "MCM36200 / MT16D832X ?" */ - case 0x03: - m = 8; - break; - - } - - switch (k >> 2) { - case 0x02: - k = 70; - break; - - case 0x03: - k = 60; - break; - - default: - printf ("unknown dramdelay (0x%x) - defaulting to 70 ns", k); - k = 70; - } - -#ifdef CONFIG_FADS - /* the FADS is missing this bit, all rams treated as non-edo */ - s = 0; -#else - s = (*((uint *) BCSR2) >> 27) & 0x01; -#endif - - if (!_draminit (base, m, s, k)) { - printf ("%dM %dns %sDRAM: ", m, k, s ? "EDO " : ""); - } else { - _dramdisable (); - m = 0; - } -#endif /* !CONFIG_MPC885ADS */ - m += sdramsz; /* add sdram size to total */ - - return (m << 20); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ========================================================================= */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ -#if defined(CONFIG_MPC86xADS) - puts ("Board: MPC86xADS\n"); -#elif defined(CONFIG_MPC885ADS) - puts ("Board: MPC885ADS\n"); -#else /* Only old ADS/FADS have got revision ID in BCSR3 */ - uint r = (((*((uint *) BCSR3) >> 23) & 1) << 3) - | (((*((uint *) BCSR3) >> 19) & 1) << 2) - | (((*((uint *) BCSR3) >> 16) & 3)); - - puts ("Board: "); -#if defined(CONFIG_FADS) - puts ("FADS"); - checkdboard (); -#else - puts ("ADS"); -#endif - - puts (" rev "); - - switch (r) { - case 0x00: - puts ("ENG\n"); - break; - case 0x01: - puts ("PILOT\n"); - break; - default: - printf ("unknown (0x%x)\n", r); - return -1; - } -#endif /* CONFIG_MPC86xADS */ - - return 0; -} - -/* ========================================================================= */ - -#if defined(CONFIG_CMD_PCMCIA) - -#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR -volatile unsigned char *pcmcia_mem = (unsigned char*)CONFIG_SYS_PCMCIA_MEM_ADDR; -#endif - -int pcmcia_init(void) -{ - volatile pcmconf8xx_t *pcmp; - uint v, slota = 0, slotb = 0; - - /* - ** Enable the PCMCIA for a Flash card. - */ - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - -#if 0 - pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_MEM_ADDR; - pcmp->pcmc_por0 = 0xc00ff05d; -#endif - - /* Set all slots to zero by default. */ - pcmp->pcmc_pgcra = 0; - pcmp->pcmc_pgcrb = 0; -#ifdef CONFIG_PCMCIA_SLOT_A - pcmp->pcmc_pgcra = 0x40; -#endif -#ifdef CONFIG_PCMCIA_SLOT_B - pcmp->pcmc_pgcrb = 0x40; -#endif - - /* enable PCMCIA buffers */ - *((uint *)BCSR1) &= ~BCSR1_PCCEN; - - /* Check if any PCMCIA card is plugged in. */ - -#ifdef CONFIG_PCMCIA_SLOT_A - slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ; -#endif -#ifdef CONFIG_PCMCIA_SLOT_B - slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ; -#endif - - if (!(slota || slotb)) { - printf("No card present\n"); - pcmp->pcmc_pgcra = 0; - pcmp->pcmc_pgcrb = 0; - return -1; - } - else - printf("Card present ("); - - v = 0; - - /* both the ADS and the FADS have a 5V keyed pcmcia connector (?) - ** - ** Paolo - Yes, but i have to insert some 3.3V card in that slot on - ** my FADS... :-) - */ - -#if defined(CONFIG_MPC86x) - switch ((pcmp->pcmc_pipr >> 30) & 3) -#elif defined(CONFIG_MPC823) || defined(CONFIG_MPC850) - switch ((pcmp->pcmc_pipr >> 14) & 3) -#endif - { - case 0x03 : - printf("5V"); - v = 5; - break; - case 0x01 : - printf("5V and 3V"); -#ifdef CONFIG_FADS - v = 3; /* User lower voltage if supported! */ -#else - v = 5; -#endif - break; - case 0x00 : - printf("5V, 3V and x.xV"); -#ifdef CONFIG_FADS - v = 3; /* User lower voltage if supported! */ -#else - v = 5; -#endif - break; - } - - switch (v) { -#ifdef CONFIG_FADS - case 3: - printf("; using 3V"); - /* - ** Enable 3 volt Vcc. - */ - *((uint *)BCSR1) &= ~BCSR1_PCCVCC1; - *((uint *)BCSR1) |= BCSR1_PCCVCC0; - break; -#endif - case 5: - printf("; using 5V"); -#ifdef CONFIG_FADS - /* - ** Enable 5 volt Vcc. - */ - *((uint *)BCSR1) &= ~BCSR1_PCCVCC0; - *((uint *)BCSR1) |= BCSR1_PCCVCC1; -#endif - break; - - default: - *((uint *)BCSR1) |= BCSR1_PCCEN; /* disable pcmcia */ - - printf("; unknown voltage"); - return -1; - } - printf(")\n"); - /* disable pcmcia reset after a while */ - - udelay(20); - -#ifdef CONFIG_PCMCIA_SLOT_A - pcmp->pcmc_pgcra = 0; -#endif -#ifdef CONFIG_PCMCIA_SLOT_B - pcmp->pcmc_pgcrb = 0; -#endif - - /* If you using a real hd you should give a short - * spin-up time. */ -#ifdef CONFIG_DISK_SPINUP_TIME - udelay(CONFIG_DISK_SPINUP_TIME); -#endif - - return 0; -} - -#endif - -/* ========================================================================= */ - -#ifdef CONFIG_SYS_PC_IDE_RESET - -void ide_set_reset(int on) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - /* - * Configure PC for IDE Reset Pin - */ - if (on) { /* assert RESET */ - immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET); - } else { /* release RESET */ - immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET; - } - - /* program port pin as GPIO output */ - immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET); - immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET); - immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET; -} - -#endif /* CONFIG_SYS_PC_IDE_RESET */ diff --git a/board/fads/fads.h b/board/fads/fads.h deleted file mode 100644 index 1be00b9048..0000000000 --- a/board/fads/fads.h +++ /dev/null @@ -1,468 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum, - * and Dan Malek - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * This header file contains values common to all FADS family boards. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/**************************************************************************** - * Flash Memory Map as used by U-Boot: - * - * Start Address Length - * +-----------------------+ 0xFE00_0000 Start of Flash ----------------- - * | | 0xFE00_0100 Reset Vector - * + + 0xFE0?_???? - * | U-Boot code | - * | | - * +-----------------------+ 0xFE04_0000 (sector border) - * | | - * | | - * | U-Boot environment | - * | | ^ - * | | | U-Boot - * +=======================+ 0xFE08_0000 (sector border) ----------------- - * | Available | | Applications - * | ... | v - * - *****************************************************************************/ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_NFSBOOTCOMMAND \ - "dhcp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ - "bootm" - -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ - "bootm fe080000" - -#undef CONFIG_BOOTARGS - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#if !defined(CONFIG_MPC885ADS) -#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#endif - -/* - * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options: - * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on - * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have - * got FEC so FEC is the default. - */ -#undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */ -#define CONFIG_FEC_ENET /* Use FEC ethernet */ - -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - -#ifdef CONFIG_FEC_ENET -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_MII_INIT 1 -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -#if !defined(FADS_COMMANDS_ALREADY_DEFINED) -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_PCMCIA -#define CONFIG_CMD_PING - -#endif - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP /* #undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */ -#define CONFIG_SYS_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ -/* - * 2048 SDRAM rows - * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CONFIG_SYS_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64)) -#elif defined(CONFIG_FADS) /* Old/new FADS */ -#define CONFIG_SYS_SDRAM_SIZE 0x00400000 /* 4 Mbyte */ -#else /* Old ADS */ -#define CONFIG_SYS_SDRAM_SIZE 0x00000000 /* No SDRAM */ -#endif - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#if (CONFIG_SYS_SDRAM_SIZE) -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE /* 1 ... SDRAM_SIZE */ -#else -#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#endif /* CONFIG_SYS_SDRAM_SIZE */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */ - -#ifdef CONFIG_BZIP2 -#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ -#else -#define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -/*----------------------------------------------------------------------- - * Flash organization - */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ -#define CONFIG_ENV_OFFSET CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment */ -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -#if defined(CONFIG_CMD_JFFS2) - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3" -#define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)" -*/ - -#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ - -/*----------------------------------------------------------------------- - * I2C configuration - */ -#if defined(CONFIG_CMD_I2C) -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address defaults */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR SCCR_TBS - -/*----------------------------------------------------------------------- - * DER - Debug Enable Register - *----------------------------------------------------------------------- - * Set to zero to prevent the processor from entering debug mode - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the entire - * address space, we have to set the memory controller differently. - * Normally, you write the option register first, and then enable the - * chip select by writing the base register. For CS0, you must write - * the base register first, followed by the option register. - */ - -/* - * Init Memory Controller: - * - * BR0/OR0 (Flash) - * BR1/OR1 (BCSR) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - -#define BCSR_ADDR ((uint) 0xFF080000) - -#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 8 Mbyte until detected */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_V ) - -/* BCSRx - Board Control and Status Registers */ -#define CONFIG_SYS_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */ -#define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V) - -/* values according to the manual */ - -#define BCSR0 ((uint) (BCSR_ADDR + 0x00)) -#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) -#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) -#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) -#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) - -/* - * (F)ADS bitvalues by Helmut Buchsbaum - * - * See User's Manual for a proper - * description of the following structures - */ - -#define BCSR0_ERB ((uint)0x80000000) -#define BCSR0_IP ((uint)0x40000000) -#define BCSR0_BDIS ((uint)0x10000000) -#define BCSR0_BPS_MASK ((uint)0x0C000000) -#define BCSR0_ISB_MASK ((uint)0x01800000) -#define BCSR0_DBGC_MASK ((uint)0x00600000) -#define BCSR0_DBPC_MASK ((uint)0x00180000) -#define BCSR0_EBDF_MASK ((uint)0x00060000) - -#define BCSR1_FLASH_EN ((uint)0x80000000) -#define BCSR1_DRAM_EN ((uint)0x40000000) -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDEN ((uint)0x10000000) -#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) -#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) -#define BCSR1_BCSR_EN ((uint)0x02000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVPP_MASK ((uint)0x00300000) -#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_SDRAM_EN ((uint)0x00020000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) - -#define BCSR1_PCCVCCON BCSR1_PCCVCC0 - -#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) -#define BCSR2_FLASH_PD_SHIFT 28 -#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT 23 -#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) -#define BCSR2_DBREVNR_MASK ((uint)0x00030000) - -#define BCSR3_DBID_MASK ((ushort)0x3800) -#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) -#define BCSR3_BREVNR0 ((ushort)0x0080) -#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) -#define BCSR3_BREVN1 ((ushort)0x0008) -#define BCSR3_BREVN2_MASK ((ushort)0x0003) - -#define BCSR4_ETHLOOP ((uint)0x80000000) -#define BCSR4_TFPLDL ((uint)0x40000000) -#define BCSR4_TPSQEL ((uint)0x20000000) -#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#if defined(CONFIG_MPC823) -#define BCSR4_USB_EN ((uint)0x08000000) -#define BCSR4_USB_SPEED ((uint)0x04000000) -#define BCSR4_VCCO ((uint)0x02000000) -#define BCSR4_VIDEO_ON ((uint)0x00800000) -#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) -#define BCSR4_VIDEO_RST ((uint)0x00200000) -#define BCSR4_MODEM_EN ((uint)0x00100000) -#define BCSR4_DATA_VOICE ((uint)0x00080000) -#elif defined(CONFIG_MPC850) -#define BCSR4_DATA_VOICE ((uint)0x00080000) -#elif defined(CONFIG_MPC860SAR) -#define BCSR4_UTOPIA_EN ((uint)0x08000000) -#else /* MPC860T and other chips with FEC */ -#define BCSR4_FETH_EN ((uint)0x08000000) -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#define BCSR4_FETHFDE ((uint)0x02000000) -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#define BCSR4_FETHRST ((uint)0x00200000) -#endif - -/* BSCR5 exists on MPC86xADS and MPC885ADS only */ - -#define CONFIG_SYS_PHYDEV_ADDR (BCSR_ADDR + 0x20000) - -#define BCSR5 (CONFIG_SYS_PHYDEV_ADDR + 0x300) - -#define BCSR5_MII2_EN 0x40 -#define BCSR5_MII2_RST 0x20 -#define BCSR5_T1_RST 0x10 -#define BCSR5_ATM155_RST 0x08 -#define BCSR5_ATM25_RST 0x04 -#define BCSR5_MII1_EN 0x02 -#define BCSR5_MII1_RST 0x01 - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_MAC_PARTITION 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_ISO_PARTITION 1 - -#undef CONFIG_ATAPI -#if 0 /* does not make sense when CONFIG_CMD_IDE is not enabled, too */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ -#endif -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 - -#define CONFIG_DISK_SPINUP_TIME 1000000 -/* #undef CONFIG_DISK_SPINUP_TIME */ /* usin Compact Flash */ diff --git a/board/fads/flash.c b/board/fads/flash.c deleted file mode 100644 index ea2f713ca6..0000000000 --- a/board/fads/flash.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -#define QUAD_ID(id) ((((ulong)(id) & 0xFF) << 24) | \ - (((ulong)(id) & 0xFF) << 16) | \ - (((ulong)(id) & 0xFF) << 8) | \ - (((ulong)(id) & 0xFF) << 0) \ - ) - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static int write_word (flash_info_t * info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - vu_long *bcsr = (vu_long *)BCSR_ADDR; - unsigned long pd_size, total_size, bsize, or_am; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].size = 0; - flash_info[i].sector_count = 0; - flash_info[i].start[0] = 0xFFFFFFFF; /* For TFTP */ - } - - switch ((bcsr[2] & BCSR2_FLASH_PD_MASK) >> BCSR2_FLASH_PD_SHIFT) { - case 2: - case 4: - case 6: - pd_size = 0x800000; - or_am = 0xFF800000; - break; - - case 5: - case 7: - pd_size = 0x400000; - or_am = 0xFFC00000; - break; - - case 8: - pd_size = 0x200000; - or_am = 0xFFE00000; - break; - - default: - pd_size = 0; - or_am = 0xFFE00000; - printf("## Unsupported flash detected by BCSR: 0x%08lX\n", bcsr[2]); - } - - total_size = 0; - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS && total_size < pd_size; ++i) { - bsize = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + total_size), - &flash_info[i]); - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, bsize, bsize >> 20); - } - - total_size += bsize; - } - - if (total_size != pd_size) { - printf("## Detected flash size %lu conflicts with PD data %lu\n", - total_size, pd_size); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = or_am | CONFIG_SYS_OR_TIMING_FLASH; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i) { -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - if (CONFIG_SYS_MONITOR_BASE >= flash_info[i].start[0]) - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[i]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - if (CONFIG_ENV_ADDR >= flash_info[i].start[0]) - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[i]); -#endif - } - - return total_size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_BM: - printf ("BRIGHT MICRO "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM080: - printf ("29F080 or 29LV080 (8 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: - printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - * The following code can not run from flash! - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info) -{ - short i; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; - - switch (addr[0]) { - case QUAD_ID(AMD_MANUFACT): - info->flash_id = FLASH_MAN_AMD; - break; - - case QUAD_ID(FUJ_MANUFACT): - info->flash_id = FLASH_MAN_FUJ; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - switch (addr[1]) { /* device ID */ - case QUAD_ID(AMD_ID_F040B): - case QUAD_ID(AMD_ID_LV040B): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00200000; - break; /* => 2 MB */ - - case QUAD_ID(AMD_ID_F080B): - info->flash_id += FLASH_AM080; - info->sector_count = 16; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif /* 0 */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - -#if 0 - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#else - /* set sector offsets for uniform sector type */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = (ulong)addr + (i * 0x00040000); -#endif - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *) (info->start[i]); - info->protect[i] = addr[2] & 1; - } - - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *) info->start[0]; - *addr = 0xF0F0F0F0; /* reset bank */ - } - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - vu_long *addr = (vu_long *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return ERR_INVAL; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type - aborted\n"); - return ERR_UNKNOWN_FLASH_TYPE; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x80808080; - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *) (info->start[sect]); - addr[0] = 0x30303030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long *) (info->start[l_sect]); - while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF) - { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return ERR_TIMOUT; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned long *) info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *) (info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *) dest) & data) != data) { - return ERR_NOT_ERASED; - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0xA0A0A0A0; - - *((vu_long *) dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *) dest) & 0x80808080) != (data & 0x80808080)) - { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return ERR_TIMOUT; - } - } - return (0); -} diff --git a/board/fads/lamp.c b/board/fads/lamp.c deleted file mode 100644 index ffcc2b3c41..0000000000 --- a/board/fads/lamp.c +++ /dev/null @@ -1,43 +0,0 @@ -#include <config.h> - -#include <common.h> - -void -signal_delay(unsigned int n) -{ - while (n--); -} - -void -signal_on(void) -{ - *((volatile uint *)BCSR4) &= ~(1<<(31-3)); /* led on */ -} - -void -signal_off(void) -{ - *((volatile uint *)BCSR4) |= (1<<(31-3)); /* led off */ -} - -void -slow_blink(unsigned int n) -{ - while (n--) { - signal_on(); - signal_delay(0x00400000); - signal_off(); - signal_delay(0x00400000); - } -} - -void -fast_blink(unsigned int n) -{ - while (n--) { - signal_on(); - signal_delay(0x00100000); - signal_off(); - signal_delay(0x00100000); - } -} diff --git a/board/fads/pcmcia.c b/board/fads/pcmcia.c deleted file mode 100644 index 996f032f64..0000000000 --- a/board/fads/pcmcia.c +++ /dev/null @@ -1,71 +0,0 @@ -#include <common.h> -#include <mpc8xx.h> -#include <pcmcia.h> - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#ifdef CONFIG_PCMCIA - -#define PCMCIA_BOARD_MSG "FADS" - -int pcmcia_voltage_set(int slot, int vcc, int vpp) -{ - u_long reg = 0; - - switch(vpp) { - case 0: reg = 0; break; - case 50: reg = 1; break; - case 120: reg = 2; break; - default: return 1; - } - - switch(vcc) { - case 0: reg = 0; break; -#ifdef CONFIG_FADS - case 33: reg = BCSR1_PCCVCC0 | BCSR1_PCCVCC1; break; - case 50: reg = BCSR1_PCCVCC1; break; -#endif - default: return 1; - } - - /* first, turn off all power */ - -#ifdef CONFIG_FADS - *((uint *)BCSR1) &= ~(BCSR1_PCCVCC0 | BCSR1_PCCVCC1); -#endif - *((uint *)BCSR1) &= ~BCSR1_PCCVPP_MASK; - - /* enable new powersettings */ - -#ifdef CONFIG_FADS - *((uint *)BCSR1) |= reg; -#endif - - *((uint *)BCSR1) |= reg << 20; - - return 0; -} - -int pcmcia_hardware_enable(int slot) -{ - *((uint *)BCSR1) &= ~BCSR1_PCCEN; - return 0; -} - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_hardware_disable(int slot) -{ - *((uint *)BCSR1) &= ~BCSR1_PCCEN; - return 0; -} -#endif - -#endif /* CONFIG_PCMCIA */ diff --git a/board/fads/u-boot.lds b/board/fads/u-boot.lds deleted file mode 100644 index 3123a888f1..0000000000 --- a/board/fads/u-boot.lds +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - /*. = DEFINED(env_offset) ? env_offset : .;*/ - common/env_embedded.o (.ppcenv*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} -ENTRY(_start) diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index b2d5378143..9d6b9a7b66 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -488,6 +488,9 @@ int configure_vsc3316_3308(void) } switch (serdes2_prtcl) { +#ifdef CONFIG_PPC_B4420 + case 0x9d: +#endif case 0x9E: case 0x9A: case 0x98: @@ -852,6 +855,9 @@ int config_serdes2_refclks(void) * For this SerDes2's Refclk1 need to be set to 100MHz */ switch (serdes2_prtcl) { +#ifdef CONFIG_PPC_B4420 + case 0x9d: +#endif case 0x9E: case 0x9A: case 0xb2: diff --git a/board/freescale/ls2085a/Makefile b/board/freescale/ls2085a/Makefile new file mode 100644 index 0000000000..701b35cd59 --- /dev/null +++ b/board/freescale/ls2085a/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2014 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls2085a.o +obj-y += ddr.o diff --git a/board/freescale/ls2085a/README b/board/freescale/ls2085a/README new file mode 100644 index 0000000000..b7023e1d48 --- /dev/null +++ b/board/freescale/ls2085a/README @@ -0,0 +1,16 @@ +Freescale ls2085a_emu + +This is a emulator target with limited peripherals. + +Memory map from core's view + +0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom +0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR +0x00_1800_0000 .. 0x00_181F_FFFF OCRAM +0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1 +0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1 +0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 +0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 + +Other addresses are either reserved, or not used directly by u-boot. +This list should be updated when more addresses are used. diff --git a/board/freescale/ls2085a/ddr.c b/board/freescale/ls2085a/ddr.c new file mode 100644 index 0000000000..257bc162d0 --- /dev/null +++ b/board/freescale/ls2085a/ddr.c @@ -0,0 +1,175 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 3) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + /* + * we use identical timing for all slots. If needed, change the code + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; + */ + if (popts->registered_dimm_en) + pbsp = rdimms[0]; + else + pbsp = udimms[0]; + + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for data rate %lu MT/s\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 1; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif +} + +#ifdef CONFIG_SYS_DDR_RAW_TIMING +dimm_params_t ddr_raw_timing = { + .n_ranks = 2, + .rank_density = 1073741824u, + .capacity = 2147483648, + .primary_sdram_width = 64, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 14, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tckmin_x_ps = 937, + .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */ + .taa_ps = 13090, + .twr_ps = 15000, + .trcd_ps = 13090, + .trrd_ps = 5000, + .trp_ps = 13090, + .tras_ps = 33000, + .trc_ps = 46090, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, + .refresh_rate_ps = 7800000, + .tfaw_ps = 25000, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR on board"; + + if (((controller_number == 0) && (dimm_number == 0)) || + ((controller_number == 1) && (dimm_number == 0))) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} +#endif +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing DDR...."); + + puts("using SPD\n"); + dram_size = fsl_ddr_sdram(); + + return dram_size; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; + } else { + gd->bd->bi_dram[0].size = gd->ram_size; + } +} diff --git a/board/freescale/ls2085a/ddr.h b/board/freescale/ls2085a/ddr.h new file mode 100644 index 0000000000..77f6aafe3d --- /dev/null +++ b/board/freescale/ls2085a/ddr.h @@ -0,0 +1,57 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 2140, 0, 4, 4, 0x0, 0x0}, + {1, 2140, 0, 4, 4, 0x0, 0x0}, + {} +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {4, 2140, 0, 5, 4, 0x0, 0x0}, + {2, 2140, 0, 5, 4, 0x0, 0x0}, + {1, 2140, 0, 4, 4, 0x0, 0x0}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +static const struct board_specific_parameters *rdimms[] = { + rdimm0, +}; + + +#endif diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c new file mode 100644 index 0000000000..a18db1d714 --- /dev/null +++ b/board/freescale/ls2085a/ls2085a.c @@ -0,0 +1,100 @@ +/* + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <netdev.h> +#include <fsl_ifc.h> +#include <fsl_ddr.h> +#include <asm/io.h> +#include <fdt_support.h> +#include <libfdt.h> +#include <fsl_mc.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + init_final_memctl_regs(); + return 0; +} + +int board_early_init_f(void) +{ + init_early_memctl_regs(); /* tighten IFC timing */ + + return 0; +} + +int dram_init(void) +{ + printf("DRAM: "); + gd->ram_size = initdram(0); + + return 0; +} + +int timer_init(void) +{ + u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; + u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; + + out_le32(cltbenr, 0x1); /* enable cluster0 timebase */ + out_le32(cntcr, 0x1); /* enable clock for timer */ + + return 0; +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ +} + +int board_eth_init(bd_t *bis) +{ + int error = 0; + +#ifdef CONFIG_SMC91111 + error = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + +#ifdef CONFIG_FSL_MC_ENET + error = cpu_eth_init(bis); +#endif + return error; +} + +#ifdef CONFIG_FSL_MC_ENET +void fdt_fixup_board_enet(void *fdt) +{ + int offset; + + offset = fdt_path_offset(fdt, "/fsl,dprc@0"); + if (get_mc_boot_status() == 0) + fdt_status_okay(fdt, offset); + else + fdt_status_fail(fdt, offset); +} +#endif + +#ifdef CONFIG_OF_BOARD_SETUP +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + /* limit the memory size to bank 1 until Linux can handle 40-bit PA */ + base = getenv_bootm_low(); + size = getenv_bootm_size(); + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_FSL_MC_ENET + fdt_fixup_board_enet(blob); +#endif +} +#endif diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c index 387e454cef..16bba59ba8 100644 --- a/board/freescale/m5253demo/flash.c +++ b/board/freescale/m5253demo/flash.c @@ -177,7 +177,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) { FPWV *addr; int flag, prot, sect, count; - ulong type, start, last; + ulong type, start; int rcode = 0, flashtype = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -217,7 +217,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) flag = disable_interrupts(); start = get_timer(0); - last = start; if ((s_last - s_first) == (CONFIG_SYS_SST_SECT - 1)) { if (prot == 0) { @@ -319,14 +318,13 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) { ulong wp, count; u16 data; - int rc, port_width; + int rc; if (info->flash_id == FLASH_UNKNOWN) return 4; /* get lower word aligned address */ wp = addr; - port_width = sizeof(FPW); /* handle unaligned start bytes */ if (wp & 1) { diff --git a/board/freescale/mpc8260ads/Makefile b/board/freescale/mpc8260ads/Makefile deleted file mode 100644 index 007d9580ae..0000000000 --- a/board/freescale/mpc8260ads/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mpc8260ads.o flash.o diff --git a/board/freescale/mpc8260ads/flash.c b/board/freescale/mpc8260ads/flash.c deleted file mode 100644 index 4012d45868..0000000000 --- a/board/freescale/mpc8260ads/flash.c +++ /dev/null @@ -1,476 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Add support the Sharp chips on the mpc8260ads. - * I started with board/ip860/flash.c and made changes I found in - * the MTD project by David Schleef. - * - * (C) Copyright 2003 Arabella Software Ltd. - * Yuli Barcohen <yuli@arabellasw.com> - * Re-written to support multi-bank flash SIMMs. - * Added support for real protection and JFFS2. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -/* Intel-compatible flash ID */ -#define INTEL_COMPAT 0x89898989 -#define INTEL_ALT 0xB0B0B0B0 - -/* Intel-compatible flash commands */ -#define INTEL_PROGRAM 0x10101010 -#define INTEL_ERASE 0x20202020 -#define INTEL_CLEAR 0x50505050 -#define INTEL_LOCKBIT 0x60606060 -#define INTEL_PROTECT 0x01010101 -#define INTEL_STATUS 0x70707070 -#define INTEL_READID 0x90909090 -#define INTEL_CONFIRM 0xD0D0D0D0 -#define INTEL_RESET 0xFFFFFFFF - -/* Intel-compatible flash status bits */ -#define INTEL_FINISHED 0x80808080 -#define INTEL_OK 0x80808080 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.) - * Up to 32MB of flash supported (up to 4 banks.) - * BCSR is used for flash presence detect (page 4-65 of the User's Manual) - * - * The following code can not run from flash! - */ -unsigned long flash_init (void) -{ - ulong size = 0, sect_start, sect_size = 0, bank_size; - ushort sect_count = 0; - int i, j, nbanks; - vu_long *addr = (vu_long *)CONFIG_SYS_FLASH_BASE; - vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR; - - switch (bcsr[2] & 0xF) { - case 0: - nbanks = 4; - break; - case 1: - nbanks = 2; - break; - case 2: - nbanks = 1; - break; - default: /* Unsupported configurations */ - nbanks = CONFIG_SYS_MAX_FLASH_BANKS; - } - - if (nbanks > CONFIG_SYS_MAX_FLASH_BANKS) - nbanks = CONFIG_SYS_MAX_FLASH_BANKS; - - for (i = 0; i < nbanks; i++) { - *addr = INTEL_READID; /* Read Intelligent Identifier */ - if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) { - switch (addr[1]) { - case SHARP_ID_28F016SCL: - case SHARP_ID_28F016SCZ: - flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; - sect_count = 32; - sect_size = 0x40000; - break; - default: - flash_info[i].flash_id = FLASH_UNKNOWN; - sect_count = CONFIG_SYS_MAX_FLASH_SECT; - sect_size = - CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS / CONFIG_SYS_MAX_FLASH_SECT; - } - } - else - flash_info[i].flash_id = FLASH_UNKNOWN; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n", - addr[0], addr[1], (ulong)addr); - size = 0; - *addr = INTEL_RESET; /* Reset bank to Read Array mode */ - break; - } - flash_info[i].sector_count = sect_count; - flash_info[i].size = bank_size = sect_size * sect_count; - size += bank_size; - sect_start = (ulong)addr; - for (j = 0; j < sect_count; j++) { - addr = (vu_long *)sect_start; - flash_info[i].start[j] = sect_start; - flash_info[i].protect[j] = (addr[2] == 0x01010101); - sect_start += sect_size; - } - *addr = INTEL_RESET; /* Reset bank to Read Array mode */ - addr = (vu_long *)sect_start; - } - - if (size == 0) { /* Unknown flash, fill with hard-coded values */ - sect_start = CONFIG_SYS_FLASH_BASE; - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].size = CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS; - flash_info[i].sector_count = sect_count; - for (j = 0; j < sect_count; j++) { - flash_info[i].start[j] = sect_start; - flash_info[i].protect[j] = 0; - sect_start += sect_size; - } - } - size = CONFIG_SYS_FLASH_SIZE; - } - else - for (i = nbanks; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].size = 0; - flash_info[i].sector_count = 0; - } - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - return (size); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_SHARP: printf ("Sharp "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); - break; - case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); - break; - case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); - break; - case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - - last = start = get_timer (0); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Clear Status Register */ - *addr = INTEL_CLEAR; - /* Single Block Erase Command */ - *addr = INTEL_ERASE; - /* Confirm */ - *addr = INTEL_CONFIRM; - - if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { - /* Resume Command, as per errata update */ - *addr = INTEL_CONFIRM; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = INTEL_RESET; /* reset bank */ - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - if (*addr != INTEL_OK) { - printf("Block erase failed at %08X, CSR=%08X\n", - (uint)addr, (uint)*addr); - *addr = INTEL_RESET; /* reset bank */ - return 1; - } - - /* reset to read mode */ - *addr = INTEL_RESET; - } - } - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - ulong start; - int rc = 0; - int flag; - vu_long *addr = (vu_long *)dest; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - - *addr = INTEL_CLEAR; /* Clear status register */ - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Write Command */ - *addr = INTEL_PROGRAM; - - /* Write Data */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - printf("Write timed out\n"); - rc = 1; - break; - } - } - if (*addr != INTEL_OK) { - printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr); - rc = 1; - } - - *addr = INTEL_RESET; /* Reset to read array mode */ - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - *(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - rc = write_word(info, wp, data); - - return rc; -} - -/*----------------------------------------------------------------------- - * Set/Clear sector's lock bit, returns: - * 0 - OK - * 1 - Error (timeout, voltage problems, etc.) - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - ulong start; - int i; - int rc = 0; - vu_long *addr = (vu_long *)(info->start[sector]); - int flag = disable_interrupts(); - - *addr = INTEL_CLEAR; /* Clear status register */ - if (prot) { /* Set sector lock bit */ - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - } - else { /* Clear sector lock bit */ - *addr = INTEL_LOCKBIT; /* All sectors lock bits */ - *addr = INTEL_CONFIRM; /* clear */ - } - - start = get_timer(0); - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) { - printf("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - - if (*addr != INTEL_OK) { - printf("Flash lock bit operation failed at %08X, CSR=%08X\n", - (uint)addr, (uint)*addr); - rc = 1; - } - - if (!rc) - info->protect[sector] = prot; - - /* - * Clear lock bit command clears all sectors lock bits, so - * we have to restore lock bits of protected sectors. - */ - if (!prot) - for (i = 0; i < info->sector_count; i++) - if (info->protect[i]) { - addr = (vu_long *)(info->start[i]); - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - udelay(CONFIG_SYS_FLASH_LOCK_TOUT * 1000); - } - - if (flag) - enable_interrupts(); - - *addr = INTEL_RESET; /* Reset to read array mode */ - - return rc; -} diff --git a/board/freescale/mpc8260ads/mpc8260ads.c b/board/freescale/mpc8260ads/mpc8260ads.c deleted file mode 100644 index b8c8ce9603..0000000000 --- a/board/freescale/mpc8260ads/mpc8260ads.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified during 2001 by - * Advanced Communications Technologies (Australia) Pty. Ltd. - * Howard Walker, Tuong Vu-Dinh - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Added support for the 16M dram simm on the 8260ads boards - * - * (C) Copyright 2003-2004 Arabella Software Ltd. - * Yuli Barcohen <yuli@arabellasw.com> - * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init. - * - * Copyright (c) 2005 MontaVista Software, Inc. - * Vitaly Bordug <vbordug@ru.mvista.com> - * Added support for PCI. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> -#include <asm/m8260_pci.h> -#include <i2c.h> -#include <spd.h> -#include <miiphy.h> -#ifdef CONFIG_PCI -#include <pci.h> -#endif -#ifdef CONFIG_OF_LIBFDT -#include <libfdt.h> -#include <fdt_support.h> -#endif - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1) -#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2) -#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3) - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ - /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ - /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ - /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ - /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ - /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ - /* PA9 */ { 0, 0, 0, 0, 0, 0 }, /* PA9 */ - /* PA8 */ { 0, 0, 0, 0, 0, 0 }, /* PA8 */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */ - /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */ - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ -#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS - /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC17 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */ - /* PC16 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */ -#else - /* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */ - /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ -#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ -#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */ -#else - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ -#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */ - /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ - /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -void reset_phy (void) -{ - vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR; - - /* Reset the PHY */ -#if CONFIG_SYS_PHY_ADDR == 0 - bcsr[1] &= ~(FETHIEN1 | FETH1_RST); - udelay(2); - bcsr[1] |= FETH1_RST; -#else - bcsr[3] &= ~(FETHIEN2 | FETH2_RST); - udelay(2); - bcsr[3] |= FETH2_RST; -#endif /* CONFIG_SYS_PHY_ADDR == 0 */ - udelay(1000); -#ifdef CONFIG_MII -#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS - /* - * Do not bypass Rx/Tx (de)scrambler (fix configuration error) - * Enable autonegotiation. - */ - bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, 16, 0x610); - bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR, - BMCR_ANENABLE | BMCR_ANRESTART); -#else - /* - * Ethernet PHY is configured (by means of configuration pins) - * to work at 10Mb/s only. We reconfigure it using MII - * to advertise all capabilities, including 100Mb/s, and - * restart autonegotiation. - */ - - /* Advertise all capabilities */ - bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_ADVERTISE, 0x01E1); - - /* Do not bypass Rx/Tx (de)scrambler */ - bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_FCSCOUNTER, 0x0000); - - bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR, - BMCR_ANENABLE | BMCR_ANRESTART); -#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */ -#endif /* CONFIG_MII */ -} - -#ifdef CONFIG_PCI -typedef struct pci_ic_s { - unsigned long pci_int_stat; - unsigned long pci_int_mask; -}pci_ic_t; -#endif - -int board_early_init_f (void) -{ - vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR; - -#ifdef CONFIG_PCI - volatile pci_ic_t* pci_ic = (pci_ic_t *) CONFIG_SYS_PCI_INT; - - /* mask alll the PCI interrupts */ - pci_ic->pci_int_mask |= 0xfff00000; -#endif -#if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1) - bcsr[1] &= ~RS232EN_1; -#endif -#if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1) - bcsr[1] &= ~RS232EN_2; -#endif - -#if CONFIG_ADSTYPE != CONFIG_SYS_8260ADS /* PCI mode can be selected */ -#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS - if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */ -#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */ - { - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; - immap->im_siu_conf.sc_siumcr = - (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) - | SIUMCR_LBPC01; - } -#endif /* CONFIG_ADSTYPE != CONFIG_SYS_8260ADS */ - - return 0; -} - -#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1) - -phys_size_t initdram (int board_type) -{ -#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS - long int msize = 32; -#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS - long int msize = 64; -#else - long int msize = 16; -#endif - -#ifndef CONFIG_SYS_RAMBOOT - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar *ramaddr, c = 0xff; - uint or; - uint psdmr; - uint psrt; - - int i; - - immap->im_siu_conf.sc_ppc_acr = 0x00000002; - immap->im_siu_conf.sc_ppc_alrh = 0x01267893; - immap->im_siu_conf.sc_tescr1 = 0x00004000; - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; -#ifdef CONFIG_SYS_LSDRAM_BASE - /* - Initialise local bus SDRAM only if the pins - are configured as local bus pins and not as PCI. - The configuration is determined by the HRCW. - */ - if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) { - memctl->memc_lsrt = CONFIG_SYS_LSRT; -#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS /* CS3 */ - memctl->memc_or3 = 0xFF803280; - memctl->memc_br3 = CONFIG_SYS_LSDRAM_BASE | 0x00001861; -#else /* CS4 */ - memctl->memc_or4 = 0xFFC01480; - memctl->memc_br4 = CONFIG_SYS_LSDRAM_BASE | 0x00001861; -#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */ - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000; - ramaddr = (uchar *) CONFIG_SYS_LSDRAM_BASE; - *ramaddr = c; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000; - for (i = 0; i < 8; i++) - *ramaddr = c; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000; - *ramaddr = c; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000; - } -#endif /* CONFIG_SYS_LSDRAM_BASE */ - - /* Init 60x bus SDRAM */ -#ifdef CONFIG_SPD_EEPROM - { - spd_eeprom_t spd; - uint pbi, bsel, rowst, lsb, tmp; - - i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd)); - - /* Bank-based interleaving is not supported for physical bank - sizes greater than 128MB which is encoded as 0x20 in SPD - */ - pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI; - msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */ - or = ~(msize - 1) << 20; /* SDAM */ - switch (spd.nbanks) { /* BPD */ - case 2: - bsel = 1; - break; - case 4: - bsel = 2; - or |= 0x00002000; - break; - case 8: - bsel = 3; - or |= 0x00004000; - break; - } - lsb = 3; /* For 64-bit port, lsb is 3 bits */ - - if (pbi) { /* Bus partition depends on interleaving */ - rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb); - or |= (rowst << 9); /* ROWST */ - } else { - rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb); - or |= ((rowst * 2 - 12) << 9); /* ROWST */ - } - or |= ((spd.nrow_addr - 9) << 6); /* NUMR */ - - psdmr = (pbi << 31); /* PBI */ - /* Bus multiplexing parameters */ - tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */ - psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */ - psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */ - - tmp = (31 - lsb - 10) - tmp; - /* Pin connected to SDA10 is (31 - lsb - 10). - rowst is multiplexed over (32 - (lsb + spd.nrow_addr)), - so (rowst + tmp) alternates with AP. - */ - if (pbi) /* Table 10-7 */ - psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */ - else - psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */ - - /* SDRAM device-specific parameters */ - tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */ - switch (tmp) { /* RFRC */ - case 1: - case 2: - psdmr |= (1 << 15); - break; - case 3: - case 4: - case 5: - case 6: - case 7: - case 8: - psdmr |= ((tmp - 2) << 15); - break; - default: - psdmr |= (7 << 15); - } - psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */ - psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */ - /* BL=0 because for 64-bit SDRAM burst length must be 4 */ - /* LDOTOPRE ??? */ - for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++) - tmp >>= 1; - switch (i) { /* WRC */ - case 0: - case 1: - psdmr |= (1 << 4); - break; - case 2: - case 3: - psdmr |= (i << 4); - break; - } - /* EAMUX=0 - no external address multiplexing */ - /* BUFCMD=0 - no external buffers */ - for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++) - tmp >>= 1; - psdmr |= i; /* CL */ - - switch (spd.refresh & 0x7F) { - case 1: - tmp = 3900; - break; - case 2: - tmp = 7800; - break; - case 3: - tmp = 31300; - break; - case 4: - tmp = 62500; - break; - case 5: - tmp = 125000; - break; - default: - tmp = 15625; - } - psrt = tmp / (1000000000 / CONFIG_8260_CLKIN * - ((memctl->memc_mptpr >> 8) + 1)) - 1; -#ifdef SPD_DEBUG - printf ("\nDIMM type: %-18.18s\n", spd.mpart); - printf ("SPD size: %d\n", spd.info_size); - printf ("EEPROM size: %d\n", 1 << spd.chip_size); - printf ("Memory type: %d\n", spd.mem_type); - printf ("Row addr: %d\n", spd.nrow_addr); - printf ("Column addr: %d\n", spd.ncol_addr); - printf ("# of rows: %d\n", spd.nrows); - printf ("Row density: %d\n", spd.row_dens); - printf ("# of banks: %d\n", spd.nbanks); - printf ("Data width: %d\n", - 256 * spd.dataw_msb + spd.dataw_lsb); - printf ("Chip width: %d\n", spd.primw); - printf ("Refresh rate: %02X\n", spd.refresh); - printf ("CAS latencies: %02X\n", spd.cas_lat); - printf ("Write latencies: %02X\n", spd.write_lat); - printf ("tRP: %d\n", spd.trp); - printf ("tRCD: %d\n", spd.trcd); - - printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt); -#endif /* SPD_DEBUG */ - } -#else /* !CONFIG_SPD_EEPROM */ - or = CONFIG_SYS_OR2; - psdmr = CONFIG_SYS_PSDMR; - psrt = CONFIG_SYS_PSRT; -#endif /* CONFIG_SPD_EEPROM */ - memctl->memc_psrt = psrt; - memctl->memc_or2 = or; - memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x00000041; - ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE; - memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */ - *ramaddr = c; - memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */ - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */ - *ramaddr = c; - memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */ - *ramaddr = c; -#endif /* CONFIG_SYS_RAMBOOT */ - - /* return total 60x bus SDRAM size */ - return (msize * 1024 * 1024); -} - -int checkboard (void) -{ -#if CONFIG_ADSTYPE == CONFIG_SYS_8260ADS - puts ("Board: Motorola MPC8260ADS\n"); -#elif CONFIG_ADSTYPE == CONFIG_SYS_8266ADS - puts ("Board: Motorola MPC8266ADS\n"); -#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS - puts ("Board: Motorola PQ2FADS-ZU\n"); -#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS - puts ("Board: Motorola MPC8272ADS\n"); -#else - puts ("Board: unknown\n"); -#endif - return 0; -} - -#ifdef CONFIG_PCI -struct pci_controller hose; - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif -} -#endif diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds index 61b83bfc63..8a4a8a2f07 100644 --- a/board/freescale/mx31ads/u-boot.lds +++ b/board/freescale/mx31ads/u-boot.lds @@ -70,6 +70,8 @@ SECTIONS *(.__rel_dyn_end) } + .hash : { *(.hash*) } + .end : { *(.__end) @@ -100,7 +102,7 @@ SECTIONS .dynbss : { *(.dynbss) } .dynstr : { *(.dynstr*) } .dynamic : { *(.dynamic*) } - .hash : { *(.hash*) } + .gnu.hash : { *(.gnu.hash) } .plt : { *(.plt*) } .interp : { *(.interp*) } .gnu : { *(.gnu*) } diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c index d8c87458e8..2b883c719e 100644 --- a/board/freescale/p1023rds/p1023rds.c +++ b/board/freescale/p1023rds/p1023rds.c @@ -182,11 +182,6 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); - /* By default NOR is on, and NAND is disabled */ -#ifdef CONFIG_NAND_U_BOOT - do_fixup_by_path_string(blob, "nor_flash", "status", "disabled"); - do_fixup_by_path_string(blob, "nand_flash", "status", "okay"); -#endif #ifdef CONFIG_HAS_FSL_DR_USB fdt_fixup_dr_usb(blob, bd); #endif diff --git a/board/freescale/p1023rds/tlb.c b/board/freescale/p1023rds/tlb.c index 8b2bf50799..3c92c14ae3 100644 --- a/board/freescale/p1023rds/tlb.c +++ b/board/freescale/p1023rds/tlb.c @@ -36,7 +36,6 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_4M, 1), -#ifndef CONFIG_NAND_SPL /* *W*G* - BCSR and NOR flash on local bus*/ /* This will be changed to *I*G* after relocation to RAM. */ SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS, @@ -79,7 +78,6 @@ struct fsl_e_tlb_entry tlb_table[] = { CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_1M, 1), -#endif /* *I*G - NAND */ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h index 9fc879a4ef..ed52fef621 100644 --- a/board/freescale/t208xqds/ddr.h +++ b/board/freescale/t208xqds/ddr.h @@ -25,21 +25,21 @@ struct board_specific_parameters { static const struct board_specific_parameters udimm0[] = { /* * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ - {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, - {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, - {2, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, - {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, - {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, - {2, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b}, - {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, - {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, - {1, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, - {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, - {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, - {1, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b}, + {2, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {2, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09}, + {2, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, + {2, 1700, 0, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, + {2, 1900, 0, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {2, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b}, + {1, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {1, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09}, + {1, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, + {1, 1700, 0, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 0, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {1, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b}, {} }; diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index d7a804d22a..5879198e4d 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -416,6 +416,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR); switch (srds_s1) { + case 0x1b: case 0x1c: case 0x95: case 0xa2: @@ -429,8 +430,11 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); break; + case 0x50: case 0x51: + case 0x5e: case 0x5f: + case 0x64: case 0x65: /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); @@ -439,6 +443,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); break; case 0x66: + case 0x67: /* * XFI does not need a PHY to work, but to avoid U-boot use * default PHY address which is zero to a MAC when it found @@ -453,6 +458,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_10GEC3, 6); fm_info_set_phy_address(FM1_10GEC4, 7); break; + case 0x6a: case 0x6b: fm_info_set_phy_address(FM1_10GEC1, 4); fm_info_set_phy_address(FM1_10GEC2, 5); @@ -470,6 +476,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); break; + case 0x70: case 0x71: /* SGMII in Slot3 */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); @@ -625,6 +632,7 @@ int board_eth_init(bd_t *bis) fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) || + (srds_s1 == 0x6a) || (srds_s1 == 0x70) || (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || (srds_s1 == 0x71)) { /* As XFI is in cage intead of a slot, so diff --git a/board/freescale/t208xqds/t2080_rcw.cfg b/board/freescale/t208xqds/t2080_rcw.cfg index c2ad0fda55..972dedc687 100644 --- a/board/freescale/t208xqds/t2080_rcw.cfg +++ b/board/freescale/t208xqds/t2080_rcw.cfg @@ -3,6 +3,6 @@ aa55aa55 010e0100 #SerDes Protocol: 0x66_0x16 #Core/DDR: 1533Mhz/2133MT/s 12100017 15000000 00000000 00000000 -66160002 00008400 e8104000 c1000000 +66150002 00008400 e8104000 c1000000 00000000 00000000 00000000 000307fc 00000000 00000000 00000000 00000004 diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 9cfc0bd7c3..135343949e 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -105,6 +105,7 @@ int brd_mux_lane_to_slot(void) /* SerDes1 is not enabled */ break; #if defined(CONFIG_T2080QDS) + case 0x1b: case 0x1c: case 0xa2: /* SD1(A:D) => SLOT3 SGMII @@ -126,6 +127,7 @@ int brd_mux_lane_to_slot(void) */ QIXIS_WRITE(brdcfg[12], 0x3a); break; + case 0x50: case 0x51: /* SD1(A:D) => SLOT3 XAUI * SD1(E) => SLOT1 PCIe4 @@ -140,6 +142,7 @@ int brd_mux_lane_to_slot(void) */ QIXIS_WRITE(brdcfg[12], 0xfe); break; + case 0x6a: case 0x6b: /* SD1(A:D) => XFI cage * SD1(E) => SLOT1 PCIe4 @@ -184,6 +187,7 @@ int brd_mux_lane_to_slot(void) QIXIS_WRITE(brdcfg[12], 0x1a); break; #elif defined(CONFIG_T2081QDS) + case 0x50: case 0x51: /* SD1(A:D) => SLOT2 XAUI * SD1(E) => SLOT1 PCIe4 x1 @@ -192,6 +196,7 @@ int brd_mux_lane_to_slot(void) QIXIS_WRITE(brdcfg[12], 0x98); QIXIS_WRITE(brdcfg[13], 0x70); break; + case 0x6a: case 0x6b: /* SD1(A:D) => XFI SFP Module * SD1(E) => SLOT1 PCIe4 x1 @@ -201,13 +206,6 @@ int brd_mux_lane_to_slot(void) QIXIS_WRITE(brdcfg[13], 0x70); break; case 0x6c: - /* SD1(A:B) => XFI SFP Module - * SD1(C:D) => SLOT2 SGMII - * SD1(E:H) => SLOT1 PCIe4 x4 - */ - QIXIS_WRITE(brdcfg[12], 0xe8); - QIXIS_WRITE(brdcfg[13], 0x0); - break; case 0x6d: /* SD1(A:B) => XFI SFP Module * SD1(C:D) => SLOT2 SGMII diff --git a/board/freescale/t208xrdb/t2080_rcw.cfg b/board/freescale/t208xrdb/t2080_rcw.cfg index cd62cc8641..15e1bf43dd 100644 --- a/board/freescale/t208xrdb/t2080_rcw.cfg +++ b/board/freescale/t208xrdb/t2080_rcw.cfg @@ -3,6 +3,6 @@ aa55aa55 010e0100 #SerDes Protocol: 0x66_0x16 #Core/DDR: 1533Mhz/1600MT/s 120c0017 15000000 00000000 00000000 -66160002 00008400 ec104000 c1000000 +66150002 00008400 ec104000 c1000000 00000000 00000000 00000000 000307fc 00000000 00000000 00000000 00000004 diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c index 24cf907430..6210e4618f 100644 --- a/board/freescale/t4qds/eth.c +++ b/board/freescale/t4qds/eth.c @@ -449,7 +449,9 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); break; + case 27: case 28: + case 35: case 36: /* SGMII in Slot1 and Slot2 */ fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); @@ -465,6 +467,7 @@ int board_eth_init(bd_t *bis) slot_qsgmii_phyaddr[1][2]); } break; + case 37: case 38: fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); @@ -479,8 +482,11 @@ int board_eth_init(bd_t *bis) slot_qsgmii_phyaddr[1][3]); } break; + case 39: case 40: + case 45: case 46: + case 47: case 48: fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); @@ -585,12 +591,17 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR); break; + case 6: case 7: + case 12: case 13: case 14: + case 15: case 16: + case 21: case 22: case 23: + case 24: case 25: case 26: /* XAUI/HiGig in Slot3, SGMII in Slot4 */ @@ -600,7 +611,9 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); break; + case 27: case 28: + case 35: case 36: /* SGMII in Slot3 and Slot4 */ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); @@ -612,6 +625,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]); fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]); break; + case 37: case 38: /* QSGMII in Slot3 and Slot4 */ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); @@ -623,8 +637,11 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]); fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]); break; + case 39: case 40: + case 45: case 46: + case 47: case 48: /* SGMII in Slot3 */ fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); @@ -637,8 +654,11 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); break; + case 49: case 50: + case 51: case 52: + case 53: case 54: fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index 79b770b488..fe1bc7f08d 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -354,14 +354,18 @@ int config_frontside_crossbar_vsc3316(void) FSL_CORENET2_RCWSR4_SRDS1_PRTCL; srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; switch (srds_prtcl_s1) { + case 37: case 38: /* swap first lane and third lane on slot1 */ vsc3316_fsm1_tx[0][1] = 14; vsc3316_fsm1_tx[6][1] = 0; vsc3316_fsm1_rx[1][1] = 2; vsc3316_fsm1_rx[6][1] = 13; + case 39: case 40: + case 45: case 46: + case 47: case 48: /* swap first lane and third lane on slot2 */ vsc3316_fsm1_tx[2][1] = 8; @@ -382,17 +386,24 @@ int config_frontside_crossbar_vsc3316(void) FSL_CORENET2_RCWSR4_SRDS2_PRTCL; srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; switch (srds_prtcl_s2) { + case 37: case 38: /* swap first lane and third lane on slot3 */ vsc3316_fsm2_tx[2][1] = 11; vsc3316_fsm2_tx[5][1] = 4; vsc3316_fsm2_rx[2][1] = 9; vsc3316_fsm2_rx[4][1] = 7; + case 39: case 40: + case 45: case 46: + case 47: case 48: + case 49: case 50: + case 51: case 52: + case 53: case 54: /* swap first lane and third lane on slot4 */ vsc3316_fsm2_tx[6][1] = 3; @@ -425,6 +436,7 @@ int config_backside_crossbar_mux(void) case 0: /* SerDes3 is not enabled */ break; + case 1: case 2: case 9: case 10: @@ -434,13 +446,20 @@ int config_backside_crossbar_mux(void) brdcfg |= BRDCFG12_SD3MX_SLOT5; QIXIS_WRITE(brdcfg[12], brdcfg); break; + case 3: case 4: + case 5: case 6: + case 7: case 8: + case 11: case 12: + case 13: case 14: + case 15: case 16: case 17: + case 18: case 19: case 20: /* SD3(4:7) => SLOT6(0:3) */ @@ -462,6 +481,7 @@ int config_backside_crossbar_mux(void) case 0: /* SerDes4 is not enabled */ break; + case 1: case 2: /* 10b, SD4(0:7) => SLOT7(0:7) */ brdcfg = QIXIS_READ(brdcfg[12]); @@ -469,8 +489,11 @@ int config_backside_crossbar_mux(void) brdcfg |= BRDCFG12_SD4MX_SLOT7; QIXIS_WRITE(brdcfg[12], brdcfg); break; + case 3: case 4: + case 5: case 6: + case 7: case 8: /* x1b, SD4(4:7) => SLOT8(0:3) */ brdcfg = QIXIS_READ(brdcfg[12]); @@ -478,9 +501,13 @@ int config_backside_crossbar_mux(void) brdcfg |= BRDCFG12_SD4MX_SLOT8; QIXIS_WRITE(brdcfg[12], brdcfg); break; + case 9: case 10: + case 11: case 12: + case 13: case 14: + case 15: case 16: case 18: /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */ diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg index 3e56817204..6f09a7bba2 100644 --- a/board/freescale/t4qds/t4_rcw.cfg +++ b/board/freescale/t4qds/t4_rcw.cfg @@ -1,7 +1,7 @@ #PBL preamble and RCW header aa55aa55 010e0100 -#serdes protocol 1_28_6_12 +#serdes protocol 1_27_5_11 16070019 18101916 00000000 00000000 -04383060 30548c00 ec020000 f5000000 +04362858 30548c00 ec020000 f5000000 00000000 ee0000ee 00000000 000307fc 00000000 00000000 00000000 00000028 diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c index d220475b5a..142c6a877b 100644 --- a/board/freescale/t4rdb/eth.c +++ b/board/freescale/t4rdb/eth.c @@ -67,7 +67,7 @@ int board_eth_init(bd_t *bis) /* Register the 10G MDIO bus */ fm_memac_mdio_init(bis, &tgec_mdio_info); - if (srds_prtcl_s1 == 28) { + if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) { /* SGMII */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1); fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2); diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg index 13408bd01f..fdbbe5ef65 100644 --- a/board/freescale/t4rdb/t4_rcw.cfg +++ b/board/freescale/t4rdb/t4_rcw.cfg @@ -1,7 +1,7 @@ #PBL preamble and RCW header aa55aa55 010e0100 -#serdes protocol 28_56_2_10 +#serdes protocol 27_56_1_9 16070019 18101916 00000000 00000000 -70701050 00448c00 6c020000 f5000000 +6c700848 00448c00 6c020000 f5000000 00000000 ee0000ee 00000000 000287fc 00000000 50000000 00000000 00000028 diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index d64d3aa872..54a9f2c7c3 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -278,6 +278,26 @@ static void setup_iomux_i2c(void) imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads)); } +static void setup_iomux_qspi(void) +{ + static const iomux_v3_cfg_t qspi0_pads[] = { + VF610_PAD_PTD0__QSPI0_A_QSCK, + VF610_PAD_PTD1__QSPI0_A_CS0, + VF610_PAD_PTD2__QSPI0_A_DATA3, + VF610_PAD_PTD3__QSPI0_A_DATA2, + VF610_PAD_PTD4__QSPI0_A_DATA1, + VF610_PAD_PTD5__QSPI0_A_DATA0, + VF610_PAD_PTD7__QSPI0_B_QSCK, + VF610_PAD_PTD8__QSPI0_B_CS0, + VF610_PAD_PTD9__QSPI0_B_DATA3, + VF610_PAD_PTD10__QSPI0_B_DATA2, + VF610_PAD_PTD11__QSPI0_B_DATA1, + VF610_PAD_PTD12__QSPI0_B_DATA0, + }; + + imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads)); +} + #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[1] = { {ESDHC1_BASE_ADDR}, @@ -321,7 +341,8 @@ static void clock_init(void) clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | - CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK); + CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK | + CCM_CCGR2_QSPI0_CTRL_MASK); clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, CCM_CCGR3_ANADIG_CTRL_MASK); clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, @@ -352,11 +373,14 @@ static void clock_init(void) CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | CCM_CACRR_ARM_CLK_DIV(0)); clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, - CCM_CSCMR1_ESDHC1_CLK_SEL(3)); + CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3)); clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, CCM_CSCDR1_RMII_CLK_EN); clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0)); + clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, + CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) | + CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3)); clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, CCM_CSCMR2_RMII_CLK_SEL(0)); } @@ -386,6 +410,7 @@ int board_early_init_f(void) setup_iomux_uart(); setup_iomux_enet(); setup_iomux_i2c(); + setup_iomux_qspi(); return 0; } diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c index 7a98e41d0a..1bac97027d 100644 --- a/board/gdsys/405ep/iocon.c +++ b/board/gdsys/405ep/iocon.c @@ -374,11 +374,12 @@ int last_stage_init(void) FPGA_GET_REG(0, fpga_features, &fpga_features); - if (!legacy) - ch0_rgmii2_present = !pca9698_get_value(0x20, 30); + if (!legacy) { + /* Turn on Parade DP501 */ + pca9698_direction_output(0x20, 9, 1); - print_fpga_info(0, ch0_rgmii2_present); - osd_probe(0); + ch0_rgmii2_present = !pca9698_get_value(0x20, 30); + } /* wait for FPGA done */ for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { @@ -408,13 +409,16 @@ int last_stage_init(void) } } - /* wait for slave-PLLs to be up and running */ + /* give slave-PLLs and Parade DP501 some time to be up and running */ udelay(500000); mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; slaves = mclink_probe(); mclink_fpgacount = 0; + print_fpga_info(0, ch0_rgmii2_present); + osd_probe(0); + if (slaves <= 0) return 0; diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c index 2f8e306261..3a075c471f 100644 --- a/board/gdsys/405ex/io64.c +++ b/board/gdsys/405ex/io64.c @@ -287,7 +287,7 @@ int last_stage_init(void) for (fpga = 0; fpga < 2; ++fpga) { for (k = 0; k < 32; ++k) { u16 status; - FPGA_GET_REG(k, ch[k].status_int, &status); + FPGA_GET_REG(fpga, ch[k].status_int, &status); if (!(status & (1 << 4))) { failed = 1; printf("fpga %d channel %d: no serdes lock\n", @@ -304,7 +304,7 @@ int last_stage_init(void) for (fpga = 0; fpga < 2; ++fpga) { for (k = 0; k < 32; ++k) { u16 status; - FPGA_GET_REG(k, hicb_ch[k].status_int, &status); + FPGA_GET_REG(fpga, hicb_ch[k].status_int, &status); if (status) printf("fpga %d hicb %d: hicb status %04x\n", fpga, k, status); diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index fb841e0b8f..7f8b4277eb 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -8,6 +8,6 @@ obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o obj-$(CONFIG_IO) += miiphybb.o obj-$(CONFIG_IO64) += miiphybb.o -obj-$(CONFIG_IOCON) += osd.o mclink.o +obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o obj-$(CONFIG_DLVISION_10G) += osd.o obj-$(CONFIG_CONTROLCENTERD) += dp501.o diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c index 52f3ea167f..7eb15ed0ba 100644 --- a/board/gdsys/common/dp501.c +++ b/board/gdsys/common/dp501.c @@ -54,14 +54,39 @@ static void dp501_link_training(u8 addr) void dp501_powerup(u8 addr) { dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */ + dp501_setbits(addr, 0x0a, 0x0e); /* block HDCP and MCCS on I2C bride*/ i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */ dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */ dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */ i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */ dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */ dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */ + dp501_clrbits(addr, 0x60, 0x20); /* Enable scrambling */ + +#ifdef CONFIG_SYS_DP501_VCAPCTRL0 + i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0); +#else i2c_reg_write(addr, 0x24, 0xc0); /* SDR mode 0, ext. H/VSYNC */ +#endif + +#ifdef CONFIG_SYS_DP501_DIFFERENTIAL + i2c_reg_write(addr + 2, 0x24, 0x10); /* clock input differential */ + i2c_reg_write(addr + 2, 0x25, 0x04); + i2c_reg_write(addr + 2, 0x26, 0x10); +#else i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */ +#endif + + i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */ + i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */ + i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */ + i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */ + i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */ + i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */ + dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */ + i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */ + i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */ + i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */ if (dp501_detect_cable_adapter(addr)) { printf("DVI/HDMI cable adapter detected\n"); @@ -69,16 +94,6 @@ void dp501_powerup(u8 addr) dp501_clrbits(addr, 0x00, 0x08); /* DVI/HDMI HDCP operation */ } else { printf("no DVI/HDMI cable adapter detected\n"); - i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */ - i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */ - i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */ - i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */ - i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */ - i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */ - dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */ - i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */ - i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */ - i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */ dp501_setbits(addr, 0x00, 0x08); /* for DP HDCP operation */ dp501_link_training(addr); diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index c49cd9a619..1c765e4cbf 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -9,6 +9,7 @@ #include <i2c.h> #include <malloc.h> +#include "dp501.h" #include <gdsys_fpga.h> #define CH7301_I2C_ADDR 0x75 @@ -24,6 +25,8 @@ #define SIL1178_MASTER_I2C_ADDRESS 0x38 #define SIL1178_SLAVE_I2C_ADDRESS 0x39 +#define DP501_I2C_ADDR 0x08 + #define PIXCLK_640_480_60 25180000 enum { @@ -54,51 +57,23 @@ u16 *buf; unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1; -#ifdef CONFIG_SYS_CH7301 -int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C; +#ifdef CONFIG_SYS_ICS8N3QV01_I2C +int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C; #endif -#if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178) -static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data) -{ - u16 val; - - do { - FPGA_GET_REG(screen, extended_interrupt, &val); - } while (val & (1 << 12)); - - FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg | (data << 8)); - FPGA_SET_REG(screen, i2c.write_mailbox, 0xc400 | (slave << 1)); -} +#ifdef CONFIG_SYS_CH7301_I2C +int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C; +#endif -static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg) -{ - unsigned int ctr = 0; - u16 val; - - do { - FPGA_GET_REG(screen, extended_interrupt, &val); - } while (val & (1 << 12)); - - FPGA_SET_REG(screen, extended_interrupt, 1 << 14); - FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg); - FPGA_SET_REG(screen, i2c.write_mailbox, 0xc000 | (slave << 1)); - - FPGA_GET_REG(screen, extended_interrupt, &val); - while (!(val & (1 << 14))) { - udelay(100000); - if (ctr++ > 5) { - printf("iic receive timeout\n"); - break; - } - FPGA_GET_REG(screen, extended_interrupt, &val); - } +#ifdef CONFIG_SYS_SIL1178_I2C +int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C; +#endif - FPGA_GET_REG(screen, i2c.read_mailbox_ext, &val); - return val >> 8; -} +#ifdef CONFIG_SYS_DP501_I2C +int dp501_i2c[] = CONFIG_SYS_DP501_I2C; #endif + #ifdef CONFIG_SYS_MPC92469AC static void mpc92469ac_calc_parameters(unsigned int fout, unsigned int *post_div, unsigned int *feedback_div) @@ -151,9 +126,9 @@ static void mpc92469ac_set(unsigned screen, unsigned int fout) } #endif -#ifdef CONFIG_SYS_ICS8N3QV01 +#ifdef CONFIG_SYS_ICS8N3QV01_I2C -static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index) +static unsigned int ics8n3qv01_get_fout_calc(unsigned index) { unsigned long long n; unsigned long long mint; @@ -164,11 +139,11 @@ static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index) if (index > 3) return 0; - reg_a = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0 + index); - reg_b = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 4 + index); - reg_c = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 8 + index); - reg_d = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 12 + index); - reg_f = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20 + index); + reg_a = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0 + index); + reg_b = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 4 + index); + reg_c = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 8 + index); + reg_d = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 12 + index); + reg_f = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20 + index); mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20); mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1) @@ -216,7 +191,7 @@ static void ics8n3qv01_calc_parameters(unsigned int fout, *_n = n; } -static void ics8n3qv01_set(unsigned screen, unsigned int fout) +static void ics8n3qv01_set(unsigned int fout) { unsigned int n; unsigned int mint; @@ -226,7 +201,7 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout) long long off_ppm; u8 reg0, reg4, reg8, reg12, reg18, reg20; - fout_calc = ics8n3qv01_get_fout_calc(screen, 1); + fout_calc = ics8n3qv01_get_fout_calc(1); off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000 / ICS8N3QV01_F_DEFAULT_1; printf(" PLL is off by %lld ppm\n", off_ppm); @@ -234,28 +209,28 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout) / ICS8N3QV01_F_DEFAULT_1; ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n); - reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0; + reg0 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0) & 0xc0; reg0 |= (mint & 0x1f) << 1; reg0 |= (mfrac >> 17) & 0x01; - fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0); + i2c_reg_write(ICS8N3QV01_I2C_ADDR, 0, reg0); reg4 = mfrac >> 9; - fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4); + i2c_reg_write(ICS8N3QV01_I2C_ADDR, 4, reg4); reg8 = mfrac >> 1; - fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8); + i2c_reg_write(ICS8N3QV01_I2C_ADDR, 8, reg8); reg12 = mfrac << 7; reg12 |= n & 0x7f; - fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12); + i2c_reg_write(ICS8N3QV01_I2C_ADDR, 12, reg12); - reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03; + reg18 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 18) & 0x03; reg18 |= 0x20; - fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18); + i2c_reg_write(ICS8N3QV01_I2C_ADDR, 18, reg18); - reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f; + reg20 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20) & 0x1f; reg20 |= mint & (1 << 5); - fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20); + i2c_reg_write(ICS8N3QV01_I2C_ADDR, 20, reg20); } #endif @@ -315,9 +290,9 @@ int osd_probe(unsigned screen) u16 version; u16 features; u8 value; -#ifdef CONFIG_SYS_CH7301 int old_bus = i2c_get_bus_num(); -#endif + bool pixclock_present = false; + bool output_driver_present = false; FPGA_GET_REG(0, osd.version, &version); FPGA_GET_REG(0, osd.features, &features); @@ -332,50 +307,76 @@ int osd_probe(unsigned screen) printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n", screen, version/100, version%100, base_width, base_height); -#ifdef CONFIG_SYS_CH7301 - i2c_set_bus_num(ch7301_i2c[screen]); - value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID); - if (value != 0x17) { - printf(" Probing CH7301 failed, DID %02x\n", value); - i2c_set_bus_num(old_bus); - return -1; - } - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0); - i2c_set_bus_num(old_bus); -#endif + /* setup pixclock */ #ifdef CONFIG_SYS_MPC92469AC + pixclock_present = true; mpc92469ac_set(screen, PIXCLK_640_480_60); #endif -#ifdef CONFIG_SYS_ICS8N3QV01 - ics8n3qv01_set(screen, PIXCLK_640_480_60); +#ifdef CONFIG_SYS_ICS8N3QV01_I2C + i2c_set_bus_num(ics8n3qv01_i2c[screen]); + if (!i2c_probe(ICS8N3QV01_I2C_ADDR)) { + ics8n3qv01_set(PIXCLK_640_480_60); + pixclock_present = true; + } #endif -#ifdef CONFIG_SYS_SIL1178 - value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02); - if (value != 0x06) { - printf(" Probing CH7301 SIL1178, DEV_IDL %02x\n", value); - return -1; + if (!pixclock_present) + printf(" no pixelclock found\n"); + + /* setup output driver */ + +#ifdef CONFIG_SYS_CH7301_I2C + i2c_set_bus_num(ch7301_i2c[screen]); + if (!i2c_probe(CH7301_I2C_ADDR)) { + value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID); + if (value == 0x17) { + i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08); + i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16); + i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60); + i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09); + i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0); + output_driver_present = true; + } + } +#endif + +#ifdef CONFIG_SYS_SIL1178_I2C + i2c_set_bus_num(sil1178_i2c[screen]); + if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) { + value = i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02); + if (value == 0x06) { + /* + * magic initialization sequence, + * adapted from datasheet + */ + i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37); + output_driver_present = true; + } } - /* magic initialization sequence adapted from datasheet */ - fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36); - fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44); - fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c); - fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10); - fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80); - fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30); - fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89); - fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60); - fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36); - fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37); #endif - FPGA_SET_REG(screen, videocontrol, 0x0002); +#ifdef CONFIG_SYS_DP501_I2C + i2c_set_bus_num(dp501_i2c[screen]); + if (!i2c_probe(DP501_I2C_ADDR)) { + dp501_powerup(DP501_I2C_ADDR); + output_driver_present = true; + } +#endif + + if (!output_driver_present) + printf(" no output driver found\n"); + FPGA_SET_REG(screen, osd.control, 0x0049); FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1)); @@ -385,6 +386,8 @@ int osd_probe(unsigned screen) if (screen > max_osd_screen) max_osd_screen = screen; + i2c_set_bus_num(old_bus); + return 0; } diff --git a/board/gdsys/p1022/controlcenterd-id.c b/board/gdsys/p1022/controlcenterd-id.c index 3fca3c53b2..70eff912aa 100644 --- a/board/gdsys/p1022/controlcenterd-id.c +++ b/board/gdsys/p1022/controlcenterd-id.c @@ -30,7 +30,7 @@ #include <i2c.h> #include <mmc.h> #include <tpm.h> -#include <sha1.h> +#include <u-boot/sha1.h> #include <asm/byteorder.h> #include <asm/unaligned.h> #include <pca9698.h> @@ -86,6 +86,11 @@ enum { ESDHC_BOOT_IMAGE_ENTRY_OFS = 0x60, }; +enum { + I2C_SOC_0 = 0, + I2C_SOC_1 = 1, +}; + struct key_program { uint32_t magic; uint32_t code_crc; @@ -1156,7 +1161,7 @@ static void ccdm_hang(void) int j; #endif - I2C_SET_BUS(0); + I2C_SET_BUS(I2C_SOC_0); pca9698_direction_output(0x22, 0, 0); /* Finder */ pca9698_direction_output(0x22, 4, 0); /* Status */ @@ -1189,8 +1194,8 @@ int startup_ccdm_id_module(void) int result = 0; unsigned int orig_i2c_bus; - orig_i2c_bus = I2C_GET_BUS(); - I2C_SET_BUS(1); + orig_i2c_bus = i2c_get_bus_num(); + i2c_set_bus_num(I2C_SOC_1); /* goto end; */ @@ -1216,7 +1221,7 @@ int startup_ccdm_id_module(void) failure: result = 1; end: - I2C_SET_BUS(orig_i2c_bus); + i2c_set_bus_num(orig_i2c_bus); if (result) ccdm_hang(); diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c index 8ccd9ce6ba..f76d968962 100644 --- a/board/gdsys/p1022/controlcenterd.c +++ b/board/gdsys/p1022/controlcenterd.c @@ -221,11 +221,7 @@ void hw_watchdog_reset(void) #ifdef CONFIG_TRAILBLAZER int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - int rcode = 0; - - if (run_command(getenv("bootcmd"), flag) < 0) - rcode = 1; - return rcode; + return run_command(getenv("bootcmd"), flag); } int board_early_init_r(void) @@ -386,9 +382,9 @@ static void hydra_initialize(void) fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); - versions = readl(fpga->versions); - fpga_version = readl(fpga->fpga_version); - fpga_features = readl(fpga->fpga_features); + versions = readl(&fpga->versions); + fpga_version = readl(&fpga->fpga_version); + fpga_features = readl(&fpga->fpga_features); hardware_version = versions & 0xf; feature_uart_channels = (fpga_features >> 6) & 0x1f; diff --git a/board/gdsys/p1022/sdhc_boot.c b/board/gdsys/p1022/sdhc_boot.c index e4323181fc..fd0e910d7b 100644 --- a/board/gdsys/p1022/sdhc_boot.c +++ b/board/gdsys/p1022/sdhc_boot.c @@ -32,7 +32,7 @@ #define ESDHC_BOOT_IMAGE_SIZE 0x48 #define ESDHC_BOOT_IMAGE_ADDR 0x50 -int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr) +int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) { u8 *tmp_buf; u32 blklen, code_offset, code_len, n; diff --git a/board/hidden_dragon/Makefile b/board/hidden_dragon/Makefile deleted file mode 100644 index eb1c5fdf86..0000000000 --- a/board/hidden_dragon/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = hidden_dragon.o flash.o diff --git a/board/hidden_dragon/README b/board/hidden_dragon/README deleted file mode 100644 index 529fe2be0e..0000000000 --- a/board/hidden_dragon/README +++ /dev/null @@ -1,60 +0,0 @@ -U-Boot for Hidden Dragon board ------------------------------- - -Hidden Dragon is a MPC824x-based board by Motorola. For the most -part it is similar to Sandpoint8245 board. So unless otherwise -mentioned, the codes in this directory are adapted from ../sandpoint -directory. - -Apparently there are very few of this board out there. Even Motorola -website does not have any info on it. - -RAM: - start = 0x0000 0000 - size = 0x0200 0000 (32 MB) - -Flash: - BANK ONE: - start = 0xFFE0 0000 - size = 0x0020 0000 (2 MB) - flash chip = 29LV160TE (1x16 Mbits or 2x8 Mbits) - flash sectors = 16K, 2x8K, 32K, 31x64K - - BANK TWO: - NONE - -The processor interrupt vectors reside on the first 256 bytes -starting from address 0xFFF00000. The "reset vector" (first -instruction executed after reset) is located on 0xFFF0 0100. - -U-Boot is configured to reside in flash starting at the address of -0xFFF00000. The environment space is located in flash separately from -U-Boot, at the second sector of the first flash bank, starting from -0xFFE04000 until 0xFFE06000 (8KB). - -Network: - - RTL8139 chip on the base board (SUPPORTED) - - RTL8129 chip on the processor board (NOT SUPPORTED) - -Serial: - - Two NS16550 compatible UART on the processor board (SUPPORTED) - - One NS16550 compatible UART on the base board (UNTESTED) - -Misc: - VIA686A PCI SuperIO peripheral controller - - 2 USB ports (UNTESTED) - - 2 PS2 ports (UNTESTED) - - Parallel port (UNTESTED) - - IDE & floppy interface (UNTESTED) - - S3 Savage4 video card (UNTESTED) - -TODO: ------ -- Support for the VIA686A based peripherals -- The RTL8139 driver frequently gives rx error. -- Support for RTL8129 network controller. (Why is the support removed from - rtl8139.c driver?) - -(C) Copyright 2004 -Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com diff --git a/board/hidden_dragon/flash.c b/board/hidden_dragon/flash.c deleted file mode 100644 index fc91a03aed..0000000000 --- a/board/hidden_dragon/flash.c +++ /dev/null @@ -1,559 +0,0 @@ -/* - * (C) Copyright 2004 - * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com - * - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> -#include <asm/processor.h> -#include <asm/pci_io.h> -#include <w83c553f.h> - -#define ROM_CS0_START 0xFF800000 -#define ROM_CS1_START 0xFF000000 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*flash command address offsets*/ - -#define ADDR0 (0xAAA) -#define ADDR1 (0x555) -#define ADDR3 (0x001) - -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------- - */ - -static unsigned long flash_id (unsigned char mfct, unsigned char chip) - __attribute__ ((const)); - -typedef struct { - FLASH_WORD_SIZE extval; - unsigned short intval; -} map_entry; - -static unsigned long flash_id (unsigned char mfct, unsigned char chip) -{ - static const map_entry mfct_map[] = { - {(FLASH_WORD_SIZE) AMD_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)}, - {(FLASH_WORD_SIZE) FUJ_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)}, - {(FLASH_WORD_SIZE) STM_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)}, - {(FLASH_WORD_SIZE) MT_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)}, - {(FLASH_WORD_SIZE) INTEL_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}, - {(FLASH_WORD_SIZE) INTEL_ALT_MANU, - (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)} - }; - - static const map_entry chip_map[] = { - {AMD_ID_F040B, FLASH_AM040}, - {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB} - }; - - const map_entry *p; - unsigned long result = FLASH_UNKNOWN; - - /* find chip id */ - for (p = &chip_map[0]; - p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++) - if (p->extval == chip) { - result = FLASH_VENDMASK | p->intval; - break; - } - - /* find vendor id */ - for (p = &mfct_map[0]; - p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++) - if (p->extval == mfct) { - result &= ~FLASH_VENDMASK; - result |= (unsigned long) p->intval << 16; - break; - } - - return result; -} - -unsigned long flash_init (void) -{ - unsigned long i; - unsigned char j; - static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - flash_info_t *const pflinfo = &flash_info[i]; - - pflinfo->flash_id = FLASH_UNKNOWN; - pflinfo->size = 0; - pflinfo->sector_count = 0; - } - - /* Enable writes to Hidden Dragon flash */ - { - register unsigned char temp; - - CONFIG_READ_BYTE (CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, - temp); - temp &= ~0x20; /* clear BIOSWP bit */ - CONFIG_WRITE_BYTE (CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, - temp); - } - - for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) { - flash_info_t *const pflinfo = &flash_info[i]; - const unsigned long base_address = flash_banks[i]; - volatile FLASH_WORD_SIZE *const flash = - (FLASH_WORD_SIZE *) base_address; - - flash[0xAAA << (3 * i)] = 0xaa; - flash[0x555 << (3 * i)] = 0x55; - flash[0xAAA << (3 * i)] = 0x90; - __asm__ __volatile__ ("sync"); - - pflinfo->flash_id = - flash_id (flash[0x0], flash[0x2 + 14 * i]); - - switch (pflinfo->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - pflinfo->size = 0x00080000; - pflinfo->sector_count = 8; - for (j = 0; j < 8; j++) { - pflinfo->start[j] = - base_address + 0x00010000 * j; - pflinfo->protect[j] = flash[(j << 16) | 0x2]; - } - break; - case FLASH_STM800AB: - pflinfo->size = 0x00100000; - pflinfo->sector_count = 19; - pflinfo->start[0] = base_address; - pflinfo->start[1] = base_address + 0x4000; - pflinfo->start[2] = base_address + 0x6000; - pflinfo->start[3] = base_address + 0x8000; - for (j = 1; j < 16; j++) { - pflinfo->start[j + 3] = - base_address + 0x00010000 * j; - } - break; - default: - /* The chip used is not listed in flash_id - TODO: Change this to explicitly detect the flash type - */ - { - int sector_addr = base_address; - - pflinfo->size = 0x00200000; - pflinfo->sector_count = 35; - pflinfo->start[0] = sector_addr; - sector_addr += 0x4000; /* 16K */ - pflinfo->start[1] = sector_addr; - sector_addr += 0x2000; /* 8K */ - pflinfo->start[2] = sector_addr; - sector_addr += 0x2000; /* 8K */ - pflinfo->start[3] = sector_addr; - sector_addr += 0x8000; /* 32K */ - - for (j = 4; j < 35; j++) { - pflinfo->start[j] = sector_addr; - sector_addr += 0x10000; /* 64K */ - } - } - break; - } - /* Protect monitor and environment sectors - */ -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - /* reset device to read mode */ - flash[0x0000] = 0xf0; - __asm__ __volatile__ ("sync"); - } - - /* only have 1 bank */ - return flash_info[0].size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - static const char unk[] = "Unknown"; - const char *mfct = unk, *type = unk; - unsigned int i; - - if (info->flash_id != FLASH_UNKNOWN) { - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - mfct = "AMD"; - break; - case FLASH_MAN_FUJ: - mfct = "FUJITSU"; - break; - case FLASH_MAN_STM: - mfct = "STM"; - break; - case FLASH_MAN_SST: - mfct = "SST"; - break; - case FLASH_MAN_BM: - mfct = "Bright Microelectonics"; - break; - case FLASH_MAN_INTEL: - mfct = "Intel"; - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - type = "AM29F040B (512K * 8, uniform sector size)"; - break; - case FLASH_AM400B: - type = "AM29LV400B (4 Mbit, bottom boot sect)"; - break; - case FLASH_AM400T: - type = "AM29LV400T (4 Mbit, top boot sector)"; - break; - case FLASH_AM800B: - type = "AM29LV800B (8 Mbit, bottom boot sect)"; - break; - case FLASH_AM800T: - type = "AM29LV800T (8 Mbit, top boot sector)"; - break; - case FLASH_AM160T: - type = "AM29LV160T (16 Mbit, top boot sector)"; - break; - case FLASH_AM320B: - type = "AM29LV320B (32 Mbit, bottom boot sect)"; - break; - case FLASH_AM320T: - type = "AM29LV320T (32 Mbit, top boot sector)"; - break; - case FLASH_STM800AB: - type = "M29W800AB (8 Mbit, bottom boot sect)"; - break; - case FLASH_SST800A: - type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; - break; - case FLASH_SST160A: - type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; - break; - } - } - - printf ("\n Brand: %s Type: %s\n" - " Size: %lu KB in %d Sectors\n", - mfct, type, info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; i++) { - unsigned long size; - unsigned int erased; - unsigned long *flash = (unsigned long *) info->start[i]; - - /* - * Check if whole sector is erased - */ - size = (i != (info->sector_count - 1)) ? - (info->start[i + 1] - info->start[i]) >> 2 : - (info->start[0] + info->size - info->start[i]) >> 2; - - for (flash = (unsigned long *) info->start[i], erased = 1; - (flash != (unsigned long *) info->start[i] + size) - && erased; flash++) - erased = *flash == ~0x0UL; - - printf ("%s %08lX %s %s", - (i % 5) ? "" : "\n ", - info->start[i], - erased ? "E" : " ", info->protect[i] ? "RO" : " "); - } - - puts ("\n"); - return; -} - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - unsigned char sh8b; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) - && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (FLASH_WORD_SIZE *) (info->start[0] + - ((info->start[sect] - - info->start[0]) << sh8b)); - if (info->flash_id & FLASH_MAN_SST) { - addr[ADDR0 << sh8b] = - (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = - (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0 << sh8b] = - (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0 << sh8b] = - (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = - (FLASH_WORD_SIZE) 0x00550055; - addr[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ - udelay (30000); /* wait 30 ms */ - } else - addr[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] - - info-> - start[0]) << sh8b)); - while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != - (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0]; - volatile FLASH_WORD_SIZE *dest2; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int flag; - int i; - unsigned char sh8b; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) - && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) + - info->start[0]); - - /* Check if Flash is (sufficiently) erased */ - if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i << sh8b] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} diff --git a/board/hidden_dragon/hidden_dragon.c b/board/hidden_dragon/hidden_dragon.c deleted file mode 100644 index 8d47f37955..0000000000 --- a/board/hidden_dragon/hidden_dragon.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2004 - * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com - * - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> -#include <pci.h> -#include <netdev.h> - -int checkboard (void) -{ - /*TODO: Check processor type */ - - puts ( "Board: Hidden Dragon " -#ifdef CONFIG_MPC8240 - "8240" -#endif -#ifdef CONFIG_MPC8245 - "8245" -#endif - " ##Test not implemented yet##\n"); - /* TODO: Implement board test */ - return 0; -} - -phys_size_t initdram (int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices, report devices found. - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_hidden_dragon_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_hidden_dragon_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/hymod/hymod.c b/board/hymod/hymod.c index 5fec914f5a..0183f781de 100644 --- a/board/hymod/hymod.c +++ b/board/hymod/hymod.c @@ -8,6 +8,8 @@ */ #include <common.h> +#include <bootretry.h> +#include <cli.h> #include <mpc8260.h> #include <mpc8260_irq.h> #include <ioports.h> @@ -413,13 +415,11 @@ last_stage_init (void) hymod_conf_t *cp = &gd->bd->bi_hymod_conf; int rc; -#ifdef CONFIG_BOOT_RETRY_TIME /* - * we use the readline () function, but we also want + * we use the cli_readline() function, but we also want * command timeout enabled */ - init_cmd_timeout (); -#endif + bootretry_init_cmd_timeout(); memset ((void *) cp, 0, sizeof (*cp)); diff --git a/board/hymod/input.c b/board/hymod/input.c index 184902cde5..a9035d3405 100644 --- a/board/hymod/input.c +++ b/board/hymod/input.c @@ -6,6 +6,8 @@ */ #include <common.h> +#include <bootretry.h> +#include <cli.h> int hymod_get_serno (const char *prompt) @@ -14,11 +16,9 @@ hymod_get_serno (const char *prompt) int n, serno; char *p; -#ifdef CONFIG_BOOT_RETRY_TIME - reset_cmd_timeout (); -#endif + bootretry_reset_cmd_timeout(); - n = readline (prompt); + n = cli_readline(prompt); if (n < 0) return (n); @@ -42,11 +42,9 @@ hymod_get_ethaddr (void) for (;;) { int n; -#ifdef CONFIG_BOOT_RETRY_TIME - reset_cmd_timeout (); -#endif + bootretry_reset_cmd_timeout(); - n = readline ("Enter board ethernet address: "); + n = cli_readline("Enter board ethernet address: "); if (n < 0) return (n); diff --git a/board/ispan/Makefile b/board/ispan/Makefile deleted file mode 100644 index 39931fdfd6..0000000000 --- a/board/ispan/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2004 Arabella Software Ltd. -# Yuli Barcohen <yuli@arabellasw.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := ispan.o diff --git a/board/ispan/ispan.c b/board/ispan/ispan.c deleted file mode 100644 index c610c3bd7e..0000000000 --- a/board/ispan/ispan.c +++ /dev/null @@ -1,448 +0,0 @@ -/* - * Copyright (C) 2004 Arabella Software Ltd. - * Yuli Barcohen <yuli@arabellasw.com> - * - * Support for Interphase iSPAN Communications Controllers - * (453x and others). Tested on 4532. - * - * Derived from iSPAN 4539 port (iphase4539) by - * Wolfgang Grandegger <wg@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> -#include <asm/io.h> - -/* - * I/O Ports configuration table - * - * If conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1) -#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2) -#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3) - -const iop_conf_t iop_conf_tab[4][32] = { - /* Port A */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ - /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ - /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ - /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ - /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ - /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 SMTXD */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 SMRXD */ - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ - /* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ - /* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ - /* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ - /* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ - /* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ - /* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ - /* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ - /* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ - /* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ - /* PB7 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ - /* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ - /* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ - /* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */ - /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */ - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ - /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */ - /* PC18 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Rx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Tx Clock (CLK16) */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 } /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */ - /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */ - /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPICLK */ - /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMOSI */ - /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMISO */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* MII MDIO */ - /* PD12 */ { 1, 0, 0, 1, 0, 0 }, /* MII MDC */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 SMTXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 SMRXD */ - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { CONFIG_SYS_FCC3, 0, 0, 1, 0, 1 }, /* MII PHY Reset */ - /* PD5 */ { CONFIG_SYS_FCC3, 0, 0, 1, 0, 0 }, /* MII PHY Enable */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -#define PSPAN_ADDR 0xF0020000 -#define EEPROM_REG 0x408 -#define EEPROM_READ_CMD 0xA000 -#define PSPAN_WRITE(a,v) \ - *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio() -#define PSPAN_READ(a) \ - *((volatile unsigned long *)(PSPAN_ADDR+(a))) - -static int seeprom_read (int addr, uchar * data, int size) -{ - ulong val, cmd; - int i; - - for (i = 0; i < size; i++) { - - cmd = EEPROM_READ_CMD; - cmd |= ((addr + i) << 24) & 0xff000000; - - /* Wait for ACT to authorize write */ - while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) - eieio (); - - /* Write command */ - PSPAN_WRITE (EEPROM_REG, cmd); - - /* Wait for data to be valid */ - while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) - eieio (); - /* Do it twice, first read might be erratic */ - while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) - eieio (); - - /* Read error */ - if (val & 0x00000040) { - return -1; - } else { - data[i] = (val >> 16) & 0xff; - } - } - return 0; -} - -/*************************************************************** - * We take some basic Hardware Configuration Parameter from the - * Serial EEPROM conected to the PSpan bridge. We keep it as - * simple as possible. - */ -#ifdef DEBUG -static int hwc_flash_size (void) -{ - uchar byte; - - if (!seeprom_read (0x40, &byte, sizeof (byte))) { - switch ((byte >> 2) & 0x3) { - case 0x1: - return 0x0400000; - break; - case 0x2: - return 0x0800000; - break; - case 0x3: - return 0x1000000; - default: - return 0x0100000; - } - } - return -1; -} - -static int hwc_local_sdram_size (void) -{ - uchar byte; - - if (!seeprom_read (0x40, &byte, sizeof (byte))) { - switch ((byte & 0x03)) { - case 0x1: - return 0x0800000; - case 0x2: - return 0x1000000; - default: - return 0; /* not present */ - } - } - return -1; -} -#endif /* DEBUG */ - -static int hwc_main_sdram_size (void) -{ - uchar byte; - - if (!seeprom_read (0x41, &byte, sizeof (byte))) { - return 0x1000000 << ((byte >> 5) & 0x7); - } - return -1; -} - -static int hwc_serial_number (void) -{ - int sn = -1; - - if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) { - sn = cpu_to_le32 (sn); - } - return sn; -} - -static int hwc_mac_address (char *str) -{ - char mac[6]; - - if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) { - sprintf (str, "%02X:%02X:%02X:%02X:%02X:%02X", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - } else { - strcpy (str, "ERROR"); - return -1; - } - return 0; -} - -static int hwc_manufact_date (char *str) -{ - uchar byte; - int value; - - if (seeprom_read (0x92, &byte, sizeof (byte))) - goto out; - value = byte; - if (seeprom_read (0x93, &byte, sizeof (byte))) - goto out; - value += byte << 8; - sprintf (str, "%02d/%02d/%04d", - value & 0x1F, (value >> 5) & 0xF, - 1980 + ((value >> 9) & 0x1FF)); - return 0; - -out: - strcpy (str, "ERROR"); - return -1; -} - -static int hwc_board_type (char **str) -{ - ushort id = 0; - - if (seeprom_read (7, (uchar *) & id, sizeof (id)) == 0) { - switch (id) { - case 0x9080: - *str = "4532-002"; - break; - case 0x9081: - *str = "4532-001"; - break; - case 0x9082: - *str = "4532-000"; - break; - default: - *str = "Unknown"; - } - } else { - *str = "Unknown"; - } - - return id; -} - -phys_size_t initdram (int board_type) -{ - long maxsize = hwc_main_sdram_size(); - -#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_USE_FIRMWARE) - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar *base; - int i; - - immap->im_siu_conf.sc_ppc_acr = 0x00000026; - immap->im_siu_conf.sc_ppc_alrh = 0x01276345; - immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF; - immap->im_siu_conf.sc_lcl_acr = 0x00000000; - immap->im_siu_conf.sc_lcl_alrh = 0x01234567; - immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF; - immap->im_siu_conf.sc_tescr1 = 0x00004000; - immap->im_siu_conf.sc_ltescr1 = 0x00004000; - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - /* Initialise 60x bus SDRAM */ - base = (uchar *)(CONFIG_SYS_SDRAM_BASE | 0x110); - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_or1 = CONFIG_SYS_60x_OR; - memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | CONFIG_SYS_60x_BR; - - memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x28000000; - *base = 0xFF; - memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x08000000; - for (i = 0; i < 8; i++) - *base = 0xFF; - memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x18000000; - *base = 0xFF; - memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x40000000; - - /* Initialise local bus SDRAM */ - base = (uchar *)CONFIG_SYS_LSDRAM_BASE; - memctl->memc_lsrt = CONFIG_SYS_LSRT; - memctl->memc_or2 = CONFIG_SYS_LOC_OR; - memctl->memc_br2 = CONFIG_SYS_LSDRAM_BASE | CONFIG_SYS_LOC_BR; - - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000; - *base = 0xFF; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000; - for (i = 0; i < 8; i++) - *base = 0xFF; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000; - *base = 0xFF; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (~(memctl->memc_or1 & BRx_BA_MSK) + 1) / 2; - - maxsize = get_ram_size((long *)(memctl->memc_br1 & BRx_BA_MSK), maxsize); - - memctl->memc_or1 |= ~(maxsize - 1); - - if (maxsize != hwc_main_sdram_size()) - puts("Oops: memory test has not found all memory!\n"); -#endif /* !CONFIG_SYS_RAMBOOT && !CONFIG_SYS_USE_FIRMWARE */ - - /* Return total RAM size (size of 60x SDRAM) */ - return maxsize; -} - -int checkboard(void) -{ - char string[32], *id; - - hwc_manufact_date(string); - hwc_board_type(&id); - printf("Board: Interphase iSPAN %s (#%d %s)\n", - id, hwc_serial_number(), string); -#ifdef DEBUG - printf("Manufacturing date: %s\n", string); - printf("Serial number : %d\n", hwc_serial_number()); - printf("FLASH size : %d MB\n", hwc_flash_size() >> 20); - printf("Main SDRAM size : %d MB\n", hwc_main_sdram_size() >> 20); - printf("Local SDRAM size : %d MB\n", hwc_local_sdram_size() >> 20); - hwc_mac_address(string); - printf("MAC address : %s\n", string); -#endif - return 0; -} - -int misc_init_r(void) -{ - char *s, str[32]; - int num; - - if ((s = getenv("serial#")) == NULL && - (num = hwc_serial_number()) != -1) { - sprintf(str, "%06d", num); - setenv("serial#", str); - } - if ((s = getenv("ethaddr")) == NULL && hwc_mac_address(str) == 0) { - setenv("ethaddr", str); - } - - return 0; -} diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index f941e44e83..2ddb3da38f 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -12,7 +12,7 @@ #include <ioports.h> #include <command.h> #include <malloc.h> -#include <hush.h> +#include <cli_hush.h> #include <net.h> #include <netdev.h> #include <asm/io.h> diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c index f0e91bbdfe..b6b19ccb8e 100644 --- a/board/keymile/common/ivm.c +++ b/board/keymile/common/ivm.c @@ -6,7 +6,7 @@ */ #include <common.h> -#include <hush.h> +#include <cli_hush.h> #include <i2c.h> #include "common.h" @@ -120,7 +120,7 @@ static int ivm_findinventorystring(int type, /* Look for the requested number of CR. */ while ((cr != nr) && (addr < INVENTORYDATASIZE)) { - if ((buf[addr] == '\r')) + if (buf[addr] == '\r') cr++; addr++; } diff --git a/board/matrix_vision/mvblm7/Makefile b/board/matrix_vision/mvblm7/Makefile index 9ed2837a78..caa6cfd34c 100644 --- a/board/matrix_vision/mvblm7/Makefile +++ b/board/matrix_vision/mvblm7/Makefile @@ -8,10 +8,6 @@ obj-y := mvblm7.o pci.o fpga.o extra-y := bootscript.img -quiet_cmd_mkimage = MKIMAGE $@ -cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ - $(if $(KBUILD_VERBOSE:1=), >/dev/null) - MKIMAGEFLAGS_bootscript.image := -T script -C none -n M7_script $(obj)/bootscript.img: $(src)/bootscript diff --git a/board/matrix_vision/mvsmr/Makefile b/board/matrix_vision/mvsmr/Makefile index a9c794e21a..cef1b7664c 100644 --- a/board/matrix_vision/mvsmr/Makefile +++ b/board/matrix_vision/mvsmr/Makefile @@ -12,10 +12,6 @@ obj-y := mvsmr.o fpga.o extra-y := bootscript.img -quiet_cmd_mkimage = MKIMAGE $@ -cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ - $(if $(KBUILD_VERBOSE:1=), >/dev/null) - MKIMAGEFLAGS_bootscript.image := -T script -C none -n mvSMR_Script $(obj)/bootscript.img: $(src)/bootscript diff --git a/board/mcc200/auto_update.c b/board/mcc200/auto_update.c index 2f622b0846..43173ce060 100644 --- a/board/mcc200/auto_update.c +++ b/board/mcc200/auto_update.c @@ -12,11 +12,6 @@ #include <usb.h> #include <part.h> -#ifdef CONFIG_SYS_HUSH_PARSER -#include <hush.h> -#endif - - #ifdef CONFIG_AUTO_UPDATE #ifndef CONFIG_USB_OHCI @@ -247,7 +242,7 @@ int au_do_update(int idx, long sz) /* parse_string_outer() runs off the end. */ addr[image_get_data_size (hdr)] = 0; addr += 8; - parse_string_outer(addr, FLAG_PARSE_SEMICOLON); + run_command_list(addr, -1, 0); return 0; } diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S index cca9c0c880..ee9b7a9d3e 100644 --- a/board/mpl/vcma9/lowlevel_init.S +++ b/board/mpl/vcma9/lowlevel_init.S @@ -229,7 +229,7 @@ lowlevel_init: bne 0b /* PLD access is now possible */ - /* r3 = SDRAMDATA + /* r3 = SDRAMDATA */ /* r13 = pointer to MEM controller regs */ ldr r1, =PLD_BASE mov r4, #SDRAMENTRY_SIZE diff --git a/board/netphone/Makefile b/board/netphone/Makefile deleted file mode 100644 index ba3460577f..0000000000 --- a/board/netphone/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = netphone.o flash.o phone_console.o diff --git a/board/netphone/flash.c b/board/netphone/flash.c deleted file mode 100644 index 91bd968379..0000000000 --- a/board/netphone/flash.c +++ /dev/null @@ -1,513 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_byte(flash_info_t * info, ulong dest, uchar data); -static void flash_get_offsets(ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size; -#if CONFIG_NETPHONE_VERSION == 2 - unsigned long size1; -#endif - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size, size << 20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); - -#ifdef CONFIG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - flash_info[0].size = size; - -#if CONFIG_NETPHONE_VERSION == 2 - size1 = flash_get_size((vu_long *) FLASH_BASE4_PRELIM, &flash_info[1]); - if (size1 > 0) { - if (flash_info[1].flash_id == FLASH_UNKNOWN) - printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", size1, size1 << 20); - - /* Remap FLASH according to real size */ - memctl->memc_or4 = CONFIG_SYS_OR_TIMING_FLASH | (-size1 & 0xFFFF8000); - memctl->memc_br4 = (CONFIG_SYS_FLASH_BASE4 & BR_BA_MSK) | (memctl->memc_br4 & ~(BR_BA_MSK)); - - /* Re-do sizing to get full correct info */ - size1 = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE4, &flash_info[1]); - - flash_get_offsets(CONFIG_SYS_FLASH_BASE4, &flash_info[1]); - - size += size1; - } else - memctl->memc_br4 &= ~BR_V; -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_MX: - printf("MXIC "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29LV040B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - short i; - uchar mid; - uchar pid; - vu_char *caddr = (vu_char *) addr; - ulong base = (ulong) addr; - - /* Write auto select command: read Manufacturer ID */ - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0x90; - - mid = caddr[0]; - switch (mid) { - case (AMD_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_FUJ; - break; - case (MX_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_MX; - break; - case (STM_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - pid = caddr[1]; /* device ID */ - switch (pid) { - case (AMD_ID_LV400T & 0xFF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV400B & 0xFF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV800T & 0xFF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800B & 0xFF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV160T & 0xFF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160B & 0xFF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - - case (STM_ID_M29W040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & 0xFF): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV320B & 0xFF): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - printf(" "); - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection: D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (vu_char *) info->start[0]; - - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0xF0; - - udelay(20000); - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - vu_char *addr = (vu_char *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_char *) (info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = start; - addr = (vu_char *) (info->start[l_sect]); - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_char *) info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - int rc; - - while (cnt > 0) { - if ((rc = write_byte(info, addr++, *src++)) != 0) { - return (rc); - } - --cnt; - } - - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_byte(flash_info_t * info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *) (info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *) dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *((vu_char *) dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c deleted file mode 100644 index 8ff4489ade..0000000000 --- a/board/netphone/netphone.c +++ /dev/null @@ -1,690 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * U-Boot port on NetTA4 board - */ - -#include <common.h> -#include <miiphy.h> -#include <sed156x.h> -#include <status_led.h> - -#include "mpc8xx.h" - -#ifdef CONFIG_HW_WATCHDOG -#include <watchdog.h> -#endif - -int fec8xx_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -int fec8xx_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value); - -/****************************************************************/ - -/* some sane bit macros */ -#define _BD(_b) (1U << (31-(_b))) -#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) - -#define _BW(_b) (1U << (15-(_b))) -#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) - -#define _BB(_b) (1U << (7-(_b))) -#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) - -#define _B(_b) _BD(_b) -#define _BR(_l, _h) _BDR(_l, _h) - -/****************************************************************/ - -/* - * Check Board Identity: - * - * Return 1 always. - */ - -int checkboard(void) -{ - printf ("Intracom NetPhone V%d\n", CONFIG_NETPHONE_VERSION); - return (0); -} - -/****************************************************************/ - -#define _NOT_USED_ 0xFFFFFFFF - -/****************************************************************/ - -#define CS_0000 0x00000000 -#define CS_0001 0x10000000 -#define CS_0010 0x20000000 -#define CS_0011 0x30000000 -#define CS_0100 0x40000000 -#define CS_0101 0x50000000 -#define CS_0110 0x60000000 -#define CS_0111 0x70000000 -#define CS_1000 0x80000000 -#define CS_1001 0x90000000 -#define CS_1010 0xA0000000 -#define CS_1011 0xB0000000 -#define CS_1100 0xC0000000 -#define CS_1101 0xD0000000 -#define CS_1110 0xE0000000 -#define CS_1111 0xF0000000 - -#define BS_0000 0x00000000 -#define BS_0001 0x01000000 -#define BS_0010 0x02000000 -#define BS_0011 0x03000000 -#define BS_0100 0x04000000 -#define BS_0101 0x05000000 -#define BS_0110 0x06000000 -#define BS_0111 0x07000000 -#define BS_1000 0x08000000 -#define BS_1001 0x09000000 -#define BS_1010 0x0A000000 -#define BS_1011 0x0B000000 -#define BS_1100 0x0C000000 -#define BS_1101 0x0D000000 -#define BS_1110 0x0E000000 -#define BS_1111 0x0F000000 - -#define GPL0_AAAA 0x00000000 -#define GPL0_AAA0 0x00200000 -#define GPL0_AAA1 0x00300000 -#define GPL0_000A 0x00800000 -#define GPL0_0000 0x00A00000 -#define GPL0_0001 0x00B00000 -#define GPL0_111A 0x00C00000 -#define GPL0_1110 0x00E00000 -#define GPL0_1111 0x00F00000 - -#define GPL1_0000 0x00000000 -#define GPL1_0001 0x00040000 -#define GPL1_1110 0x00080000 -#define GPL1_1111 0x000C0000 - -#define GPL2_0000 0x00000000 -#define GPL2_0001 0x00010000 -#define GPL2_1110 0x00020000 -#define GPL2_1111 0x00030000 - -#define GPL3_0000 0x00000000 -#define GPL3_0001 0x00004000 -#define GPL3_1110 0x00008000 -#define GPL3_1111 0x0000C000 - -#define GPL4_0000 0x00000000 -#define GPL4_0001 0x00001000 -#define GPL4_1110 0x00002000 -#define GPL4_1111 0x00003000 - -#define GPL5_0000 0x00000000 -#define GPL5_0001 0x00000400 -#define GPL5_1110 0x00000800 -#define GPL5_1111 0x00000C00 -#define LOOP 0x00000080 - -#define EXEN 0x00000040 - -#define AMX_COL 0x00000000 -#define AMX_ROW 0x00000020 -#define AMX_MAR 0x00000030 - -#define NA 0x00000008 - -#define UTA 0x00000004 - -#define TODT 0x00000002 - -#define LAST 0x00000001 - -#define A10_AAAA GPL0_AAAA -#define A10_AAA0 GPL0_AAA0 -#define A10_AAA1 GPL0_AAA1 -#define A10_000A GPL0_000A -#define A10_0000 GPL0_0000 -#define A10_0001 GPL0_0001 -#define A10_111A GPL0_111A -#define A10_1110 GPL0_1110 -#define A10_1111 GPL0_1111 - -#define RAS_0000 GPL1_0000 -#define RAS_0001 GPL1_0001 -#define RAS_1110 GPL1_1110 -#define RAS_1111 GPL1_1111 - -#define CAS_0000 GPL2_0000 -#define CAS_0001 GPL2_0001 -#define CAS_1110 GPL2_1110 -#define CAS_1111 GPL2_1111 - -#define WE_0000 GPL3_0000 -#define WE_0001 GPL3_0001 -#define WE_1110 GPL3_1110 -#define WE_1111 GPL3_1111 - -/* #define CAS_LATENCY 3 */ -#define CAS_LATENCY 2 - -const uint sdram_table[0x40] = { - -#if CAS_LATENCY == 3 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, -#endif - -#if CAS_LATENCY == 2 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - -#endif - - /* UPT */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, - CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, -}; - -#if CONFIG_NETPHONE_VERSION == 2 -static const uint nandcs_table[0x40] = { - /* RSS */ - CS_1000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0000 | GPL4_1110 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111, - CS_0000 | GPL4_0001 | GPL5_1111 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */ - - /* RBS */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_1000 | GPL4_1111 | GPL5_1110 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0001 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111, - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, - - /* WBS */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* UPT */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 , - CS_0001 | LAST, -}; -#endif - -/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ -/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ -#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) - -/* 8 */ -#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -void check_ram(unsigned int addr, unsigned int size) -{ - unsigned int i, j, v, vv; - volatile unsigned int *p; - unsigned int pv; - - p = (unsigned int *)addr; - pv = (unsigned int)p; - for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) - *p++ = pv; - - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - v = (unsigned int)p; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - p++; - } - - for (j = 0; j < 5; j++) { - switch (j) { - case 0: v = 0x00000000; break; - case 1: v = 0xffffffff; break; - case 2: v = 0x55555555; break; - case 3: v = 0xaaaaaaaa; break; - default:v = 0xdeadbeef; break; - } - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - *p = v; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - *p = ~v; - p++; - } - } -} - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size; - - upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0])); - - /* - * Preliminary prescaler for refresh - */ - memctl->memc_mptpr = MPTPR_PTP_DIV8; - - memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - - memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */ - - udelay(200); - - /* perform SDRAM initialisation sequence */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ - udelay(1); - - memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */ - - udelay(10000); - - { - u32 d1, d2; - - d1 = 0xAA55AA55; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - hang(); - } - - d1 = 0x55AA55AA; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - hang(); - } - } - - size = get_ram_size((long *)0, SDRAM_MAX_SIZE); - - if (size == 0) { - printf("SIZE is zero: LOOP on 0\n"); - for (;;) { - *(volatile u32 *)0 = 0; - (void)*(volatile u32 *)0; - } - } - - return size; -} - -/* ------------------------------------------------------------------------- */ - -void reset_phys(void) -{ - int phyno; - unsigned short v; - - udelay(10000); - /* reset the damn phys */ - mii_init(); - - for (phyno = 0; phyno < 32; ++phyno) { - fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v); - if (v == 0xFFFF) - continue; - fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN); - udelay(10000); - fec8xx_miiphy_write(NULL, phyno, MII_BMCR, - BMCR_RESET | BMCR_ANENABLE); - udelay(10000); - } -} - -/* ------------------------------------------------------------------------- */ - -/* GP = general purpose, SP = special purpose (on chip peripheral) */ - -/* bits that can have a special purpose or can be configured as inputs/outputs */ -#define PA_GP_INMASK 0 -#define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15)) -#define PA_SP_MASK 0 -#define PA_ODR_VAL 0 -#define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15)) -#define PA_SP_DIRVAL 0 - -#define PB_GP_INMASK _B(28) -#define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30)) -#define PB_SP_MASK (_BR(22, 25)) -#define PB_ODR_VAL 0 -#define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30)) -#define PB_SP_DIRVAL 0 - -#if CONFIG_NETPHONE_VERSION == 1 -#define PC_GP_INMASK _BW(12) -#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15)) -#elif CONFIG_NETPHONE_VERSION == 2 -#define PC_GP_INMASK (_BW(13) | _BW(15)) -#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(12)) -#endif -#define PC_SP_MASK 0 -#define PC_SOVAL 0 -#define PC_INTVAL 0 -#define PC_GP_OUTVAL (_BW(10) | _BW(11)) -#define PC_SP_DIRVAL 0 - -#if CONFIG_NETPHONE_VERSION == 1 -#define PE_GP_INMASK _B(31) -#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30)) -#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28)) -#elif CONFIG_NETPHONE_VERSION == 2 -#define PE_GP_INMASK _BR(28, 31) -#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27)) -#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27)) -#endif -#define PE_SP_MASK 0 -#define PE_ODR_VAL 0 -#define PE_SP_DIRVAL 0 - -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile iop8xx_t *ioport = &immap->im_ioport; - volatile cpm8xx_t *cpm = &immap->im_cpm; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* NAND chip select */ -#if CONFIG_NETPHONE_VERSION == 1 - memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX); - memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); -#elif CONFIG_NETPHONE_VERSION == 2 - upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0])); - memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS); - memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA); - memctl->memc_mamr = 0; /* all clear */ -#endif - - /* DSP chip select */ - memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX); - memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); - -#if CONFIG_NETPHONE_VERSION == 1 - memctl->memc_br4 &= ~BR_V; -#endif - memctl->memc_br5 &= ~BR_V; - memctl->memc_br6 &= ~BR_V; - memctl->memc_br7 &= ~BR_V; - - ioport->iop_padat = PA_GP_OUTVAL; - ioport->iop_paodr = PA_ODR_VAL; - ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; - ioport->iop_papar = PA_SP_MASK; - - cpm->cp_pbdat = PB_GP_OUTVAL; - cpm->cp_pbodr = PB_ODR_VAL; - cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; - cpm->cp_pbpar = PB_SP_MASK; - - ioport->iop_pcdat = PC_GP_OUTVAL; - ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; - ioport->iop_pcso = PC_SOVAL; - ioport->iop_pcint = PC_INTVAL; - ioport->iop_pcpar = PC_SP_MASK; - - cpm->cp_pedat = PE_GP_OUTVAL; - cpm->cp_peodr = PE_ODR_VAL; - cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL; - cpm->cp_pepar = PE_SP_MASK; - - return 0; -} - -#ifdef CONFIG_HW_WATCHDOG - -void hw_watchdog_reset(void) -{ - /* XXX add here the really funky stuff */ -} - -#endif - -#ifdef CONFIG_SHOW_ACTIVITY - -static volatile int left_to_poll = PHONE_CONSOLE_POLL_HZ; /* poll */ - -/* called from timer interrupt every 1/CONFIG_SYS_HZ sec */ -void board_show_activity(ulong timestamp) -{ - if (left_to_poll > -PHONE_CONSOLE_POLL_HZ) - --left_to_poll; -} - -extern void phone_console_do_poll(void); - -static void do_poll(void) -{ - unsigned int base; - - while (left_to_poll <= 0) { - phone_console_do_poll(); - base = left_to_poll + PHONE_CONSOLE_POLL_HZ; - do { - left_to_poll = base; - } while (base != left_to_poll); - } -} - -/* called when looping */ -void show_activity(int arg) -{ - do_poll(); -} - -#endif - -#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) -int overwrite_console(void) -{ - /* printf("overwrite_console called\n"); */ - return 0; -} -#endif - -extern int drv_phone_init(void); -extern int drv_phone_use_me(void); -extern int drv_phone_is_idle(void); - -int misc_init_r(void) -{ - return drv_phone_init(); -} - -int last_stage_init(void) -{ - int i; - -#if CONFIG_NETPHONE_VERSION == 2 - /* assert peripheral reset */ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12); - for (i = 0; i < 10; i++) - udelay(1000); - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |= _BW(12); -#endif - reset_phys(); - - /* check in order to enable the local console */ - left_to_poll = PHONE_CONSOLE_POLL_HZ; - i = CONFIG_SYS_HZ * 2; - while (i > 0) { - - if (tstc()) { - getc(); - break; - } - - do_poll(); - - if (drv_phone_use_me()) { - status_led_set(0, STATUS_LED_ON); - while (!drv_phone_is_idle()) { - do_poll(); - udelay(1000000 / CONFIG_SYS_HZ); - } - - console_assign(stdin, "phone"); - console_assign(stdout, "phone"); - console_assign(stderr, "phone"); - setenv("bootdelay", "-1"); - break; - } - - udelay(1000000 / CONFIG_SYS_HZ); - i--; - left_to_poll--; - } - left_to_poll = PHONE_CONSOLE_POLL_HZ; - - return 0; -} diff --git a/board/netphone/phone_console.c b/board/netphone/phone_console.c deleted file mode 100644 index d195a398eb..0000000000 --- a/board/netphone/phone_console.c +++ /dev/null @@ -1,1128 +0,0 @@ -/* - * (C) Copyright 2004 Intracom S.A. - * Pantelis Antoniou <panto@intracom.gr> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * phone_console.c - * - * A phone based console - * - * Virtual display of 80x24 characters. - * The actual display is much smaller and panned to show the virtual one. - * Input is made by a numeric keypad utilizing the input method of - * mobile phones. Sorry no T9 lexicons... - * - */ - -#include <common.h> - -#include <version.h> -#include <linux/types.h> -#include <stdio_dev.h> - -#include <sed156x.h> - -/*************************************************************************************************/ - -#define ROWS 24 -#define COLS 80 - -#define REFRESH_HZ (CONFIG_SYS_HZ/50) /* refresh every 20ms */ -#define BLINK_HZ (CONFIG_SYS_HZ/2) /* cursor blink every 500ms */ - -/*************************************************************************************************/ - -#define DISPLAY_BACKLIT_PORT ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat -#define DISPLAY_BACKLIT_MASK 0x0010 - -/*************************************************************************************************/ - -#define KP_STABLE_HZ (CONFIG_SYS_HZ/100) /* stable for 10ms */ -#define KP_REPEAT_DELAY_HZ (CONFIG_SYS_HZ/4) /* delay before repeat 250ms */ -#define KP_REPEAT_HZ (CONFIG_SYS_HZ/20) /* repeat every 50ms */ -#define KP_FORCE_DELAY_HZ (CONFIG_SYS_HZ/2) /* key was force pressed */ -#define KP_IDLE_DELAY_HZ (CONFIG_SYS_HZ/2) /* key was released and idle */ - -#if CONFIG_NETPHONE_VERSION == 1 -#define KP_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) -#define KP_SPI_RXD_MASK 0x0008 - -#define KP_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) -#define KP_SPI_TXD_MASK 0x0004 - -#define KP_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) -#define KP_SPI_CLK_MASK 0x0001 -#elif CONFIG_NETPHONE_VERSION == 2 -#define KP_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) -#define KP_SPI_RXD_MASK 0x00000008 - -#define KP_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) -#define KP_SPI_TXD_MASK 0x00000004 - -#define KP_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) -#define KP_SPI_CLK_MASK 0x00000002 -#endif - -#define KP_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) -#define KP_CS_MASK 0x00000010 - -#define KP_SPI_RXD() (KP_SPI_RXD_PORT & KP_SPI_RXD_MASK) - -#define KP_SPI_TXD(x) \ - do { \ - if (x) \ - KP_SPI_TXD_PORT |= KP_SPI_TXD_MASK; \ - else \ - KP_SPI_TXD_PORT &= ~KP_SPI_TXD_MASK; \ - } while(0) - -#define KP_SPI_CLK(x) \ - do { \ - if (x) \ - KP_SPI_CLK_PORT |= KP_SPI_CLK_MASK; \ - else \ - KP_SPI_CLK_PORT &= ~KP_SPI_CLK_MASK; \ - } while(0) - -#define KP_SPI_CLK_TOGGLE() (KP_SPI_CLK_PORT ^= KP_SPI_CLK_MASK) - -#define KP_SPI_BIT_DELAY() /* no delay */ - -#define KP_CS(x) \ - do { \ - if (x) \ - KP_CS_PORT |= KP_CS_MASK; \ - else \ - KP_CS_PORT &= ~KP_CS_MASK; \ - } while(0) - -#define KP_ROWS 7 -#define KP_COLS 4 - -#define KP_ROWS_MASK ((1 << KP_ROWS) - 1) -#define KP_COLS_MASK ((1 << KP_COLS) - 1) - -#define SCAN 0 -#define SCAN_FILTER 1 -#define SCAN_COL 2 -#define SCAN_COL_FILTER 3 -#define PRESSED 4 - -#define KP_F1 0 /* leftmost dot (tab) */ -#define KP_F2 1 /* middle left dot */ -#define KP_F3 2 /* up */ -#define KP_F4 3 /* middle right dot */ -#define KP_F5 4 /* rightmost dot */ -#define KP_F6 5 /* C */ -#define KP_F7 6 /* left */ -#define KP_F8 7 /* down */ -#define KP_F9 8 /* right */ -#define KP_F10 9 /* enter */ -#define KP_F11 10 /* R */ -#define KP_F12 11 /* save */ -#define KP_F13 12 /* redial */ -#define KP_F14 13 /* speaker */ -#define KP_F15 14 /* unused */ -#define KP_F16 15 /* unused */ - -#define KP_RELEASE -1 /* key depressed */ -#define KP_FORCE -2 /* key was pressed for more than force hz */ -#define KP_IDLE -3 /* key was released and idle */ - -#define KP_1 '1' -#define KP_2 '2' -#define KP_3 '3' -#define KP_4 '4' -#define KP_5 '5' -#define KP_6 '6' -#define KP_7 '7' -#define KP_8 '8' -#define KP_9 '9' -#define KP_0 '0' -#define KP_STAR '*' -#define KP_HASH '#' - -/*************************************************************************************************/ - -static int curs_disabled; -static int curs_col, curs_row; -static int disp_col, disp_row; - -static int width, height; - -/* the simulated vty buffer */ -static char vty_buf[ROWS * COLS]; -static char last_visible_buf[ROWS * COLS]; /* worst case */ -static char *last_visible_curs_ptr; -static int last_visible_curs_rev; -static int blinked_state; -static int last_input_mode; -static int refresh_time; -static int blink_time; -static char last_fast_punct; - -/*************************************************************************************************/ - -#define IM_SMALL 0 -#define IM_CAPITAL 1 -#define IM_NUMBER 2 - -static int input_mode; -static char fast_punct; -static int tab_indicator; -static const char *fast_punct_list = ",.:;*"; - -static const char *input_mode_txt[] = { "abc", "ABC", "123" }; - -static const char *punct = ".,!;?'\"-()@/:_+&%*=<>$[]{}\\~^#|"; -static const char *whspace = " 0\n"; -/* per mode character select (for 2-9) */ -static const char *digits_sel[2][8] = { - { /* small */ - "abc2", /* 2 */ - "def3", /* 3 */ - "ghi4", /* 4 */ - "jkl5", /* 5 */ - "mno6", /* 6 */ - "pqrs7", /* 7 */ - "tuv8", /* 8 */ - "wxyz9", /* 9 */ - }, { /* capital */ - "ABC2", /* 2 */ - "DEF3", /* 3 */ - "GHI4", /* 4 */ - "JKL5", /* 5 */ - "MNO6", /* 6 */ - "PQRS7", /* 7 */ - "TUV8", /* 8 */ - "WXYZ9", /* 9 */ - } -}; - -/*****************************************************************************/ - -static void update(void); -static void ensure_visible(int col, int row, int dx, int dy); - -static void console_init(void) -{ - curs_disabled = 0; - curs_col = 0; - curs_row = 0; - - disp_col = 0; - disp_row = 0; - - input_mode = IM_SMALL; - fast_punct = ','; - last_fast_punct = '\0'; - refresh_time = REFRESH_HZ; - blink_time = BLINK_HZ; - - memset(vty_buf, ' ', sizeof(vty_buf)); - - memset(last_visible_buf, ' ', sizeof(last_visible_buf)); - last_visible_curs_ptr = NULL; - last_input_mode = -1; - last_visible_curs_rev = 0; - - blinked_state = 0; - - sed156x_init(); - width = sed156x_text_width; - height = sed156x_text_height - 1; - - tab_indicator = 0; -} - -/*****************************************************************************/ - -void phone_putc(const char c); - -/*****************************************************************************/ - -static int queued_char = -1; -static int enabled = 0; - -/*****************************************************************************/ - -/* flush buffers */ -int phone_start(void) -{ - console_init(); - - update(); - sed156x_sync(); - - enabled = 1; - queued_char = 'U' - '@'; - - /* backlit on */ - DISPLAY_BACKLIT_PORT &= ~DISPLAY_BACKLIT_MASK; - - return 0; -} - -int phone_stop(void) -{ - enabled = 0; - - sed156x_clear(); - sed156x_sync(); - - /* backlit off */ - DISPLAY_BACKLIT_PORT |= DISPLAY_BACKLIT_MASK; - - return 0; -} - -void phone_puts(const char *s) -{ - int count = strlen(s); - - while (count--) - phone_putc(*s++); -} - -int phone_tstc(void) -{ - return queued_char >= 0 ? 1 : 0; -} - -int phone_getc(void) -{ - int r; - - if (queued_char < 0) - return -1; - - r = queued_char; - queued_char = -1; - - return r; -} - -/*****************************************************************************/ - -int drv_phone_init(void) -{ - struct stdio_dev console_dev; - - console_init(); - - memset(&console_dev, 0, sizeof(console_dev)); - strcpy(console_dev.name, "phone"); - console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */ - console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - console_dev.start = phone_start; - console_dev.stop = phone_stop; - console_dev.putc = phone_putc; /* 'putc' function */ - console_dev.puts = phone_puts; /* 'puts' function */ - console_dev.tstc = phone_tstc; /* 'tstc' function */ - console_dev.getc = phone_getc; /* 'getc' function */ - - if (stdio_register(&console_dev) == 0) - return 1; - - return 0; -} - -static int use_me; - -int drv_phone_use_me(void) -{ - return use_me; -} - -static void kp_do_poll(void); - -void phone_console_do_poll(void) -{ - int i, x, y; - - kp_do_poll(); - - if (enabled) { - /* do the blink */ - blink_time -= PHONE_CONSOLE_POLL_HZ; - if (blink_time <= 0) { - blink_time += BLINK_HZ; - if (last_visible_curs_ptr) { - i = last_visible_curs_ptr - last_visible_buf; - x = i % width; y = i / width; - sed156x_reverse_at(x, y, 1); - last_visible_curs_rev ^= 1; - } - } - - /* do the refresh */ - refresh_time -= PHONE_CONSOLE_POLL_HZ; - if (refresh_time <= 0) { - refresh_time += REFRESH_HZ; - sed156x_sync(); - } - } - -} - -static int last_scancode = -1; -static int forced_scancode = 0; -static int input_state = -1; -static int input_scancode = -1; -static int input_selected_char = -1; -static char input_covered_char; - -static void putchar_at_cursor(char c) -{ - vty_buf[curs_row * COLS + curs_col] = c; - ensure_visible(curs_col, curs_row, 1, 1); -} - -static char getchar_at_cursor(void) -{ - return vty_buf[curs_row * COLS + curs_col]; -} - -static void queue_input_char(char c) -{ - if (c <= 0) - return; - - queued_char = c; -} - -static void terminate_input(void) -{ - if (input_state < 0) - return; - - if (input_selected_char >= 0) - queue_input_char(input_selected_char); - - input_state = -1; - input_selected_char = -1; - putchar_at_cursor(input_covered_char); - - curs_disabled = 0; - blink_time = BLINK_HZ; - update(); -} - -static void handle_enabled_scancode(int scancode) -{ - char c; - int new_disp_col, new_disp_row; - const char *sel; - - - switch (scancode) { - - /* key was released */ - case KP_RELEASE: - forced_scancode = 0; - break; - - /* key was forced */ - case KP_FORCE: - - switch (last_scancode) { - case '#': - if (input_mode == IM_NUMBER) { - input_mode = IM_CAPITAL; - /* queue backspace to erase # */ - queue_input_char('\b'); - } else { - input_mode = IM_NUMBER; - fast_punct = '*'; - } - update(); - break; - - case '0': case '1': - case '2': case '3': case '4': case '5': - case '6': case '7': case '8': case '9': - - if (input_state < 0) - break; - - input_selected_char = last_scancode; - putchar_at_cursor((char)input_selected_char); - terminate_input(); - - break; - - default: - break; - } - - break; - - /* release and idle */ - case KP_IDLE: - input_scancode = -1; - if (input_state < 0) - break; - terminate_input(); - break; - - /* change input mode */ - case '#': - if (last_scancode == '#') /* no repeat */ - break; - - if (input_mode == IM_NUMBER) { - input_scancode = scancode; - input_state = 0; - input_selected_char = scancode; - input_covered_char = getchar_at_cursor(); - putchar_at_cursor((char)input_selected_char); - terminate_input(); - break; - } - - if (input_mode == IM_SMALL) - input_mode = IM_CAPITAL; - else - input_mode = IM_SMALL; - - update(); - break; - - case '*': - /* no repeat */ - if (last_scancode == scancode) - break; - - if (input_state >= 0) - terminate_input(); - - input_scancode = fast_punct; - input_state = 0; - input_selected_char = input_scancode; - input_covered_char = getchar_at_cursor(); - putchar_at_cursor((char)input_selected_char); - terminate_input(); - - break; - - case '0': case '1': - case '2': case '3': case '4': case '5': - case '6': case '7': case '8': case '9': - - /* no repeat */ - if (last_scancode == scancode) - break; - - if (input_mode == IM_NUMBER) { - input_scancode = scancode; - input_state = 0; - input_selected_char = scancode; - input_covered_char = getchar_at_cursor(); - putchar_at_cursor((char)input_selected_char); - terminate_input(); - break; - } - - if (input_state >= 0 && input_scancode != scancode) - terminate_input(); - - if (input_state < 0) { - curs_disabled = 1; - input_scancode = scancode; - input_state = 0; - input_covered_char = getchar_at_cursor(); - } else - input_state++; - - if (scancode == '0') - sel = whspace; - else if (scancode == '1') - sel = punct; - else - sel = digits_sel[input_mode][scancode - '2']; - c = *(sel + input_state); - if (c == '\0') { - input_state = 0; - c = *sel; - } - - input_selected_char = (int)c; - putchar_at_cursor((char)input_selected_char); - update(); - - break; - - /* move visible display */ - case KP_F3: case KP_F8: case KP_F7: case KP_F9: - - new_disp_col = disp_col; - new_disp_row = disp_row; - - switch (scancode) { - /* up */ - case KP_F3: - if (new_disp_row <= 0) - break; - new_disp_row--; - break; - - /* down */ - case KP_F8: - if (new_disp_row >= ROWS - height) - break; - new_disp_row++; - break; - - /* left */ - case KP_F7: - if (new_disp_col <= 0) - break; - new_disp_col--; - break; - - /* right */ - case KP_F9: - if (new_disp_col >= COLS - width) - break; - new_disp_col++; - break; - } - - /* no change? */ - if (disp_col == new_disp_col && disp_row == new_disp_row) - break; - - disp_col = new_disp_col; - disp_row = new_disp_row; - update(); - - break; - - case KP_F6: /* backspace */ - /* inputing something; no backspace sent, just cancel input */ - if (input_state >= 0) { - input_selected_char = -1; /* cancel */ - terminate_input(); - break; - } - queue_input_char('\b'); - break; - - case KP_F10: /* enter */ - /* inputing something; first cancel input */ - if (input_state >= 0) - terminate_input(); - queue_input_char('\r'); - break; - - case KP_F11: /* R -> Ctrl-C (abort) */ - if (input_state >= 0) - terminate_input(); - queue_input_char('C' - 'Q'); /* ctrl-c */ - break; - - case KP_F5: /* F% -> Ctrl-U (clear line) */ - if (input_state >= 0) - terminate_input(); - queue_input_char('U' - 'Q'); /* ctrl-c */ - break; - - - case KP_F1: /* tab */ - /* inputing something; first cancel input */ - if (input_state >= 0) - terminate_input(); - queue_input_char('\t'); - break; - - case KP_F2: /* change fast punct */ - sel = strchr(fast_punct_list, fast_punct); - if (sel == NULL) - sel = &fast_punct_list[0]; - sel++; - if (*sel == '\0') - sel = &fast_punct_list[0]; - fast_punct = *sel; - update(); - break; - - - } - - if (scancode != KP_FORCE && scancode != KP_IDLE) /* don't record forced or idle scancode */ - last_scancode = scancode; -} - -static void scancode_action(int scancode) -{ -#if 0 - if (scancode == KP_RELEASE) - printf(" RELEASE\n"); - else if (scancode == KP_FORCE) - printf(" FORCE\n"); - else if (scancode == KP_IDLE) - printf(" IDLE\n"); - else if (scancode < 32) - printf(" F%d", scancode + 1); - else - printf(" %c", (char)scancode); - printf("\n"); -#endif - - if (enabled) { - handle_enabled_scancode(scancode); - return; - } - - if (scancode == KP_FORCE && last_scancode == '*') - use_me = 1; - - last_scancode = scancode; -} - -/**************************************************************************************/ - -/* update the display; make sure to update only the differences */ -static void update(void) -{ - int i; - char *s, *e, *t, *r, *b, *cp; - - if (input_mode != last_input_mode) - sed156x_output_at(sed156x_text_width - 3, sed156x_text_height - 1, input_mode_txt[input_mode], 3); - - if (tab_indicator == 0) { - sed156x_output_at(0, sed156x_text_height - 1, "\\t", 2); - tab_indicator = 1; - } - - if (fast_punct != last_fast_punct) - sed156x_output_at(4, sed156x_text_height - 1, &fast_punct, 1); - - if (curs_disabled || - curs_col < disp_col || curs_col >= (disp_col + width) || - curs_row < disp_row || curs_row >= (disp_row + height)) { - cp = NULL; - } else - cp = last_visible_buf + (curs_row - disp_row) * width + (curs_col - disp_col); - - - /* printf("(%d,%d) (%d,%d) %s\n", curs_col, curs_row, disp_col, disp_row, cp ? "YES" : "no"); */ - - /* clear previous cursor */ - if (last_visible_curs_ptr && last_visible_curs_rev == 0) { - i = last_visible_curs_ptr - last_visible_buf; - sed156x_reverse_at(i % width, i / width, 1); - } - - b = vty_buf + disp_row * COLS + disp_col; - t = last_visible_buf; - for (i = 0; i < height; i++) { - s = b; - e = b + width; - /* update only the differences */ - do { - while (s < e && *s == *t) { - s++; - t++; - } - if (s == e) /* no more */ - break; - - /* find run */ - r = s; - while (s < e && *s != *t) - *t++ = *s++; - - /* and update */ - sed156x_output_at(r - b, i, r, s - r); - - } while (s < e); - - b += COLS; - } - - /* set cursor */ - if (cp) { - last_visible_curs_ptr = cp; - i = last_visible_curs_ptr - last_visible_buf; - sed156x_reverse_at(i % width, i / width, 1); - last_visible_curs_rev = 0; - } else { - last_visible_curs_ptr = NULL; - } - - last_input_mode = input_mode; - last_fast_punct = fast_punct; -} - -/* ensure visibility; the trick is to minimize the screen movement */ -static void ensure_visible(int col, int row, int dx, int dy) -{ - int x1, y1, x2, y2, a1, b1, a2, b2; - - /* clamp visible region */ - if (col < 0) { - dx -= col; - col = 0; - if (dx <= 0) - dx = 1; - } - - if (row < 0) { - dy -= row; - row = 0; - if (dy <= 0) - dy = 1; - } - - if (col + dx > COLS) - dx = COLS - col; - - if (row + dy > ROWS) - dy = ROWS - row; - - - /* move to easier to use vars */ - x1 = disp_col; y1 = disp_row; - x2 = x1 + width; y2 = y1 + height; - a1 = col; b1 = row; - a2 = a1 + dx; b2 = b1 + dy; - - /* printf("(%d,%d) - (%d,%d) : (%d, %d) - (%d, %d)\n", x1, y1, x2, y2, a1, b1, a2, b2); */ - - if (a2 > x2) { - /* move to the right */ - x2 = a2; - x1 = x2 - width; - if (x1 < 0) { - x1 = 0; - x2 = width; - } - } else if (a1 < x1) { - /* move to the left */ - x1 = a1; - x2 = x1 + width; - if (x2 > COLS) { - x2 = COLS; - x1 = x2 - width; - } - } - - if (b2 > y2) { - /* move down */ - y2 = b2; - y1 = y2 - height; - if (y1 < 0) { - y1 = 0; - y2 = height; - } - } else if (b1 < y1) { - /* move up */ - y1 = b1; - y2 = y1 + width; - if (y2 > ROWS) { - y2 = ROWS; - y1 = y2 - height; - } - } - - /* printf("(%d,%d) - (%d,%d) : (%d, %d) - (%d, %d)\n", x1, y1, x2, y2, a1, b1, a2, b2); */ - - /* no movement? */ - if (disp_col == x1 && disp_row == y1) - return; - - disp_col = x1; - disp_row = y1; -} - -/**************************************************************************************/ - -static void newline(void) -{ - curs_col = 0; - if (curs_row + 1 < ROWS) - curs_row++; - else { - memmove(vty_buf, vty_buf + COLS, COLS * (ROWS - 1)); - memset(vty_buf + (ROWS - 1) * COLS, ' ', COLS); - } -} - -void phone_putc(const char c) -{ - int i; - - if (input_mode != -1) { - input_selected_char = -1; - terminate_input(); - } - - curs_disabled = 1; - update(); - - blink_time = BLINK_HZ; - - switch (c) { - case '\a': /* ignore bell */ - case '\r': /* ignore carriage return */ - break; - - case '\n': /* next line */ - newline(); - ensure_visible(curs_col, curs_row, 1, 1); - break; - - case 9: /* tab 8 */ - /* move to tab */ - i = curs_col; - i |= 0x0008; - i &= ~0x0007; - - if (i < COLS) - curs_col = i; - else - newline(); - - ensure_visible(curs_col, curs_row, 1, 1); - break; - - case 8: /* backspace */ - if (curs_col <= 0) - break; - curs_col--; - - /* make sure that we see a couple of characters before */ - if (curs_col > 4) - ensure_visible(curs_col - 4, curs_row, 4, 1); - else - ensure_visible(curs_col, curs_row, 1, 1); - - break; - - default: /* draw the char */ - putchar_at_cursor(c); - - /* - * check for newline - */ - if (curs_col + 1 < COLS) - curs_col++; - else - newline(); - - ensure_visible(curs_col, curs_row, 1, 1); - - break; - } - - curs_disabled = 0; - blink_time = BLINK_HZ; - update(); -} - -/**************************************************************************************/ - -static inline unsigned int kp_transfer(unsigned int val) -{ - unsigned int rx; - int b; - - rx = 0; b = 8; - while (--b >= 0) { - KP_SPI_TXD(val & 0x80); - val <<= 1; - KP_SPI_CLK_TOGGLE(); - KP_SPI_BIT_DELAY(); - rx <<= 1; - if (KP_SPI_RXD()) - rx |= 1; - KP_SPI_CLK_TOGGLE(); - KP_SPI_BIT_DELAY(); - } - - return rx; -} - -unsigned int kp_data_transfer(unsigned int val) -{ - KP_SPI_CLK(1); - KP_CS(0); - val = kp_transfer(val); - KP_CS(1); - - return val; -} - -unsigned int kp_get_col_mask(unsigned int row_mask) -{ - unsigned int val, col_mask; - - val = 0x80 | (row_mask & 0x7F); - (void)kp_data_transfer(val); -#if CONFIG_NETPHONE_VERSION == 1 - col_mask = kp_data_transfer(val) & 0x0F; -#elif CONFIG_NETPHONE_VERSION == 2 - col_mask = ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & 0x0f; - /* XXX FUCK FUCK FUCK FUCK FUCK!!!! */ - col_mask = ((col_mask & 0x08) >> 3) | /* BKBR1 */ - ((col_mask & 0x04) << 1) | /* BKBR2 */ - (col_mask & 0x02) | /* BKBR3 */ - ((col_mask & 0x01) << 2); /* BKBR4 */ - -#endif - /* printf("col_mask(row_mask = 0x%x) -> col_mask = 0x%x\n", row_mask, col_mask); */ - - return col_mask; -} - -/**************************************************************************************/ - -static const int kp_scancodes[KP_ROWS * KP_COLS] = { - KP_F1, KP_F3, KP_F4, KP_F2, - KP_F6, KP_F8, KP_F9, KP_F7, - KP_1, KP_3, KP_F11, KP_2, - KP_4, KP_6, KP_F12, KP_5, - KP_7, KP_9, KP_F13, KP_8, - KP_STAR, KP_HASH, KP_F14, KP_0, - KP_F5, KP_F15, KP_F16, KP_F10, -}; - -static const int kp_repeats[KP_ROWS * KP_COLS] = { - 0, 1, 0, 0, - 0, 1, 1, 1, - 1, 1, 0, 1, - 1, 1, 0, 1, - 1, 1, 0, 1, - 1, 1, 0, 1, - 0, 0, 0, 1, -}; - -static int kp_state = SCAN; -static int kp_last_col_mask; -static int kp_cur_row, kp_cur_col; -static int kp_scancode; -static int kp_stable; -static int kp_repeat; -static int kp_repeat_time; -static int kp_force_time; -static int kp_idle_time; - -static void kp_do_poll(void) -{ - unsigned int col_mask; - int col; - - switch (kp_state) { - case SCAN: - if (kp_idle_time > 0) { - kp_idle_time -= PHONE_CONSOLE_POLL_HZ; - if (kp_idle_time <= 0) - scancode_action(KP_IDLE); - } - - col_mask = kp_get_col_mask(KP_ROWS_MASK); - if (col_mask == KP_COLS_MASK) - break; /* nothing */ - kp_last_col_mask = col_mask; - kp_stable = 0; - kp_state = SCAN_FILTER; - break; - - case SCAN_FILTER: - col_mask = kp_get_col_mask(KP_ROWS_MASK); - if (col_mask != kp_last_col_mask) { - kp_state = SCAN; - break; - } - - kp_stable += PHONE_CONSOLE_POLL_HZ; - if (kp_stable < KP_STABLE_HZ) - break; - - kp_cur_row = 0; - kp_stable = 0; - kp_state = SCAN_COL; - - (void)kp_get_col_mask(1 << kp_cur_row); - break; - - case SCAN_COL: - col_mask = kp_get_col_mask(1 << kp_cur_row); - if (col_mask == KP_COLS_MASK) { - if (++kp_cur_row >= KP_ROWS) { - kp_state = SCAN; - break; - } - kp_get_col_mask(1 << kp_cur_row); - break; - } - kp_last_col_mask = col_mask; - kp_stable = 0; - kp_state = SCAN_COL_FILTER; - break; - - case SCAN_COL_FILTER: - col_mask = kp_get_col_mask(1 << kp_cur_row); - if (col_mask != kp_last_col_mask || col_mask == KP_COLS_MASK) { - kp_state = SCAN; - break; - } - - kp_stable += PHONE_CONSOLE_POLL_HZ; - if (kp_stable < KP_STABLE_HZ) - break; - - for (col = 0; col < KP_COLS; col++) - if ((col_mask & (1 << col)) == 0) - break; - kp_cur_col = col; - kp_state = PRESSED; - kp_scancode = kp_scancodes[kp_cur_row * KP_COLS + kp_cur_col]; - kp_repeat = kp_repeats[kp_cur_row * KP_COLS + kp_cur_col]; - - if (kp_repeat) - kp_repeat_time = KP_REPEAT_DELAY_HZ; - kp_force_time = KP_FORCE_DELAY_HZ; - - scancode_action(kp_scancode); - - break; - - case PRESSED: - col_mask = kp_get_col_mask(1 << kp_cur_row); - if (col_mask != kp_last_col_mask) { - kp_state = SCAN; - scancode_action(KP_RELEASE); - kp_idle_time = KP_IDLE_DELAY_HZ; - break; - } - - if (kp_repeat) { - kp_repeat_time -= PHONE_CONSOLE_POLL_HZ; - if (kp_repeat_time <= 0) { - kp_repeat_time += KP_REPEAT_HZ; - scancode_action(kp_scancode); - } - } - - if (kp_force_time > 0) { - kp_force_time -= PHONE_CONSOLE_POLL_HZ; - if (kp_force_time <= 0) - scancode_action(KP_FORCE); - } - - break; - } -} - -/**************************************************************************************/ - -int drv_phone_is_idle(void) -{ - return kp_state == SCAN; -} diff --git a/board/netphone/u-boot.lds b/board/netphone/u-boot.lds deleted file mode 100644 index 0dff5a4023..0000000000 --- a/board/netphone/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/netphone/u-boot.lds.debug b/board/netphone/u-boot.lds.debug deleted file mode 100644 index a198cf9520..0000000000 --- a/board/netphone/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/netta/Makefile b/board/netta/Makefile deleted file mode 100644 index 98bac7ed46..0000000000 --- a/board/netta/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = netta.o flash.o dsp.o codec.o pcmcia.o diff --git a/board/netta/codec.c b/board/netta/codec.c deleted file mode 100644 index e303aa4780..0000000000 --- a/board/netta/codec.c +++ /dev/null @@ -1,1481 +0,0 @@ -/* - * CODEC - */ - -#include <common.h> -#include <post.h> - -#include "mpc8xx.h" - -/***********************************************/ - -#define MAX_DUSLIC 4 - -#define NUM_CHANNELS 2 -#define MAX_SLICS (MAX_DUSLIC * NUM_CHANNELS) - -/***********************************************/ - -#define SOP_READ_CH_0 0xC4 /* Read SOP Register for Channel A */ -#define SOP_READ_CH_1 0xCC /* Read SOP Register for Channel B */ -#define SOP_WRITE_CH_0 0x44 /* Write SOP Register for Channel A */ -#define SOP_WRITE_CH_1 0x4C /* Write SOP Register for Channel B */ - -#define COP_READ_CH_0 0xC5 -#define COP_READ_CH_1 0xCD -#define COP_WRITE_CH_0 0x45 -#define COP_WRITE_CH_1 0x4D - -#define POP_READ_CH_0 0xC6 -#define POP_READ_CH_1 0xCE -#define POP_WRITE_CH_0 0x46 -#define POP_WRITE_CH_1 0x4E - -#define RST_CMD_DUSLIC_CHIP 0x40 /* OR 0x48 */ -#define RST_CMD_DUSLIC_CH_A 0x41 -#define RST_CMD_DUSLIC_CH_B 0x49 - -#define PCM_RESYNC_CMD_CH_A 0x42 -#define PCM_RESYNC_CMD_CH_B 0x4A - -#define ACTIVE_HOOK_LEV_4 0 -#define ACTIVE_HOOK_LEV_12 1 - -#define SLIC_P_NORMAL 0x01 - -/************************************************/ - -#define CODSP_WR 0x00 -#define CODSP_RD 0x80 -#define CODSP_OP 0x40 -#define CODSP_ADR(x) (((unsigned char)(x) & 7) << 3) -#define CODSP_M(x) ((unsigned char)(x) & 7) -#define CODSP_CMD(x) ((unsigned char)(x) & 7) - -/************************************************/ - -/* command indication ops */ -#define CODSP_M_SLEEP_PWRDN 7 -#define CODSP_M_PWRDN_HIZ 0 -#define CODSP_M_ANY_ACT 2 -#define CODSP_M_RING 5 -#define CODSP_M_ACT_MET 6 -#define CODSP_M_GND_START 4 -#define CODSP_M_RING_PAUSE 1 - -/* single byte commands */ -#define CODSP_CMD_SOFT_RESET CODSP_CMD(0) -#define CODSP_CMD_RESET_CH CODSP_CMD(1) -#define CODSP_CMD_RESYNC CODSP_CMD(2) - -/* two byte commands */ -#define CODSP_CMD_SOP CODSP_CMD(4) -#define CODSP_CMD_COP CODSP_CMD(5) -#define CODSP_CMD_POP CODSP_CMD(6) - -/************************************************/ - -/* read as 4-bytes */ -#define CODSP_INTREG_INT_CH 0x80000000 -#define CODSP_INTREG_HOOK 0x40000000 -#define CODSP_INTREG_GNDK 0x20000000 -#define CODSP_INTREG_GNDP 0x10000000 -#define CODSP_INTREG_ICON 0x08000000 -#define CODSP_INTREG_VRTLIM 0x04000000 -#define CODSP_INTREG_OTEMP 0x02000000 -#define CODSP_INTREG_SYNC_FAIL 0x01000000 -#define CODSP_INTREG_LM_THRES 0x00800000 -#define CODSP_INTREG_READY 0x00400000 -#define CODSP_INTREG_RSTAT 0x00200000 -#define CODSP_INTREG_LM_OK 0x00100000 -#define CODSP_INTREG_IO4_DU 0x00080000 -#define CODSP_INTREG_IO3_DU 0x00040000 -#define CODSP_INTREG_IO2_DU 0x00020000 -#define CODSP_INTREG_IO1_DU 0x00010000 -#define CODSP_INTREG_DTMF_OK 0x00008000 -#define CODSP_INTREG_DTMF_KEY4 0x00004000 -#define CODSP_INTREG_DTMF_KEY3 0x00002000 -#define CODSP_INTREG_DTMF_KEY2 0x00001000 -#define CODSP_INTREG_DTMF_KEY1 0x00000800 -#define CODSP_INTREG_DTMF_KEY0 0x00000400 -#define CODSP_INTREG_UTDR_OK 0x00000200 -#define CODSP_INTREG_UTDX_OK 0x00000100 -#define CODSP_INTREG_EDSP_FAIL 0x00000080 -#define CODSP_INTREG_CIS_BOF 0x00000008 -#define CODSP_INTREG_CIS_BUF 0x00000004 -#define CODSP_INTREG_CIS_REQ 0x00000002 -#define CODSP_INTREG_CIS_ACT 0x00000001 - -/************************************************/ - -/* ======== SOP REG ADDRESSES =======*/ - -#define REVISION_ADDR 0x00 -#define PCMC1_ADDR 0x05 -#define XCR_ADDR 0x06 -#define INTREG1_ADDR 0x07 -#define INTREG2_ADDR 0x08 -#define INTREG3_ADDR 0x09 -#define INTREG4_ADDR 0x0A -#define LMRES1_ADDR 0x0D -#define MASK_ADDR 0x11 -#define IOCTL3_ADDR 0x14 -#define BCR1_ADDR 0x15 -#define BCR2_ADDR 0x16 -#define BCR3_ADDR 0x17 -#define BCR4_ADDR 0x18 -#define BCR5_ADDR 0x19 -#define DSCR_ADDR 0x1A -#define LMCR1_ADDR 0x1C -#define LMCR2_ADDR 0x1D -#define LMCR3_ADDR 0x1E -#define OFR1_ADDR 0x1F -#define PCMR1_ADDR 0x21 -#define PCMX1_ADDR 0x25 -#define TSTR3_ADDR 0x2B -#define TSTR4_ADDR 0x2C -#define TSTR5_ADDR 0x2D - -/* ========= POP REG ADDRESSES ========*/ - -#define CIS_DAT_ADDR 0x00 - -#define LEC_LEN_ADDR 0x3A -#define LEC_POWR_ADDR 0x3B -#define LEC_DELP_ADDR 0x3C -#define LEC_DELQ_ADDR 0x3D -#define LEC_GAIN_XI_ADDR 0x3E -#define LEC_GAIN_RI_ADDR 0x3F -#define LEC_GAIN_XO_ADDR 0x40 -#define LEC_RES_1_ADDR 0x41 -#define LEC_RES_2_ADDR 0x42 - -#define NLP_POW_LPF_ADDR 0x30 -#define NLP_POW_LPS_ADDR 0x31 -#define NLP_BN_LEV_X_ADDR 0x32 -#define NLP_BN_LEV_R_ADDR 0x33 -#define NLP_BN_INC_ADDR 0x34 -#define NLP_BN_DEC_ADDR 0x35 -#define NLP_BN_MAX_ADDR 0x36 -#define NLP_BN_ADJ_ADDR 0x37 -#define NLP_RE_MIN_ERLL_ADDR 0x38 -#define NLP_RE_EST_ERLL_ADDR 0x39 -#define NLP_SD_LEV_X_ADDR 0x3A -#define NLP_SD_LEV_R_ADDR 0x3B -#define NLP_SD_LEV_BN_ADDR 0x3C -#define NLP_SD_LEV_RE_ADDR 0x3D -#define NLP_SD_OT_DT_ADDR 0x3E -#define NLP_ERL_LIN_LP_ADDR 0x3F -#define NLP_ERL_LEC_LP_ADDR 0x40 -#define NLP_CT_LEV_RE_ADDR 0x41 -#define NLP_CTRL_ADDR 0x42 - -#define UTD_CF_H_ADDR 0x4B -#define UTD_CF_L_ADDR 0x4C -#define UTD_BW_H_ADDR 0x4D -#define UTD_BW_L_ADDR 0x4E -#define UTD_NLEV_ADDR 0x4F -#define UTD_SLEV_H_ADDR 0x50 -#define UTD_SLEV_L_ADDR 0x51 -#define UTD_DELT_ADDR 0x52 -#define UTD_RBRK_ADDR 0x53 -#define UTD_RTIME_ADDR 0x54 -#define UTD_EBRK_ADDR 0x55 -#define UTD_ETIME_ADDR 0x56 - -#define DTMF_LEV_ADDR 0x30 -#define DTMF_TWI_ADDR 0x31 -#define DTMF_NCF_H_ADDR 0x32 -#define DTMF_NCF_L_ADDR 0x33 -#define DTMF_NBW_H_ADDR 0x34 -#define DTMF_NBW_L_ADDR 0x35 -#define DTMF_GAIN_ADDR 0x36 -#define DTMF_RES1_ADDR 0x37 -#define DTMF_RES2_ADDR 0x38 -#define DTMF_RES3_ADDR 0x39 - -#define CIS_LEV_H_ADDR 0x43 -#define CIS_LEV_L_ADDR 0x44 -#define CIS_BRS_ADDR 0x45 -#define CIS_SEIZ_H_ADDR 0x46 -#define CIS_SEIZ_L_ADDR 0x47 -#define CIS_MARK_H_ADDR 0x48 -#define CIS_MARK_L_ADDR 0x49 -#define CIS_LEC_MODE_ADDR 0x4A - -/*=====================================*/ - -#define HOOK_LEV_ACT_START_ADDR 0x89 -#define RO1_START_ADDR 0x70 -#define RO2_START_ADDR 0x95 -#define RO3_START_ADDR 0x96 - -#define TG1_FREQ_START_ADDR 0x38 -#define TG1_GAIN_START_ADDR 0x39 -#define TG1_BANDPASS_START_ADDR 0x3B -#define TG1_BANDPASS_END_ADDR 0x3D - -#define TG2_FREQ_START_ADDR 0x40 -#define TG2_GAIN_START_ADDR 0x41 -#define TG2_BANDPASS_START_ADDR 0x43 -#define TG2_BANDPASS_END_ADDR 0x45 - -/*====================================*/ - -#define PCM_HW_B 0x80 -#define PCM_HW_A 0x00 -#define PCM_TIME_SLOT_0 0x00 /* Byte 0 of PCM Frame (by default is assigned to channel A ) */ -#define PCM_TIME_SLOT_1 0x01 /* Byte 1 of PCM Frame (by default is assigned to channel B ) */ -#define PCM_TIME_SLOT_4 0x04 /* Byte 4 of PCM Frame (Corresponds to B1 of the Second GCI ) */ - -#define RX_LEV_ADDR 0x28 -#define TX_LEV_ADDR 0x30 -#define Ik1_ADDR 0x83 - -#define AR_ROW 3 /* Is the row (AR Params) of the ac_Coeff array in SMS_CODEC_Defaults struct */ -#define AX_ROW 6 /* Is the row (AX Params) of the ac_Coeff array in SMS_CODEC_Defaults struct */ -#define DCF_ROW 0 /* Is the row (DCF Params) of the dc_Coeff array in SMS_CODEC_Defaults struct */ - -/* Mark the start byte of Duslic parameters that we use with configurator */ -#define Ik1_START_BYTE 3 -#define RX_LEV_START_BYTE 0 -#define TX_LEV_START_BYTE 0 - -/************************************************/ - -#define INTREG4_CIS_ACT (1 << 0) - -#define BCR1_SLEEP 0x20 -#define BCR1_REVPOL 0x10 -#define BCR1_ACTR 0x08 -#define BCR1_ACTL 0x04 -#define BCR1_SLIC_MASK 0x03 - -#define BCR2_HARD_POL_REV 0x40 -#define BCR2_TTX 0x20 -#define BCR2_TTX_12K 0x10 -#define BCR2_HIMAN 0x08 -#define BCR2_PDOT 0x01 - -#define BCR3_PCMX_EN (1 << 4) - -#define BCR5_DTMF_EN (1 << 0) -#define BCR5_DTMF_SRC (1 << 1) -#define BCR5_LEC_EN (1 << 2) -#define BCR5_LEC_OUT (1 << 3) -#define BCR5_CIS_EN (1 << 4) -#define BCR5_CIS_AUTO (1 << 5) -#define BCR5_UTDX_EN (1 << 6) -#define BCR5_UTDR_EN (1 << 7) - -#define DSCR_TG1_EN (1 << 0) -#define DSCR_TG2_EN (1 << 1) -#define DSCR_PTG (1 << 2) -#define DSCR_COR8 (1 << 3) -#define DSCR_DG_KEY(x) (((x) & 0x0F) << 4) - -#define CIS_LEC_MODE_CIS_V23 (1 << 0) -#define CIS_LEC_MODE_CIS_FRM (1 << 1) -#define CIS_LEC_MODE_NLP_EN (1 << 2) -#define CIS_LEC_MODE_UTDR_SUM (1 << 4) -#define CIS_LEC_MODE_UTDX_SUM (1 << 5) -#define CIS_LEC_MODE_LEC_FREEZE (1 << 6) -#define CIS_LEC_MODE_LEC_ADAPT (1 << 7) - -#define TSTR4_COR_64 (1 << 5) - -#define TSTR3_AC_DLB_8K (1 << 2) -#define TSTR3_AC_DLB_32K (1 << 3) -#define TSTR3_AC_DLB_4M (1 << 5) - - -#define LMCR1_TEST_EN (1 << 7) -#define LMCR1_LM_EN (1 << 6) -#define LMCR1_LM_THM (1 << 5) -#define LMCR1_LM_ONCE (1 << 2) -#define LMCR1_LM_MASK (1 << 1) - -#define LMCR2_LM_RECT (1 << 5) -#define LMCR2_LM_SEL_VDD 0x0D -#define LMCR2_LM_SEL_IO3 0x0A -#define LMCR2_LM_SEL_IO4 0x0B -#define LMCR2_LM_SEL_IO4_MINUS_IO3 0x0F - -#define LMCR3_RTR_SEL (1 << 6) - -#define LMCR3_RNG_OFFSET_NONE 0x00 -#define LMCR3_RNG_OFFSET_1 0x01 -#define LMCR3_RNG_OFFSET_2 0x02 -#define LMCR3_RNG_OFFSET_3 0x03 - -#define TSTR5_DC_HOLD (1 << 3) - -/************************************************/ - -#define TARGET_ONHOOK_BATH_x100 4600 /* 46.0 Volt */ -#define TARGET_ONHOOK_BATL_x100 2500 /* 25.0 Volt */ -#define TARGET_V_DIVIDER_RATIO_x100 21376L /* (R1+R2)/R2 = 213.76 */ -#define DIVIDER_RATIO_ACCURx100 (22 * 100) -#define V_AD_x10000 10834L /* VAD = 1.0834 */ -#define TARGET_VDDx100 330 /* VDD = 3.3 * 10 */ -#define VDD_MAX_DIFFx100 20 /* VDD Accur = 0.2*100 */ - -#define RMS_MULTIPLIERx100 111 /* pi/(2xsqrt(2)) = 1.11*/ -#define K_INTDC_RECT_ON 4 /* When Rectifier is ON this value is necessary(2^4) */ -#define K_INTDC_RECT_OFF 2 /* 2^2 */ -#define RNG_FREQ 25 -#define SAMPLING_FREQ (2000L) -#define N_SAMPLES (SAMPLING_FREQ/RNG_FREQ) /* for Ring Freq =25Hz (40ms Integration Period)[Sampling rate 2KHz -->1 Sample every 500us] */ -#define HOOK_THRESH_RING_START_ADDR 0x8B -#define RING_PARAMS_START_ADDR 0x70 - -#define V_OUT_BATH_MAX_DIFFx100 300 /* 3.0 x100 */ -#define V_OUT_BATL_MAX_DIFFx100 400 /* 4.0 x100 */ -#define MAX_V_RING_MEANx100 50 -#define TARGET_V_RING_RMSx100 2720 -#define V_RMS_RING_MAX_DIFFx100 250 - -#define LM_OK_SRC_IRG_2 (1 << 4) - -/************************************************/ - -#define PORTB (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) -#define PORTC (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) -#define PORTD (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) - -#define _PORTD_SET(mask, state) \ - do { \ - if (state) \ - PORTD |= mask; \ - else \ - PORTD &= ~mask; \ - } while (0) - -#define _PORTB_SET(mask, state) \ - do { \ - if (state) \ - PORTB |= mask; \ - else \ - PORTB &= ~mask; \ - } while (0) - -#define _PORTB_TGL(mask) do { PORTB ^= mask; } while (0) -#define _PORTB_GET(mask) (!!(PORTB & mask)) - -#define _PORTC_GET(mask) (!!(PORTC & mask)) - -/* port B */ -#define SPI_RXD (1 << (31 - 28)) -#define SPI_TXD (1 << (31 - 29)) -#define SPI_CLK (1 << (31 - 30)) - -/* port C */ -#define COM_HOOK1 (1 << (15 - 9)) -#define COM_HOOK2 (1 << (15 - 10)) - -#ifndef CONFIG_NETTA_SWAPHOOK - -#define COM_HOOK3 (1 << (15 - 11)) -#define COM_HOOK4 (1 << (15 - 12)) - -#else - -#define COM_HOOK3 (1 << (15 - 12)) -#define COM_HOOK4 (1 << (15 - 11)) - -#endif - -/* port D */ -#define SPIENC1 (1 << (15 - 9)) -#define SPIENC2 (1 << (15 - 10)) -#define SPIENC3 (1 << (15 - 11)) -#define SPIENC4 (1 << (15 - 14)) - -#define SPI_DELAY() udelay(1) - -static inline unsigned int __SPI_Transfer(unsigned int tx) -{ - unsigned int rx; - int b; - - rx = 0; b = 8; - while (--b >= 0) { - _PORTB_SET(SPI_TXD, tx & 0x80); - tx <<= 1; - _PORTB_TGL(SPI_CLK); - SPI_DELAY(); - rx <<= 1; - rx |= _PORTB_GET(SPI_RXD); - _PORTB_TGL(SPI_CLK); - SPI_DELAY(); - } - - return rx; -} - -static const char *codsp_dtmf_map = "D1234567890*#ABC"; - -static const int spienc_mask_tab[4] = { SPIENC1, SPIENC2, SPIENC3, SPIENC4 }; -static const int com_hook_mask_tab[4] = { COM_HOOK1, COM_HOOK2, COM_HOOK3, COM_HOOK4 }; - -static unsigned int codsp_send(int duslic_id, const unsigned char *cmd, int cmdlen, unsigned char *res, int reslen) -{ - unsigned int rx; - int i; - - /* just some sanity checks */ - if (cmd == 0 || cmdlen < 0) - return -1; - - _PORTD_SET(spienc_mask_tab[duslic_id], 0); - - /* first 2 bytes are without response */ - i = 2; - while (i-- > 0 && cmdlen-- > 0) - __SPI_Transfer(*cmd++); - - while (cmdlen-- > 0) { - rx = __SPI_Transfer(*cmd++); - if (res != 0 && reslen-- > 0) - *res++ = (unsigned char)rx; - } - if (res != 0) { - while (reslen-- > 0) - *res++ = __SPI_Transfer(0xFF); - } - - _PORTD_SET(spienc_mask_tab[duslic_id], 1); - - return 0; -} - -/****************************************************************************/ - -void codsp_set_ciop_m(int duslic_id, int channel, unsigned char m) -{ - unsigned char cmd = CODSP_WR | CODSP_ADR(channel) | CODSP_M(m); - codsp_send(duslic_id, &cmd, 1, 0, 0); -} - -void codsp_reset_chip(int duslic_id) -{ - static const unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_CMD_SOFT_RESET; - codsp_send(duslic_id, &cmd, 1, 0, 0); -} - -void codsp_reset_channel(int duslic_id, int channel) -{ - unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESET_CH; - codsp_send(duslic_id, &cmd, 1, 0, 0); -} - -void codsp_resync_channel(int duslic_id, int channel) -{ - unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESYNC; - codsp_send(duslic_id, &cmd, 1, 0, 0); -} - -/****************************************************************************/ - -void codsp_write_sop_char(int duslic_id, int channel, unsigned char regno, unsigned char val) -{ - unsigned char cmd[3]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP; - cmd[1] = regno; - cmd[2] = val; - - codsp_send(duslic_id, cmd, 3, 0, 0); -} - -void codsp_write_sop_short(int duslic_id, int channel, unsigned char regno, unsigned short val) -{ - unsigned char cmd[4]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP; - cmd[1] = regno; - cmd[2] = (unsigned char)(val >> 8); - cmd[3] = (unsigned char)val; - - codsp_send(duslic_id, cmd, 4, 0, 0); -} - -void codsp_write_sop_int(int duslic_id, int channel, unsigned char regno, unsigned int val) -{ - unsigned char cmd[6]; - - cmd[0] = CODSP_WR | CODSP_ADR(channel) | CODSP_CMD_SOP; - cmd[1] = regno; - cmd[2] = (unsigned char)(val >> 24); - cmd[3] = (unsigned char)(val >> 16); - cmd[4] = (unsigned char)(val >> 8); - cmd[5] = (unsigned char)val; - - codsp_send(duslic_id, cmd, 6, 0, 0); -} - -unsigned char codsp_read_sop_char(int duslic_id, int channel, unsigned char regno) -{ - unsigned char cmd[3]; - unsigned char res[2]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP; - cmd[1] = regno; - - codsp_send(duslic_id, cmd, 2, res, 2); - - return res[1]; -} - -unsigned short codsp_read_sop_short(int duslic_id, int channel, unsigned char regno) -{ - unsigned char cmd[2]; - unsigned char res[3]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP; - cmd[1] = regno; - - codsp_send(duslic_id, cmd, 2, res, 3); - - return ((unsigned short)res[1] << 8) | res[2]; -} - -unsigned int codsp_read_sop_int(int duslic_id, int channel, unsigned char regno) -{ - unsigned char cmd[2]; - unsigned char res[5]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP; - cmd[1] = regno; - - codsp_send(duslic_id, cmd, 2, res, 5); - - return ((unsigned int)res[1] << 24) | ((unsigned int)res[2] << 16) | ((unsigned int)res[3] << 8) | res[4]; -} - -/****************************************************************************/ - -void codsp_write_cop_block(int duslic_id, int channel, unsigned char addr, const unsigned char *block) -{ - unsigned char cmd[10]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; - cmd[1] = addr; - memcpy(cmd + 2, block, 8); - codsp_send(duslic_id, cmd, 10, 0, 0); -} - -void codsp_write_cop_char(int duslic_id, int channel, unsigned char addr, unsigned char val) -{ - unsigned char cmd[3]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; - cmd[1] = addr; - cmd[2] = val; - codsp_send(duslic_id, cmd, 3, 0, 0); -} - -void codsp_write_cop_short(int duslic_id, int channel, unsigned char addr, unsigned short val) -{ - unsigned char cmd[4]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; - cmd[1] = addr; - cmd[2] = (unsigned char)(val >> 8); - cmd[3] = (unsigned char)val; - - codsp_send(duslic_id, cmd, 4, 0, 0); -} - -void codsp_read_cop_block(int duslic_id, int channel, unsigned char addr, unsigned char *block) -{ - unsigned char cmd[2]; - unsigned char res[9]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; - cmd[1] = addr; - codsp_send(duslic_id, cmd, 2, res, 9); - memcpy(block, res + 1, 8); -} - -unsigned char codsp_read_cop_char(int duslic_id, int channel, unsigned char addr) -{ - unsigned char cmd[2]; - unsigned char res[2]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; - cmd[1] = addr; - codsp_send(duslic_id, cmd, 2, res, 2); - return res[1]; -} - -unsigned short codsp_read_cop_short(int duslic_id, int channel, unsigned char addr) -{ - unsigned char cmd[2]; - unsigned char res[3]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; - cmd[1] = addr; - - codsp_send(duslic_id, cmd, 2, res, 3); - - return ((unsigned short)res[1] << 8) | res[2]; -} - -/****************************************************************************/ - -#define MAX_POP_BLOCK 50 - -void codsp_write_pop_block (int duslic_id, int channel, unsigned char addr, - const unsigned char *block, int len) -{ - unsigned char cmd[2 + MAX_POP_BLOCK]; - - if (len > MAX_POP_BLOCK) /* truncate */ - len = MAX_POP_BLOCK; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = addr; - memcpy (cmd + 2, block, len); - codsp_send (duslic_id, cmd, 2 + len, 0, 0); -} - -void codsp_write_pop_char (int duslic_id, int channel, unsigned char regno, - unsigned char val) -{ - unsigned char cmd[3]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = regno; - cmd[2] = val; - - codsp_send (duslic_id, cmd, 3, 0, 0); -} - -void codsp_write_pop_short (int duslic_id, int channel, unsigned char regno, - unsigned short val) -{ - unsigned char cmd[4]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = regno; - cmd[2] = (unsigned char) (val >> 8); - cmd[3] = (unsigned char) val; - - codsp_send (duslic_id, cmd, 4, 0, 0); -} - -void codsp_write_pop_int (int duslic_id, int channel, unsigned char regno, - unsigned int val) -{ - unsigned char cmd[6]; - - cmd[0] = CODSP_WR | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = regno; - cmd[2] = (unsigned char) (val >> 24); - cmd[3] = (unsigned char) (val >> 16); - cmd[4] = (unsigned char) (val >> 8); - cmd[5] = (unsigned char) val; - - codsp_send (duslic_id, cmd, 6, 0, 0); -} - -unsigned char codsp_read_pop_char (int duslic_id, int channel, - unsigned char regno) -{ - unsigned char cmd[3]; - unsigned char res[2]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = regno; - - codsp_send (duslic_id, cmd, 2, res, 2); - - return res[1]; -} - -unsigned short codsp_read_pop_short (int duslic_id, int channel, - unsigned char regno) -{ - unsigned char cmd[2]; - unsigned char res[3]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = regno; - - codsp_send (duslic_id, cmd, 2, res, 3); - - return ((unsigned short) res[1] << 8) | res[2]; -} - -unsigned int codsp_read_pop_int (int duslic_id, int channel, - unsigned char regno) -{ - unsigned char cmd[2]; - unsigned char res[5]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = regno; - - codsp_send (duslic_id, cmd, 2, res, 5); - - return (((unsigned int) res[1] << 24) | - ((unsigned int) res[2] << 16) | - ((unsigned int) res[3] << 8) | - res[4] ); -} -/****************************************************************************/ - -struct _coeffs { - unsigned char addr; - unsigned char values[8]; -}; - -struct _coeffs ac_coeffs[11] = { - { 0x60, {0xAD,0xDA,0xB5,0x9B,0xC7,0x2A,0x9D,0x00} }, /* 0x60 IM-Filter part 1 */ - { 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x77,0x0A,0x00} }, /* 0x68 IM-Filter part 2 */ - { 0x18, {0x08,0xC0,0xD2,0xAB,0xA5,0xE2,0xAB,0x07} }, /* 0x18 FRR-Filter */ - { 0x28, {0x44,0x93,0xF5,0x92,0x88,0x00,0x00,0x00} }, /* 0x28 AR-Filter */ - { 0x48, {0x96,0x38,0x29,0x96,0xC9,0x2B,0x8B,0x00} }, /* 0x48 LPR-Filter */ - { 0x20, {0x08,0xB0,0xDA,0x9D,0xA7,0xFA,0x93,0x06} }, /* 0x20 FRX-Filter */ - { 0x30, {0xBA,0xAC,0x00,0x01,0x85,0x50,0xC0,0x1A} }, /* 0x30 AX-Filter */ - { 0x50, {0x96,0x38,0x29,0xF5,0xFA,0x2B,0x8B,0x00} }, /* 0x50 LPX-Filter */ - { 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} }, /* 0x00 TH-Filter part 1 */ - { 0x08, {0x81,0x00,0x80,0x00,0xD7,0x33,0xBA,0x01} }, /* 0x08 TH-Filter part 2 */ - { 0x10, {0xB3,0x6C,0xDC,0xA3,0xA4,0xE5,0x88,0x00} } /* 0x10 TH-Filter part 3 */ -}; - -struct _coeffs ac_coeffs_0dB[11] = { - { 0x60, {0xAC,0x2A,0xB5,0x9A,0xB7,0x2A,0x9D,0x00} }, - { 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x83,0x0A,0x00} }, - { 0x18, {0x08,0x20,0xD4,0xA4,0x65,0xEE,0x92,0x07} }, - { 0x28, {0x2B,0xAB,0x36,0xA5,0x88,0x00,0x00,0x00} }, - { 0x48, {0xAB,0xE9,0x4E,0x32,0xAB,0x25,0xA5,0x03} }, - { 0x20, {0x08,0x20,0xDB,0x9C,0xA7,0xFA,0xB4,0x07} }, - { 0x30, {0xF3,0x10,0x07,0x60,0x85,0x40,0xC0,0x1A} }, - { 0x50, {0x96,0x38,0x29,0x97,0x39,0x19,0x8B,0x00} }, - { 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} }, - { 0x08, {0x81,0x00,0x80,0x00,0x47,0x3C,0xD2,0x01} }, - { 0x10, {0x62,0xDB,0x4A,0x87,0x73,0x28,0x88,0x00} } -}; - -struct _coeffs dc_coeffs[9] = { - { 0x80, {0x25,0x59,0x9C,0x23,0x24,0x23,0x32,0x1C} }, /* 0x80 DC-Parameter */ - { 0x70, {0x90,0x30,0x1B,0xC0,0x33,0x43,0xAC,0x02} }, /* 0x70 Ringing */ - { 0x90, {0x3F,0xC3,0x2E,0x3A,0x80,0x90,0x00,0x09} }, /* 0x90 LP-Filters */ - { 0x88, {0xAF,0x80,0x27,0x7B,0x01,0x4C,0x7B,0x02} }, /* 0x88 Hook Levels */ - { 0x78, {0x00,0xC0,0x6D,0x7A,0xB3,0x78,0x89,0x00} }, /* 0x78 Ramp Generator */ - { 0x58, {0xA5,0x44,0x34,0xDB,0x0E,0xA2,0x2A,0x00} }, /* 0x58 TTX */ - { 0x38, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x38 TG1 */ - { 0x40, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x40 TG2 */ - { 0x98, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} } /* 0x98 Reserved */ -}; - -void program_coeffs(int duslic_id, int channel, struct _coeffs *coeffs, int tab_size) -{ - int i; - - for (i = 0; i < tab_size; i++) - codsp_write_cop_block(duslic_id, channel, coeffs[i].addr, coeffs[i].values); -} - -#define SS_OPEN_CIRCUIT 0 -#define SS_RING_PAUSE 1 -#define SS_ACTIVE 2 -#define SS_ACTIVE_HIGH 3 -#define SS_ACTIVE_RING 4 -#define SS_RINGING 5 -#define SS_ACTIVE_WITH_METERING 6 -#define SS_ONHOOKTRNSM 7 -#define SS_STANDBY 8 -#define SS_MAX 8 - -static void codsp_set_slic(int duslic_id, int channel, int state) -{ - unsigned char v; - - v = codsp_read_sop_char(duslic_id, channel, BCR1_ADDR); - - switch (state) { - - case SS_ACTIVE: - codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTR) | BCR1_ACTL); - codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT); - break; - - case SS_ACTIVE_HIGH: - codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTR | BCR1_ACTL)); - codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT); - break; - - case SS_ACTIVE_RING: - case SS_ONHOOKTRNSM: - codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTL) | BCR1_ACTR); - codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT); - break; - - case SS_STANDBY: - codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTL | BCR1_ACTR)); - codsp_set_ciop_m(duslic_id, channel, CODSP_M_SLEEP_PWRDN); - break; - - case SS_OPEN_CIRCUIT: - codsp_set_ciop_m(duslic_id, channel, CODSP_M_PWRDN_HIZ); - break; - - case SS_RINGING: - codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING); - break; - - case SS_RING_PAUSE: - codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING_PAUSE); - break; - } -} - -const unsigned char Ring_Sin_28Vrms_25Hz[8] = { 0x90, 0x30, 0x1B, 0xC0, 0xC3, 0x9C, 0x88, 0x00 }; -const unsigned char Max_HookRingTh[3] = { 0x7B, 0x41, 0x62 }; - -void retrieve_slic_state(int slic_id) -{ - int duslic_id = slic_id >> 1; - int channel = slic_id & 1; - - /* Retrieve the state of the SLICs */ - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00); - - /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */ - udelay(10000); - - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK); - codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); - codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40); - - /* Program Default Hook Ring thresholds */ - codsp_write_cop_block(duslic_id, channel, dc_coeffs[1].addr, dc_coeffs[1].values); - - /* Now program Hook Threshold while Ring and ac RingTrip to max values */ - codsp_write_cop_block(duslic_id, channel, dc_coeffs[3].addr, dc_coeffs[3].values); - - codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000); - - udelay(40000); -} - -int wait_level_metering_finish(int duslic_id, int channel) -{ - int cnt; - - for (cnt = 0; cnt < 1000 && - (codsp_read_sop_char(duslic_id, channel, INTREG2_ADDR) & LM_OK_SRC_IRG_2) == 0; cnt++) { } - - return cnt != 1000; -} - -int measure_on_hook_voltages(int slic_id, long *vdd, - long *v_oh_H, long *v_oh_L, long *ring_mean_v, long *ring_rms_v) -{ - short LM_Result, Offset_Compensation; /* Signed 16 bit */ - long int VDD, VDD_diff, V_in, V_out, Divider_Ratio, Vout_diff ; - unsigned char err_mask = 0; - int duslic_id = slic_id >> 1; - int channel = slic_id & 1; - int i; - - /* measure VDD */ - /* Now select the VDD level Measurement (but first of all Hold the DC characteristic) */ - codsp_write_sop_char(duslic_id, channel, TSTR5_ADDR, TSTR5_DC_HOLD); - - /* Activate Test Mode ==> To Enable DC Hold !!! */ - /* (else the LMRES is treated as Feeding Current and the Feeding voltage changes */ - /* imediatelly (after 500us when the LMRES Registers is updated for the first time after selection of (IO4-IO3) measurement !!!!))*/ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK); - - udelay(40000); - - /* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */ - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_VDD); - - /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */ - udelay(10000); - - /* Now Read the LM Result Registers */ - LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - VDD = (-1)*((((long int)LM_Result) * 390L ) >> 15) ; /* VDDx100 */ - - *vdd = VDD; - - VDD_diff = VDD - TARGET_VDDx100; - - if (VDD_diff < 0) - VDD_diff = -VDD_diff; - - if (VDD_diff > VDD_MAX_DIFFx100) - err_mask |= 1; - - Divider_Ratio = TARGET_V_DIVIDER_RATIO_x100; - - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00); - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK); - - codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); /* Go back to ONHOOK Voltage */ - - udelay(40000); - - codsp_write_sop_char(duslic_id, channel, - LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK); - - udelay(40000); - - /* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */ - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3); - - /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */ - udelay(10000); - - /* Now Read the LM Result Registers */ - LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ; /* Vin x 10000*/ - - V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */ - - *v_oh_H = V_out; - - Vout_diff = V_out - TARGET_ONHOOK_BATH_x100; - - if (Vout_diff < 0) - Vout_diff = -Vout_diff; - - if (Vout_diff > V_OUT_BATH_MAX_DIFFx100) - err_mask |= 2; - - codsp_set_slic(duslic_id, channel, SS_ACTIVE); /* Go back to ONHOOK Voltage */ - - udelay(40000); - - /* Now Read the LM Result Registers */ - LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - - V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ; /* Vin x 10000*/ - - V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */ - - *v_oh_L = V_out; - - Vout_diff = V_out - TARGET_ONHOOK_BATL_x100; - - if (Vout_diff < 0) - Vout_diff = -Vout_diff; - - if (Vout_diff > V_OUT_BATL_MAX_DIFFx100) - err_mask |= 4; - - /* perform ring tests */ - - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00); - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK); - - udelay(40000); - - codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, LMCR3_RTR_SEL | LMCR3_RNG_OFFSET_NONE); - - /* Now program RO1 =0V , Ring Amplitude and frequency and shift factor K = 1 (LMDC=0x0088)*/ - codsp_write_cop_block(duslic_id, channel, RING_PARAMS_START_ADDR, Ring_Sin_28Vrms_25Hz); - - /* By Default RO1 is selected when ringing RNG-OFFSET = 00 */ - - /* Now program Hook Threshold while Ring and ac RingTrip to max values */ - for(i = 0; i < sizeof(Max_HookRingTh); i++) - codsp_write_cop_char(duslic_id, channel, HOOK_THRESH_RING_START_ADDR + i, Max_HookRingTh[i]); - - codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000); - - codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */ - - /* select source for the levelmeter to be IO4-IO3 */ - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3); - - udelay(40000); - - /* Before Enabling Level Meter Programm the apropriate shift factor K_INTDC=(4 if Rectifier Enabled and 2 if Rectifier Disabled) */ - codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_OFF); - - udelay(10000); - - /* Enable LevelMeter to Integrate only once (Rectifier Disabled) */ - codsp_write_sop_char(duslic_id, channel, - LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE); - - udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */ - - if (wait_level_metering_finish(duslic_id, channel)) { - - udelay(10000); /* To be sure that Integration Results are Valid wait at least 500us !!! */ - - /* Now Read the LM Result Registers (Will be valid until LM_EN becomes zero again( after that the Result is updated every 500us) ) */ - Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_OFF)) / N_SAMPLES); - - /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE); - - /* Now programm Integrator Offset Registers !!! */ - codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation); - - codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing */ - - udelay(40000); - - /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */ - codsp_write_sop_char(duslic_id, channel, - LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE); - - udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */ - - /* Poll the LM_OK bit to see when Integration Result is Ready */ - if (wait_level_metering_finish(duslic_id, channel)) { - - udelay(10000); /* wait at least 500us to be sure that the Integration Result are valid !!! */ - - /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */ - /* ==>After that Result Regs will be updated every 500us !!!) */ - LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_OFF)) ; /* Vin x 10000*/ - - V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */ - - if (V_out < 0) - V_out= -V_out; - - if (V_out > MAX_V_RING_MEANx100) - err_mask |= 8; - - *ring_mean_v = V_out; - } else { - err_mask |= 8; - *ring_mean_v = 0; - } - } else { - err_mask |= 8; - *ring_mean_v = 0; - } - - /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, - LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE); - codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000); - - codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */ - - /* Now Enable Rectifier */ - /* select source for the levelmeter to be IO4-IO3 */ - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, - LMCR2_LM_SEL_IO4_MINUS_IO3 | LMCR2_LM_RECT); - - /* Program the apropriate shift factor K_INTDC (in order to avoid Overflow at Integtation Result !!!) */ - codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_ON); - - udelay(40000); - - /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, - LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE); - - udelay(40000); - - /* Poll the LM_OK bit to see when Integration Result is Ready */ - if (wait_level_metering_finish(duslic_id, channel)) { - - udelay(10000); - - /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */ - /* ==>After that Result Regs will be updated every 500us !!!) */ - Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_ON)) / N_SAMPLES); - - /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE); - - /* Now programm Integrator Offset Registers !!! */ - codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation); - - /* Be sure that a Ring is generated !!!! */ - codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing again */ - - udelay(40000); - - /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, - LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE); - - udelay(40000); - - /* Poll the LM_OK bit to see when Integration Result is Ready */ - if (wait_level_metering_finish(duslic_id, channel)) { - - udelay(10000); - - /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */ - /* ==>After that Result Regs will be updated every 500us !!!) */ - LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_ON) ) ; /* Vin x 10000*/ - - V_out = (((V_in * Divider_Ratio) / 10000L) * RMS_MULTIPLIERx100) / 100 ; /* Vout_RMS x100 */ - if (V_out < 0) - V_out = -V_out; - - Vout_diff = (V_out - TARGET_V_RING_RMSx100); - - if (Vout_diff < 0) - Vout_diff = -Vout_diff; - - if (Vout_diff > V_RMS_RING_MAX_DIFFx100) - err_mask |= 16; - - *ring_rms_v = V_out; - } else { - err_mask |= 16; - *ring_rms_v = 0; - } - } else { - err_mask |= 16; - *ring_rms_v = 0; - } - /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK); - - retrieve_slic_state(slic_id); - - return(err_mask); -} - -int test_dtmf(int slic_id) -{ - unsigned char code; - unsigned char b; - unsigned int intreg; - int duslic_id = slic_id >> 1; - int channel = slic_id & 1; - - for (code = 0; code < 16; code++) { - b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); - codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, - (b & ~(DSCR_PTG | DSCR_DG_KEY(15))) | DSCR_DG_KEY(code) | DSCR_TG1_EN | DSCR_TG2_EN); - udelay(80000); - - intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR); - if ((intreg & CODSP_INTREG_INT_CH) == 0) - break; - - if ((intreg & CODSP_INTREG_DTMF_OK) == 0 || - codsp_dtmf_map[(intreg >> 10) & 15] != codsp_dtmf_map[code]) - break; - - b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); - codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, - b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN)); - - udelay(80000); - - intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR); /* for dtmf_pause irq */ - } - - if (code != 16) { - b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); /* stop dtmf */ - codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, - b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN)); - return(1); - } - - return(0); -} - -void data_up_persist_time(int duslic_id, int channel, int time_ms) -{ - unsigned char b; - - b = codsp_read_sop_char(duslic_id, channel, IOCTL3_ADDR); - b = (b & 0x0F) | ((time_ms & 0x0F) << 4); - codsp_write_sop_char(duslic_id, channel, IOCTL3_ADDR, b); -} - -static void program_dtmf_params(int duslic_id, int channel) -{ - unsigned char b; - - codsp_write_pop_char(duslic_id, channel, DTMF_LEV_ADDR, 0x10); - codsp_write_pop_char(duslic_id, channel, DTMF_TWI_ADDR, 0x0C); - codsp_write_pop_char(duslic_id, channel, DTMF_NCF_H_ADDR, 0x79); - codsp_write_pop_char(duslic_id, channel, DTMF_NCF_L_ADDR, 0x10); - codsp_write_pop_char(duslic_id, channel, DTMF_NBW_H_ADDR, 0x02); - codsp_write_pop_char(duslic_id, channel, DTMF_NBW_L_ADDR, 0xFB); - codsp_write_pop_char(duslic_id, channel, DTMF_GAIN_ADDR, 0x91); - codsp_write_pop_char(duslic_id, channel, DTMF_RES1_ADDR, 0x00); - codsp_write_pop_char(duslic_id, channel, DTMF_RES2_ADDR, 0x00); - codsp_write_pop_char(duslic_id, channel, DTMF_RES3_ADDR, 0x00); - - b = codsp_read_sop_char(duslic_id, channel, BCR5_ADDR); - codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, b | BCR5_DTMF_EN); -} - -static void codsp_channel_full_reset(int duslic_id, int channel) -{ - - program_coeffs(duslic_id, channel, ac_coeffs, sizeof(ac_coeffs) / sizeof(struct _coeffs)); - program_coeffs(duslic_id, channel, dc_coeffs, sizeof(dc_coeffs) / sizeof(struct _coeffs)); - - /* program basic configuration registers */ - codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, 0x01); - codsp_write_sop_char(duslic_id, channel, BCR2_ADDR, 0x41); - codsp_write_sop_char(duslic_id, channel, BCR3_ADDR, 0x43); - codsp_write_sop_char(duslic_id, channel, BCR4_ADDR, 0x00); - codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, 0x00); - - codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, 0x04); /* PG */ - - program_dtmf_params(duslic_id, channel); - - codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40); /* RingTRip_SEL */ - - data_up_persist_time(duslic_id, channel, 4); - - codsp_write_sop_char(duslic_id, channel, MASK_ADDR, 0xFF); /* All interrupts masked */ - - codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); -} - -static int codsp_chip_full_reset(int duslic_id) -{ - int i, cnt; - int intreg[NUM_CHANNELS]; - unsigned char pcm_resync; - unsigned char revision; - - codsp_reset_chip(duslic_id); - - udelay(2000); - - for (i = 0; i < NUM_CHANNELS; i++) - intreg[i] = codsp_read_sop_int(duslic_id, i, INTREG1_ADDR); - - udelay(1500); - - if (_PORTC_GET(com_hook_mask_tab[duslic_id]) == 0) { - printf("_HOOK(%d) stayed low\n", duslic_id); - return -1; - } - - for (pcm_resync = 0, i = 0; i < NUM_CHANNELS; i++) { - if (intreg[i] & CODSP_INTREG_SYNC_FAIL) - pcm_resync |= 1 << i; - } - - for (cnt = 0; cnt < 5 && pcm_resync; cnt++) { - for (i = 0; i < NUM_CHANNELS; i++) - codsp_resync_channel(duslic_id, i); - - udelay(2000); - - pcm_resync = 0; - - for (i = 0; i < NUM_CHANNELS; i++) { - if (codsp_read_sop_int(duslic_id, i, INTREG1_ADDR) & CODSP_INTREG_SYNC_FAIL) - pcm_resync |= 1 << i; - } - } - - if (cnt == 5) { - printf("PCM_Resync(%u) not completed\n", duslic_id); - return -2; - } - - revision = codsp_read_sop_char(duslic_id, 0, REVISION_ADDR); - printf("DuSLIC#%d hardware version %d.%d\r\n", duslic_id, (revision & 0xF0) >> 4, revision & 0x0F); - - codsp_write_sop_char(duslic_id, 0, XCR_ADDR, 0x80); /* EDSP_EN */ - - for (i = 0; i < NUM_CHANNELS; i++) { - codsp_write_sop_char(duslic_id, i, PCMC1_ADDR, 0x01); - codsp_channel_full_reset(duslic_id, i); - } - - return 0; -} - -int slic_self_test(int duslic_mask) -{ - int slic; - int i; - int r; - long vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v; - const char *err_txt[] = { "VDD", "V_OH_H", "V_OH_L", "V_RING_MEAN", "V_RING_RMS" }; - int error = 0; - - for (slic = 0; slic < MAX_SLICS; slic++) { /* voltages self test */ - if (duslic_mask & (1 << (slic >> 1))) { - r = measure_on_hook_voltages(slic, &vdd, - &v_oh_H, &v_oh_L, &ring_mean_v, &ring_rms_v); - - printf("SLIC %u measured voltages (x100):\n\t" - "VDD = %ld\tV_OH_H = %ld\tV_OH_L = %ld\tV_RING_MEAN = %ld\tV_RING_RMS = %ld\n", - slic, vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v); - - if (r != 0) - error |= 1 << slic; - - for (i = 0; i < 5; i++) - if (r & (1 << i)) - printf("\t%s out of range\n", err_txt[i]); - } - } - - for (slic = 0; slic < MAX_SLICS; slic++) { /* voice path self test */ - if (duslic_mask & (1 << (slic >> 1))) { - printf("SLIC %u VOICE PATH...CHECKING", slic); - printf("\rSLIC %u VOICE PATH...%s\n", slic, - (r = test_dtmf(slic)) != 0 ? "FAILED " : "PASSED "); - - if (r != 0) - error |= 1 << slic; - } - } - - return(error); -} - -#if defined(CONFIG_NETTA_ISDN) - -#define SPIENS1 (1 << (31 - 15)) -#define SPIENS2 (1 << (31 - 19)) - -static const int spiens_mask_tab[2] = { SPIENS1, SPIENS2 }; -int s_initialized = 0; - -static inline unsigned int s_transfer_internal(int s_id, unsigned int address, unsigned int value) -{ - unsigned int rx, v; - - _PORTB_SET(spiens_mask_tab[s_id], 0); - - rx = __SPI_Transfer(address); - - switch (address & 0xF0) { - case 0x60: /* write byte register */ - case 0x70: - rx = __SPI_Transfer(value); - break; - - case 0xE0: /* read R6 register */ - v = __SPI_Transfer(0); - - rx = (rx << 8) | v; - - break; - - case 0xF0: /* read byte register */ - rx = __SPI_Transfer(0); - - break; - } - - _PORTB_SET(spiens_mask_tab[s_id], 1); - - return rx; -} - -static void s_write_BR(int s_id, unsigned int regno, unsigned int val) -{ - unsigned int address; - - address = 0x70 | (regno & 15); - val &= 0xff; - - (void)s_transfer_internal(s_id, address, val); -} - -static void s_write_OR(int s_id, unsigned int regno, unsigned int val) -{ - unsigned int address; - - address = 0x70 | (regno & 15); - val &= 0xff; - - (void)s_transfer_internal(s_id, address, val); -} - -static void s_write_NR(int s_id, unsigned int regno, unsigned int val) -{ - unsigned int address; - - address = (regno & 7) << 4; - val &= 0xf; - - (void)s_transfer_internal(s_id, address | val, 0x00); -} - -#define BR7_IFR 0x08 /* IDL2 free run */ -#define BR7_ICSLSB 0x04 /* IDL2 clock speed LSB */ - -#define BR15_OVRL_REG_EN 0x80 -#define OR7_D3VR 0x80 /* disable 3V regulator */ - -#define OR8_TEME 0x10 /* TE mode enable */ -#define OR8_MME 0x08 /* master mode enable */ - -void s_initialize(void) -{ - int s_id; - - for (s_id = 0; s_id < 2; s_id++) { - s_write_BR(s_id, 7, BR7_IFR | BR7_ICSLSB); - s_write_BR(s_id, 15, BR15_OVRL_REG_EN); - s_write_OR(s_id, 8, OR8_TEME | OR8_MME); - s_write_OR(s_id, 7, OR7_D3VR); - s_write_OR(s_id, 6, 0); - s_write_BR(s_id, 15, 0); - s_write_NR(s_id, 3, 0); - } -} - -#endif - -int board_post_codec(int flags) -{ - int j; - int r; - int duslic_mask; - - printf("board_post_dsp\n"); - -#if defined(CONFIG_NETTA_ISDN) - if (s_initialized == 0) { - s_initialize(); - s_initialized = 1; - - printf("s_initialized\n"); - - udelay(20000); - } -#endif - duslic_mask = 0; - - for (j = 0; j < MAX_DUSLIC; j++) { - if (codsp_chip_full_reset(j) < 0) - printf("Error initializing DuSLIC#%d\n", j); - else - duslic_mask |= 1 << j; - } - - if (duslic_mask != 0) { - printf("Testing SLICs...\n"); - - r = slic_self_test(duslic_mask); - for (j = 0; j < MAX_SLICS; j++) { - if (duslic_mask & (1 << (j >> 1))) - printf("SLIC %u...%s\n", j, r & (1 << j) ? "FAULTY" : "OK"); - } - } - printf("DuSLIC self test finished\n"); - - return 0; /* return -1 on error */ -} diff --git a/board/netta/dsp.c b/board/netta/dsp.c deleted file mode 100644 index cd576476ec..0000000000 --- a/board/netta/dsp.c +++ /dev/null @@ -1,1208 +0,0 @@ -/* - * Intracom TI6711/TI6412 DSP - */ - -#include <common.h> -#include <post.h> - -#include "mpc8xx.h" - -struct ram_range { - u32 start; - u32 size; -}; - -#if defined(CONFIG_NETTA_6412) - -static const struct ram_range int_ram[] = { - { 0x00000000U, 0x00040000U }, -}; - -static const struct ram_range ext_ram[] = { - { 0x80000000U, 0x00100000U }, -}; - -static const struct ram_range ranges[] = { - { 0x00000000U, 0x00040000U }, - { 0x80000000U, 0x00100000U }, -}; - -static inline u16 bit_invert(u16 d) -{ - register u8 i; - register u16 r; - register u16 bit; - - r = 0; - for (i = 0; i < 16; i++) { - bit = d & (1 << i); - if (bit != 0) - r |= 1 << (15 - i); - } - return r; -} - -#else - -static const struct ram_range int_ram[] = { - { 0x00000000U, 0x00010000U }, -}; - -static const struct ram_range ext_ram[] = { - { 0x80000000U, 0x00100000U }, -}; - -static const struct ram_range ranges[] = { - { 0x00000000U, 0x00010000U }, - { 0x80000000U, 0x00100000U }, -}; - -#endif - -/*******************************************************************************************************/ - -static inline int addr_in_int_ram(u32 addr) -{ - int i; - - for (i = 0; i < sizeof(int_ram)/sizeof(int_ram[0]); i++) - if (addr >= int_ram[i].start && addr < int_ram[i].start + int_ram[i].size) - return 1; - - return 0; -} - -static inline int addr_in_ext_ram(u32 addr) -{ - int i; - - for (i = 0; i < sizeof(ext_ram)/sizeof(ext_ram[0]); i++) - if (addr >= ext_ram[i].start && addr < ext_ram[i].start + ext_ram[i].size) - return 1; - - return 0; -} - -/*******************************************************************************************************/ - -#define DSP_HPIC 0x0 -#define DSP_HPIA 0x4 -#define DSP_HPID1 0x8 -#define DSP_HPID2 0xC - -static u32 dummy_delay; -static volatile u32 *ti6711_delay = &dummy_delay; - -static inline void dsp_go_slow(void) -{ - volatile memctl8xx_t *memctl = &((immap_t *)CONFIG_SYS_IMMR)->im_memctl; -#if defined(CONFIG_NETTA_6412) - memctl->memc_or6 |= OR_SCY_15_CLK | OR_TRLX; -#else - memctl->memc_or2 |= OR_SCY_15_CLK | OR_TRLX; -#endif - memctl->memc_or5 |= OR_SCY_15_CLK | OR_TRLX; - - ti6711_delay = (u32 *)DUMMY_BASE; -} - -static inline void dsp_go_fast(void) -{ - volatile memctl8xx_t *memctl = &((immap_t *)CONFIG_SYS_IMMR)->im_memctl; -#if defined(CONFIG_NETTA_6412) - memctl->memc_or6 = (memctl->memc_or6 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK; -#else - memctl->memc_or2 = (memctl->memc_or2 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_3_CLK; -#endif - memctl->memc_or5 = (memctl->memc_or5 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK; - - ti6711_delay = &dummy_delay; -} - -/*******************************************************************************************************/ - -static inline void dsp_delay(void) -{ - /* perform ti6711_delay chip select read to have a small delay */ - (void) *(volatile u32 *)ti6711_delay; -} - -static inline u16 dsp_read_hpic(void) -{ -#if defined(CONFIG_NETTA_6412) - return bit_invert(*((volatile u16 *)DSP_BASE)); -#else - return *((volatile u16 *)DSP_BASE); -#endif -} - -static inline void dsp_write_hpic(u16 val) -{ -#if defined(CONFIG_NETTA_6412) - *((volatile u16 *)DSP_BASE) = bit_invert(val); -#else - *((volatile u16 *)DSP_BASE) = val; -#endif -} - -static inline void dsp_reset(void) -{ -#if defined(CONFIG_NETTA_6412) - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 15)); - udelay(500); - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat |= (1 << (15 - 15)); - udelay(500); -#else - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7)); - udelay(250); - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat |= (1 << (15 - 7)); - udelay(250); -#endif -} - -static inline u32 dsp_read_hpic_word(u32 addr) -{ - u32 val; - volatile u16 *p; -#if defined(CONFIG_NETTA_6412) - p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr); - - val = ((u32) bit_invert(p[0]) << 16); - /* dsp_delay(); */ - - val |= bit_invert(p[1]); - /* dsp_delay(); */ -#else - p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr); - - val = ((u32) p[0] << 16); - dsp_delay(); - - val |= p[1]; - dsp_delay(); -#endif - return val; -} - -static inline u16 dsp_read_hpic_hi_hword(u32 addr) -{ -#if defined(CONFIG_NETTA_6412) - return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr)); -#else - return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr); -#endif -} - -static inline u16 dsp_read_hpic_lo_hword(u32 addr) -{ -#if defined(CONFIG_NETTA_6412) - return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2)); -#else - return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2); -#endif -} - -static inline void dsp_wait_hrdy(void) -{ - int i; - - i = 0; -#if defined(CONFIG_NETTA_6412) - while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) { -#else - while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) { -#endif - dsp_delay(); - i++; - } -} - -static inline void dsp_write_hpic_word(u32 addr, u32 val) -{ - volatile u16 *p; -#if defined(CONFIG_NETTA_6412) - p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr); - p[0] = bit_invert((u16)(val >> 16)); - /* dsp_delay(); */ - - p[1] = bit_invert((u16)val); - /* dsp_delay(); */ -#else - p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr); - p[0] = (u16)(val >> 16); - dsp_delay(); - - p[1] = (u16)val; - dsp_delay(); -#endif -} - -static inline void dsp_write_hpic_hi_hword(u32 addr, u16 val_h) -{ -#if defined(CONFIG_NETTA_6412) - *(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = bit_invert(val_h); -#else - - *(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = val_h; -#endif -} - -static inline void dsp_write_hpic_lo_hword(u32 addr, u16 val_l) -{ -#if defined(CONFIG_NETTA_6412) - *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = bit_invert(val_l); -#else - *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = val_l; -#endif -} - -/********************************************************************/ - -static inline void c62_write_word(u32 addr, u32 val) -{ - dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16)); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - - dsp_wait_hrdy(); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - dsp_write_hpic_hi_hword(DSP_HPID2, (u16)(val >> 16)); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); - - /* dsp_wait_hrdy(); - dsp_delay(); */ -#endif - dsp_write_hpic_lo_hword(DSP_HPID2, (u16)val); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif -} - -static u32 c62_read_word(u32 addr) -{ - u32 val; - - dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16)); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - - /* FETCH */ -#if defined(CONFIG_NETTA_6412) - dsp_write_hpic_word(DSP_HPIC, 0x00100010); -#else - dsp_write_hpic(0x10); - dsp_delay(); -#endif - dsp_wait_hrdy(); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - val = (u32)dsp_read_hpic_hi_hword(DSP_HPID2) << 16; -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); - - /* dsp_wait_hrdy(); - dsp_delay(); */ -#endif - val |= dsp_read_hpic_lo_hword(DSP_HPID2); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - return val; -} - -static inline void c62_read(u32 addr, u32 *buffer, int numdata) -{ - int i; - - if (numdata <= 0) - return; - - for (i = 0; i < numdata; i++) { - *buffer++ = c62_read_word(addr); - addr += 4; - } -} - -static inline u32 c62_checksum(u32 addr, int numdata) -{ - int i; - u32 chksum; - - chksum = 0; - for (i = 0; i < numdata; i++) { - chksum += c62_read_word(addr); - addr += 4; - } - - return chksum; -} - -static inline void c62_write(u32 addr, const u32 *buffer, int numdata) -{ - int i; - - if (numdata <= 0) - return; - - for (i = 0; i < numdata; i++) { - c62_write_word(addr, *buffer++); - addr += 4; - } -} - -static inline int c62_write_word_validated(u32 addr, u32 val) -{ - c62_write_word(addr, val); - return c62_read_word(addr) == val ? 0 : -1; -} - -static inline int c62_write_validated(u32 addr, const u32 *buffer, int numdata) -{ - int i, r; - - if (numdata <= 0) - return 0; - - for (i = 0; i < numdata; i++) { - r = c62_write_word_validated(addr, *buffer++); - if (r < 0) - return r; - addr += 4; - } - return 0; -} - -#if defined(CONFIG_NETTA_6412) - -#define DRAM_REGS_BASE 0x1800000 - -#define GBLCTL DRAM_REGS_BASE -#define CECTL1 (DRAM_REGS_BASE + 0x4) -#define CECTL0 (DRAM_REGS_BASE + 0x8) -#define CECTL2 (DRAM_REGS_BASE + 0x10) -#define CECTL3 (DRAM_REGS_BASE + 0x14) -#define SDCTL (DRAM_REGS_BASE + 0x18) -#define SDTIM (DRAM_REGS_BASE + 0x1C) -#define SDEXT (DRAM_REGS_BASE + 0x20) -#define SESEC1 (DRAM_REGS_BASE + 0x44) -#define SESEC0 (DRAM_REGS_BASE + 0x48) -#define SESEC2 (DRAM_REGS_BASE + 0x50) -#define SESEC3 (DRAM_REGS_BASE + 0x54) - -#define MAR128 0x1848200 -#define MAR129 0x1848204 - -void dsp_dram_initialize(void) -{ - c62_write_word(GBLCTL, 0x120E4); - c62_write_word(CECTL1, 0x18); - c62_write_word(CECTL0, 0xD0); - c62_write_word(CECTL2, 0x18); - c62_write_word(CECTL3, 0x18); - c62_write_word(SDCTL, 0x47115000); - c62_write_word(SDTIM, 1536); - c62_write_word(SDEXT, 0x534A9); -#if 0 - c62_write_word(SESEC1, 0); - c62_write_word(SESEC0, 0); - c62_write_word(SESEC2, 0); - c62_write_word(SESEC3, 0); -#endif - c62_write_word(MAR128, 1); - c62_write_word(MAR129, 0); -} - -#endif - -static inline void dsp_init_hpic(void) -{ - int i; - volatile u16 *p; -#if defined(CONFIG_NETTA_6412) - dsp_go_fast(); -#else - dsp_go_slow(); -#endif - i = 0; -#if defined(CONFIG_NETTA_6412) - while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) { -#else - while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) { -#endif - dsp_delay(); - i++; - } - - if (i == 1000) - printf("HRDY stuck\n"); - - dsp_delay(); - - /* write control register */ - p = (volatile u16 *)DSP_BASE; - p[0] = 0x0000; - dsp_delay(); - p[1] = 0x0000; - dsp_delay(); - -#if !defined(CONFIG_NETTA_6412) - dsp_go_fast(); -#endif -} - -/***********************************************************************************************************/ - -#if !defined(CONFIG_NETTA_6412) - -static const u8 bootstrap_rbin[5084] = { - 0x52, 0x42, 0x49, 0x4e, 0xc5, 0xa9, 0x9f, 0x1a, 0x00, 0x00, 0x00, 0x02, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, - 0x00, 0x00, 0x11, 0xc0, 0x00, 0x17, 0x94, 0x2a, 0x00, 0x00, 0x00, 0x6a, - 0x00, 0x00, 0x03, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, - 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, - 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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0x32, 0x19, 0x30, 0x2a, 0x32, 0x00, 0x00, 0x6a, 0x30, 0x10, 0x02, 0xf4, - 0x30, 0x00, 0x09, 0x12, 0x00, 0x00, 0x80, 0x00, 0x02, 0x80, 0x00, 0xfa, - 0x02, 0x80, 0xc0, 0x6a, 0x03, 0x14, 0x02, 0xe6, 0x02, 0x00, 0x08, 0x2a, - 0x00, 0x00, 0x40, 0x00, 0x02, 0x18, 0x8d, 0xfa, 0x02, 0x14, 0x02, 0xf6, - 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0xc0, 0x68, 0x01, 0x80, 0x02, 0x64, - 0x00, 0x00, 0x60, 0x00, 0x01, 0x8d, 0x0d, 0xd8, 0x01, 0x80, 0x02, 0x74, - 0x0f, 0xff, 0xf9, 0x90, 0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62, - 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; - -static int load_bootstrap(void) -{ - const u8 *s = bootstrap_rbin; - u32 l = sizeof(bootstrap_rbin); - const u8 *data, *hdr, *h; - u32 chksum, chksum2; - int i, j, rangenr; - u32 start, length; - - if (l < 12) { - printf("bootstrap image corrupted. (too short header)\n"); - return -1; - } - - chksum = ((u32)s[4] << 24) | ((u32)s[5] << 16) | ((u32)s[ 6] << 8) | (u32)s[ 7]; - rangenr = ((u32)s[8] << 24) | ((u32)s[9] << 16) | ((u32)s[10] << 8) | (u32)s[11]; - s += 12; l -= 12; - - hdr = s; - s += 8 * rangenr; l -= 8 * rangenr; - data = s; - - /* validate bootstrap image */ - h = hdr; s = data; chksum2 = 0; - for (i = 0; i < rangenr; i++) { - start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3]; - length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7]; - h += 8; - - /* too short */ - if (l < length) { - printf("bootstrap image corrupted. (too short data)\n"); - return -1; - } - l -= length; - - j = (int)length / 4; - while (j-- > 0) { - chksum2 += ((u32)s[0] << 24) | ((u32)s[1] << 16) | ((u32)s[2] << 8) | (u32)s[3]; - s += 4; - } - } - - /* checksum must match */ - if (chksum != chksum2) { - printf("bootstrap image corrupted. (checksum error)\n"); - return -1; - } - - /* nothing must be left */ - if (l != 0) { - printf("bootstrap image corrupted. (garbage at the end)\n"); - return -1; - } - - /* write the image */ - h = hdr; - s = data; - for (i = 0; i < rangenr; i++) { - start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3]; - length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7]; - h += 8; - c62_write(start, (u32 *)s, length / 4); - s += length; - } - - /* and now validate checksum */ - h = hdr; - s = data; - chksum2 = 0; - for (i = 0; i < rangenr; i++) { - start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3]; - length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7]; - h += 8; - chksum2 += c62_checksum(start, length / 4); - s += length; - } - - /* checksum must match */ - if (chksum != chksum2) { - printf("bootstrap in DSP memory is corrupted\n"); - return -1; - } - - return 0; -} - -struct host_init { - u32 master_mode; - struct { - u8 port_id; - u8 slot_id; - } ch_serial_map[32]; - u32 clk_divider[2]; - /* pll */ - u32 initmode; - u32 pllm; - u32 div[4]; - u32 oscdiv1; - u32 unused[10]; -}; - -const struct host_init hi_default = { - .master_mode = -#if !defined(CONFIG_NETTA_ISDN) - -1, -#else - 0, -#endif - - .ch_serial_map = { - [ 0] = { .port_id = 2, .slot_id = 16 }, - [ 1] = { .port_id = 2, .slot_id = 17 }, - [ 2] = { .port_id = 2, .slot_id = 18 }, - [ 3] = { .port_id = 2, .slot_id = 19 }, - [ 4] = { .port_id = 2, .slot_id = 20 }, - [ 5] = { .port_id = 2, .slot_id = 21 }, - [ 6] = { .port_id = 2, .slot_id = 22 }, - [ 7] = { .port_id = 2, .slot_id = 23 }, - [ 8] = { .port_id = 2, .slot_id = 24 }, - [ 9] = { .port_id = 2, .slot_id = 25 }, - [10] = { .port_id = 2, .slot_id = 26 }, - [11] = { .port_id = 2, .slot_id = 27 }, - [12] = { .port_id = 2, .slot_id = 28 }, - [13] = { .port_id = 2, .slot_id = 29 }, - [14] = { .port_id = 2, .slot_id = 30 }, - [15] = { .port_id = 2, .slot_id = 31 }, - }, - - /* - dsp_clk(xin, pllm) = xin * pllm - serial_clk(xin, pllm, div) = (dsp_clk(xin, pllm) / 2) / (div + 1) - */ - - .clk_divider = { - [0] = 47, /* must be 2048Hz */ - [1] = 47, - }, - - .initmode = 1, - .pllm = -#if !defined(CONFIG_NETTA_ISDN) - 8, /* for =~ 25MHz 8 */ -#else - 4, -#endif - .div = { - [0] = 0x8000, - [1] = 0x8000, /* for =~ 25MHz 0x8000 */ - [2] = 0x8001, /* for =~ 25MHz 0x8001 */ - [3] = 0x8001, /* for =~ 25MHz 0x8001 */ - }, - - .oscdiv1 = 0, -}; - -static void hi_write(const struct host_init *hi) -{ - u32 hi_buf[1 + sizeof(*hi) / sizeof(u32)]; - u32 *s; - u32 chksum; - int i; - - memset(hi_buf, 0, sizeof(hi_buf)); - - s = hi_buf; - s++; - *s++ = hi->master_mode; - for (i = 0; i < (sizeof(hi->ch_serial_map) / sizeof(hi->ch_serial_map[0])) / 2; i++) - *s++ = ((u32)hi->ch_serial_map[i * 2 + 1].slot_id << 24) | ((u32)hi->ch_serial_map[i * 2 + 1].port_id << 16) | - ((u32)hi->ch_serial_map[i * 2 + 0].slot_id << 8) | (u32)hi->ch_serial_map[i * 2 + 0].port_id; - - for (i = 0; i < sizeof(hi->clk_divider)/sizeof(hi->clk_divider[0]); i++) - *s++ = hi->clk_divider[i]; - - *s++ = hi->initmode; - *s++ = hi->pllm; - for (i = 0; i < sizeof(hi->div)/sizeof(hi->div[0]); i++) - *s++ = hi->div[i]; - *s++ = hi->oscdiv1; - - chksum = 0; - for (i = 1; i < sizeof(hi_buf)/sizeof(hi_buf[0]); i++) - chksum += hi_buf[i]; - hi_buf[0] = -chksum; - - c62_write(0x1000, hi_buf, sizeof(hi_buf) / sizeof(hi_buf[0])); -} - -static void run_bootstrap(void) -{ - dsp_go_slow(); - - hi_write(&hi_default); - - /* signal interrupt */ - dsp_write_hpic(0x0002); - dsp_delay(); - - dsp_go_fast(); -} - -#endif - -/***********************************************************************************************************/ - -int board_post_dsp(int flags) -{ - u32 ramS, ramE; - u32 data, data2; - int i, j, k; -#if !defined(CONFIG_NETTA_6412) - int r; -#endif - dsp_reset(); - dsp_init_hpic(); -#if !defined(CONFIG_NETTA_6412) - dsp_go_slow(); -#endif - data = 0x11223344; - dsp_write_hpic_word(DSP_HPIA, data); - data2 = dsp_read_hpic_word(DSP_HPIA); - if (data2 != 0x11223344) { - printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2); - goto err; - } - - data = 0xFFEEDDCC; - dsp_write_hpic_word(DSP_HPIA, data); - data2 = dsp_read_hpic_word(DSP_HPIA); - if (data2 != 0xFFEEDDCC) { - printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2); - goto err; - } -#if defined(CONFIG_NETTA_6412) - dsp_dram_initialize(); -#else - r = load_bootstrap(); - if (r < 0) { - printf("BOOTSTRAP: ** ERROR ** failed to load\n"); - goto err; - } - - run_bootstrap(); - - dsp_go_fast(); -#endif - printf(" "); - - /* test RAMs */ - for (k = 0; k < sizeof(ranges)/sizeof(ranges[0]); k++) { - - ramS = ranges[k].start; - ramE = ranges[k].start + ranges[k].size; - - for (j = 0; j < 3; j++) { - - printf("\b\b\b\bR%d.%d", k, j); - - for (i = ramS; i < ramE; i += 4) { - - data = 0; - switch (j) { - case 0: data = 0xAA55AA55; break; - case 1: data = 0x55AA55AA; break; - case 2: data = (u32)i; break; - } - - c62_write_word(i, data); - data2 = c62_read_word(i); - if (data != data2) { - printf(" ** ERROR at 0x%08X; wrote 0x%08X read 0x%08X **\n", i, data, data2); - goto err; - } - } - } - } - - printf("\b\b\b\b \b\b\b\bOK\n"); -#if !defined(CONFIG_NETTA_6412) - /* XXX assume that this works */ - load_bootstrap(); - run_bootstrap(); - dsp_go_fast(); -#endif - return 0; - -err: - return -1; -} - -int board_dsp_reset(void) -{ -#if !defined(CONFIG_NETTA_6412) - int r; -#endif - dsp_reset(); - dsp_init_hpic(); -#if defined(CONFIG_NETTA_6412) - dsp_dram_initialize(); -#else - dsp_go_slow(); - r = load_bootstrap(); - if (r < 0) - return r; - - run_bootstrap(); - dsp_go_fast(); -#endif - return 0; -} diff --git a/board/netta/flash.c b/board/netta/flash.c deleted file mode 100644 index d6902a6938..0000000000 --- a/board/netta/flash.c +++ /dev/null @@ -1,492 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_byte(flash_info_t * info, ulong dest, uchar data); -static void flash_get_offsets(ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); - -#ifdef CONFIG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - - flash_info[0].size = size; - - return (size); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_MX: - printf("MXIC "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29LV040B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - short i; - uchar mid; - uchar pid; - vu_char *caddr = (vu_char *) addr; - ulong base = (ulong) addr; - - - /* Write auto select command: read Manufacturer ID */ - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0x90; - - mid = caddr[0]; - switch (mid) { - case (AMD_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_FUJ; - break; - case (MX_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_MX; - break; - case (STM_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - pid = caddr[1]; /* device ID */ - switch (pid) { - case (AMD_ID_LV400T & 0xFF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV400B & 0xFF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV800T & 0xFF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800B & 0xFF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV160T & 0xFF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160B & 0xFF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - - case (STM_ID_M29W040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & 0xFF): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV320B & 0xFF): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - printf(" "); - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection: D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (vu_char *) info->start[0]; - - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0xF0; - - udelay(20000); - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - vu_char *addr = (vu_char *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_char *) (info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = start; - addr = (vu_char *) (info->start[l_sect]); - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (vu_char *) info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - int rc; - - while (cnt > 0) { - if ((rc = write_byte(info, addr++, *src++)) != 0) { - return (rc); - } - --cnt; - } - - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_byte(flash_info_t * info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *) (info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *) dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *((vu_char *) dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/netta/netta.c b/board/netta/netta.c deleted file mode 100644 index 2c9c6bf6bc..0000000000 --- a/board/netta/netta.c +++ /dev/null @@ -1,558 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * U-Boot port on NetTA4 board - */ - -#include <common.h> -#include <miiphy.h> - -#include "mpc8xx.h" - -#ifdef CONFIG_HW_WATCHDOG -#include <watchdog.h> -#endif - -int fec8xx_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -int fec8xx_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value); - -/****************************************************************/ - -/* some sane bit macros */ -#define _BD(_b) (1U << (31-(_b))) -#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) - -#define _BW(_b) (1U << (15-(_b))) -#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) - -#define _BB(_b) (1U << (7-(_b))) -#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) - -#define _B(_b) _BD(_b) -#define _BR(_l, _h) _BDR(_l, _h) - -/****************************************************************/ - -/* - * Check Board Identity: - * - * Return 1 always. - */ - -int checkboard(void) -{ - printf ("Intracom NETTA" -#if defined(CONFIG_NETTA_ISDN) - " with ISDN support" -#endif -#if defined(CONFIG_NETTA_6412) - " (DSP:TI6412)" -#else - " (DSP:TI6711)" -#endif - "\n" - ); - return (0); -} - -/****************************************************************/ - -#define _NOT_USED_ 0xFFFFFFFF - -/****************************************************************/ - -#define CS_0000 0x00000000 -#define CS_0001 0x10000000 -#define CS_0010 0x20000000 -#define CS_0011 0x30000000 -#define CS_0100 0x40000000 -#define CS_0101 0x50000000 -#define CS_0110 0x60000000 -#define CS_0111 0x70000000 -#define CS_1000 0x80000000 -#define CS_1001 0x90000000 -#define CS_1010 0xA0000000 -#define CS_1011 0xB0000000 -#define CS_1100 0xC0000000 -#define CS_1101 0xD0000000 -#define CS_1110 0xE0000000 -#define CS_1111 0xF0000000 - -#define BS_0000 0x00000000 -#define BS_0001 0x01000000 -#define BS_0010 0x02000000 -#define BS_0011 0x03000000 -#define BS_0100 0x04000000 -#define BS_0101 0x05000000 -#define BS_0110 0x06000000 -#define BS_0111 0x07000000 -#define BS_1000 0x08000000 -#define BS_1001 0x09000000 -#define BS_1010 0x0A000000 -#define BS_1011 0x0B000000 -#define BS_1100 0x0C000000 -#define BS_1101 0x0D000000 -#define BS_1110 0x0E000000 -#define BS_1111 0x0F000000 - -#define A10_AAAA 0x00000000 -#define A10_AAA0 0x00200000 -#define A10_AAA1 0x00300000 -#define A10_000A 0x00800000 -#define A10_0000 0x00A00000 -#define A10_0001 0x00B00000 -#define A10_111A 0x00C00000 -#define A10_1110 0x00E00000 -#define A10_1111 0x00F00000 - -#define RAS_0000 0x00000000 -#define RAS_0001 0x00040000 -#define RAS_1110 0x00080000 -#define RAS_1111 0x000C0000 - -#define CAS_0000 0x00000000 -#define CAS_0001 0x00010000 -#define CAS_1110 0x00020000 -#define CAS_1111 0x00030000 - -#define WE_0000 0x00000000 -#define WE_0001 0x00004000 -#define WE_1110 0x00008000 -#define WE_1111 0x0000C000 - -#define GPL4_0000 0x00000000 -#define GPL4_0001 0x00001000 -#define GPL4_1110 0x00002000 -#define GPL4_1111 0x00003000 - -#define GPL5_0000 0x00000000 -#define GPL5_0001 0x00000400 -#define GPL5_1110 0x00000800 -#define GPL5_1111 0x00000C00 -#define LOOP 0x00000080 - -#define EXEN 0x00000040 - -#define AMX_COL 0x00000000 -#define AMX_ROW 0x00000020 -#define AMX_MAR 0x00000030 - -#define NA 0x00000008 - -#define UTA 0x00000004 - -#define TODT 0x00000002 - -#define LAST 0x00000001 - -/* #define CAS_LATENCY 3 */ -#define CAS_LATENCY 2 - -const uint sdram_table[0x40] = { - -#if CAS_LATENCY == 3 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, -#endif - -#if CAS_LATENCY == 2 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - -#endif - - /* UPT */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, - CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, -}; - -/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ -/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ -#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) - -/* 8 */ -#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -void check_ram(unsigned int addr, unsigned int size) -{ - unsigned int i, j, v, vv; - volatile unsigned int *p; - unsigned int pv; - - p = (unsigned int *)addr; - pv = (unsigned int)p; - for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) - *p++ = pv; - - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - v = (unsigned int)p; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - p++; - } - - for (j = 0; j < 5; j++) { - switch (j) { - case 0: v = 0x00000000; break; - case 1: v = 0xffffffff; break; - case 2: v = 0x55555555; break; - case 3: v = 0xaaaaaaaa; break; - default:v = 0xdeadbeef; break; - } - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - *p = v; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - *p = ~v; - p++; - } - } -} - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size; - - upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint)); - - /* - * Preliminary prescaler for refresh - */ - memctl->memc_mptpr = MPTPR_PTP_DIV8; - - memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - - memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */ - - udelay(200); - - /* perform SDRAM initialisation sequence */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ - udelay(1); - - memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */ - - udelay(10000); - - { - u32 d1, d2; - - d1 = 0xAA55AA55; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - hang(); - } - - d1 = 0x55AA55AA; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - hang(); - } - } - - size = get_ram_size((long *)0, SDRAM_MAX_SIZE); - -#if 0 - printf("check 0\n"); - check_ram(( 0 << 20), (2 << 20)); - printf("check 16\n"); - check_ram((16 << 20), (2 << 20)); - printf("check 32\n"); - check_ram((32 << 20), (2 << 20)); - printf("check 48\n"); - check_ram((48 << 20), (2 << 20)); -#endif - - if (size == 0) { - printf("SIZE is zero: LOOP on 0\n"); - for (;;) { - *(volatile u32 *)0 = 0; - (void)*(volatile u32 *)0; - } - } - - return size; -} - -/* ------------------------------------------------------------------------- */ - -int misc_init_r(void) -{ - return(0); -} - -void reset_phys(void) -{ - int phyno; - unsigned short v; - - /* reset the damn phys */ - mii_init(); - - for (phyno = 0; phyno < 32; ++phyno) { - fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v); - if (v == 0xFFFF) - continue; - fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN); - udelay(10000); - fec8xx_miiphy_write(NULL, phyno, MII_BMCR, - BMCR_RESET | BMCR_ANENABLE); - udelay(10000); - } -} - -extern int board_dsp_reset(void); - -int last_stage_init(void) -{ - int r; - - reset_phys(); - r = board_dsp_reset(); - if (r < 0) - printf("*** WARNING *** DSP reset failed (run diagnostics)\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* GP = general purpose, SP = special purpose (on chip peripheral) */ - -/* bits that can have a special purpose or can be configured as inputs/outputs */ -#define PA_GP_INMASK (_BWR(3) | _BWR(7, 9) | _BW(11)) -#define PA_GP_OUTMASK (_BW(6) | _BW(10) | _BWR(12, 15)) -#define PA_SP_MASK (_BWR(0, 2) | _BWR(4, 5)) -#define PA_ODR_VAL 0 -#define PA_GP_OUTVAL (_BW(13) | _BWR(14, 15)) -#define PA_SP_DIRVAL 0 - -#define PB_GP_INMASK (_B(28) | _B(31)) -#define PB_GP_OUTMASK (_BR(15, 19) | _BR(26, 27) | _BR(29, 30)) -#define PB_SP_MASK (_BR(22, 25)) -#define PB_ODR_VAL 0 -#define PB_GP_OUTVAL (_BR(15, 19) | _BR(26, 27) | _BR(29, 31)) -#define PB_SP_DIRVAL 0 - -#define PC_GP_INMASK (_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15)) -#define PC_GP_OUTMASK (_BW(6) | _BW(12)) -#define PC_SP_MASK (_BW(4) | _BW(8)) -#define PC_SOVAL 0 -#define PC_INTVAL _BW(7) -#define PC_GP_OUTVAL (_BW(6) | _BW(12)) -#define PC_SP_DIRVAL 0 - -#define PD_GP_INMASK 0 -#define PD_GP_OUTMASK _BWR(3, 15) -#define PD_SP_MASK 0 - -#if defined(CONFIG_NETTA_6412) - -#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11) | _BW(15)) - -#else - -#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11)) - -#endif - -#define PD_SP_DIRVAL 0 - -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile iop8xx_t *ioport = &immap->im_ioport; - volatile cpm8xx_t *cpm = &immap->im_cpm; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* CS1: NAND chip select */ - memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ; - memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); -#if !defined(CONFIG_NETTA_6412) - /* CS2: DSP */ - memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2); - memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); -#else - /* CS6: DSP */ - memctl->memc_or6 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2); - memctl->memc_br6 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); -#endif - /* CS4: External register chip select */ - memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK); - memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V); - - /* CS5: dummy for accurate delay */ - memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DUMMY_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_0_CLK | OR_ACS_DIV2); - memctl->memc_br5 = ((DUMMY_BASE & BR_BA_MSK) | BR_PS_32 | BR_V); - - ioport->iop_padat = PA_GP_OUTVAL; - ioport->iop_paodr = PA_ODR_VAL; - ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; - ioport->iop_papar = PA_SP_MASK; - - cpm->cp_pbdat = PB_GP_OUTVAL; - cpm->cp_pbodr = PB_ODR_VAL; - cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; - cpm->cp_pbpar = PB_SP_MASK; - - ioport->iop_pcdat = PC_GP_OUTVAL; - ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; - ioport->iop_pcso = PC_SOVAL; - ioport->iop_pcint = PC_INTVAL; - ioport->iop_pcpar = PC_SP_MASK; - - ioport->iop_pddat = PD_GP_OUTVAL; - ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL; - ioport->iop_pdpar = PD_SP_MASK; - - /* ioport->iop_pddat |= (1 << (15 - 6)) | (1 << (15 - 7)); */ - - return 0; -} - -#if defined(CONFIG_CMD_PCMCIA) - -int pcmcia_init(void) -{ - return 0; -} - -#endif - -#ifdef CONFIG_HW_WATCHDOG - -void hw_watchdog_reset(void) -{ - /* XXX add here the really funky stuff */ -} - -#endif diff --git a/board/netta/pcmcia.c b/board/netta/pcmcia.c deleted file mode 100644 index 3fa1925f4c..0000000000 --- a/board/netta/pcmcia.c +++ /dev/null @@ -1,346 +0,0 @@ -#include <common.h> -#include <mpc8xx.h> -#include <pcmcia.h> - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#ifdef CONFIG_PCMCIA - -/* some sane bit macros */ -#define _BD(_b) (1U << (31-(_b))) -#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) - -#define _BW(_b) (1U << (15-(_b))) -#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) - -#define _BB(_b) (1U << (7-(_b))) -#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) - -#define _B(_b) _BD(_b) -#define _BR(_l, _h) _BDR(_l, _h) - -#define PCMCIA_BOARD_MSG "NETTA" - -static const unsigned short vppd_masks[2] = { _BW(14), _BW(15) }; - -static void cfg_vppd(int no) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - unsigned short mask; - - if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0])) - return; - - mask = vppd_masks[no]; - - immap->im_ioport.iop_papar &= ~mask; - immap->im_ioport.iop_paodr &= ~mask; - immap->im_ioport.iop_padir |= mask; -} - -static void set_vppd(int no, int what) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - unsigned short mask; - - if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0])) - return; - - mask = vppd_masks[no]; - - if (what) - immap->im_ioport.iop_padat |= mask; - else - immap->im_ioport.iop_padat &= ~mask; -} - -static const unsigned short vccd_masks[2] = { _BW(10), _BW(6) }; - -static void cfg_vccd(int no) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - unsigned short mask; - - if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0])) - return; - - mask = vccd_masks[no]; - - immap->im_ioport.iop_papar &= ~mask; - immap->im_ioport.iop_paodr &= ~mask; - immap->im_ioport.iop_padir |= mask; -} - -static void set_vccd(int no, int what) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - unsigned short mask; - - if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0])) - return; - - mask = vccd_masks[no]; - - if (what) - immap->im_ioport.iop_padat |= mask; - else - immap->im_ioport.iop_padat &= ~mask; -} - -static const unsigned short oc_mask = _BW(8); - -static void cfg_oc(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - unsigned short mask = oc_mask; - - immap->im_ioport.iop_pcdir &= ~mask; - immap->im_ioport.iop_pcso &= ~mask; - immap->im_ioport.iop_pcint &= ~mask; - immap->im_ioport.iop_pcpar &= ~mask; -} - -static int get_oc(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - unsigned short mask = oc_mask; - int what; - - what = !!(immap->im_ioport.iop_pcdat & mask);; - return what; -} - -static const unsigned short shdn_mask = _BW(12); - -static void cfg_shdn(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - unsigned short mask; - - mask = shdn_mask; - - immap->im_ioport.iop_papar &= ~mask; - immap->im_ioport.iop_paodr &= ~mask; - immap->im_ioport.iop_padir |= mask; -} - -static void set_shdn(int what) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - unsigned short mask; - - mask = shdn_mask; - - if (what) - immap->im_ioport.iop_padat |= mask; - else - immap->im_ioport.iop_padat &= ~mask; -} - -static void cfg_ports (void) -{ - cfg_vppd(0); cfg_vppd(1); /* VPPD0,VPPD1 VAVPP => Hi-Z */ - cfg_vccd(0); cfg_vccd(1); /* 3V and 5V off */ - cfg_shdn(); - cfg_oc(); - - /* - * Configure Port A for TPS2211 PC-Card Power-Interface Switch - * - * Switch off all voltages, assert shutdown - */ - set_vppd(0, 1); set_vppd(1, 1); - set_vccd(0, 0); set_vccd(1, 0); - set_shdn(1); - - udelay(100000); -} - -int pcmcia_hardware_enable(int slot) -{ - volatile pcmconf8xx_t *pcmp; - uint reg, pipr, mask; - int i; - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - udelay(10000); - - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - - /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ - cfg_ports (); - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); - pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(500); - - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z - */ - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - pipr = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - pipr, - (reg&PCMCIA_VS1(slot))?"n":"ff", - (reg&PCMCIA_VS2(slot))?"n":"ff"); - - if ((pipr & mask) == mask) { - set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */ - set_vccd(0, 0); set_vccd(1, 1); /* 5V on, 3V off */ - puts (" 5.0V card found: "); - } else { - set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */ - set_vccd(0, 1); set_vccd(1, 0); /* 5V off, 3V on */ - puts (" 3.3V card found: "); - } - - /* Wait 500 ms; use this to check for over-current */ - for (i=0; i<5000; ++i) { - if (!get_oc()) { - printf (" *** Overcurrent - Safety shutdown ***\n"); - set_vccd(0, 0); set_vccd(1, 0); /* VAVPP => Hi-Z */ - return (1); - } - udelay (100); - } - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); -} - - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_hardware_disable(int slot) -{ - u_long reg; - - debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - /* Configure PCMCIA General Control Register */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - /* All voltages off / Hi-Z */ - set_vppd(0, 1); set_vppd(1, 1); - set_vccd(0, 1); set_vccd(1, 1); - - udelay(10000); - - return (0); -} -#endif - - -int pcmcia_voltage_set(int slot, int vcc, int vpp) -{ - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("voltage_set: " - PCMCIA_BOARD_MSG - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Configure Port C pins for - * 5 Volts Enable and 3 Volts enable, - * Turn all power pins to Hi-Z - */ - debug ("PCMCIA power OFF\n"); - cfg_ports (); /* Enables switch, but all in Hi-Z */ - - set_vppd(0, 1); set_vppd(1, 1); - - switch(vcc) { - case 0: - break; /* Switch off */ - - case 33: - set_vccd(0, 1); set_vccd(1, 0); - break; - - case 50: - set_vccd(0, 0); set_vccd(1, 1); - break; - - default: - goto done; - } - - /* Checking supported voltages */ - - debug ("PIPR: 0x%x --> %s\n", - pcmp->pcmc_pipr, - (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); - -done: - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", - slot+'A'); - return (0); -} - -#endif /* CONFIG_PCMCIA */ diff --git a/board/netta/u-boot.lds b/board/netta/u-boot.lds deleted file mode 100644 index 0dff5a4023..0000000000 --- a/board/netta/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/netta/u-boot.lds.debug b/board/netta/u-boot.lds.debug deleted file mode 100644 index a198cf9520..0000000000 --- a/board/netta/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/netta2/Makefile b/board/netta2/Makefile deleted file mode 100644 index c3bfb0d305..0000000000 --- a/board/netta2/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = netta2.o flash.o diff --git a/board/netta2/flash.c b/board/netta2/flash.c deleted file mode 100644 index 133f36d98c..0000000000 --- a/board/netta2/flash.c +++ /dev/null @@ -1,490 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_byte(flash_info_t * info, ulong dest, uchar data); -static void flash_get_offsets(ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size, size << 20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); - -#ifdef CONFIG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - flash_info[0].size = size; - - return (size); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_MX: - printf("MXIC "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29LV040B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - short i; - uchar mid; - uchar pid; - vu_char *caddr = (vu_char *) addr; - ulong base = (ulong) addr; - - /* Write auto select command: read Manufacturer ID */ - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0x90; - - mid = caddr[0]; - switch (mid) { - case (AMD_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_FUJ; - break; - case (MX_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_MX; - break; - case (STM_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - pid = caddr[1]; /* device ID */ - switch (pid) { - case (AMD_ID_LV400T & 0xFF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV400B & 0xFF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV800T & 0xFF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800B & 0xFF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV160T & 0xFF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160B & 0xFF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - - case (STM_ID_M29W040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & 0xFF): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV320B & 0xFF): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - printf(" "); - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection: D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (vu_char *) info->start[0]; - - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0xF0; - - udelay(20000); - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - vu_char *addr = (vu_char *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_char *) (info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = start; - addr = (vu_char *) (info->start[l_sect]); - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_char *) info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - int rc; - - while (cnt > 0) { - if ((rc = write_byte(info, addr++, *src++)) != 0) { - return (rc); - } - --cnt; - } - - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_byte(flash_info_t * info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *) (info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *) dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *((vu_char *) dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c deleted file mode 100644 index 008ae67aec..0000000000 --- a/board/netta2/netta2.c +++ /dev/null @@ -1,624 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * U-Boot port on NetTA4 board - */ - -#include <common.h> -#include <miiphy.h> - -#include "mpc8xx.h" - -#ifdef CONFIG_HW_WATCHDOG -#include <watchdog.h> -#endif - -int fec8xx_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -int fec8xx_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value); - -/****************************************************************/ - -/* some sane bit macros */ -#define _BD(_b) (1U << (31-(_b))) -#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) - -#define _BW(_b) (1U << (15-(_b))) -#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) - -#define _BB(_b) (1U << (7-(_b))) -#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) - -#define _B(_b) _BD(_b) -#define _BR(_l, _h) _BDR(_l, _h) - -/****************************************************************/ - -/* - * Check Board Identity: - * - * Return 1 always. - */ - -int checkboard(void) -{ - printf ("Intracom NetTA2 V%d\n", CONFIG_NETTA2_VERSION); - return (0); -} - -/****************************************************************/ - -#define _NOT_USED_ 0xFFFFFFFF - -/****************************************************************/ - -#define CS_0000 0x00000000 -#define CS_0001 0x10000000 -#define CS_0010 0x20000000 -#define CS_0011 0x30000000 -#define CS_0100 0x40000000 -#define CS_0101 0x50000000 -#define CS_0110 0x60000000 -#define CS_0111 0x70000000 -#define CS_1000 0x80000000 -#define CS_1001 0x90000000 -#define CS_1010 0xA0000000 -#define CS_1011 0xB0000000 -#define CS_1100 0xC0000000 -#define CS_1101 0xD0000000 -#define CS_1110 0xE0000000 -#define CS_1111 0xF0000000 - -#define BS_0000 0x00000000 -#define BS_0001 0x01000000 -#define BS_0010 0x02000000 -#define BS_0011 0x03000000 -#define BS_0100 0x04000000 -#define BS_0101 0x05000000 -#define BS_0110 0x06000000 -#define BS_0111 0x07000000 -#define BS_1000 0x08000000 -#define BS_1001 0x09000000 -#define BS_1010 0x0A000000 -#define BS_1011 0x0B000000 -#define BS_1100 0x0C000000 -#define BS_1101 0x0D000000 -#define BS_1110 0x0E000000 -#define BS_1111 0x0F000000 - -#define GPL0_AAAA 0x00000000 -#define GPL0_AAA0 0x00200000 -#define GPL0_AAA1 0x00300000 -#define GPL0_000A 0x00800000 -#define GPL0_0000 0x00A00000 -#define GPL0_0001 0x00B00000 -#define GPL0_111A 0x00C00000 -#define GPL0_1110 0x00E00000 -#define GPL0_1111 0x00F00000 - -#define GPL1_0000 0x00000000 -#define GPL1_0001 0x00040000 -#define GPL1_1110 0x00080000 -#define GPL1_1111 0x000C0000 - -#define GPL2_0000 0x00000000 -#define GPL2_0001 0x00010000 -#define GPL2_1110 0x00020000 -#define GPL2_1111 0x00030000 - -#define GPL3_0000 0x00000000 -#define GPL3_0001 0x00004000 -#define GPL3_1110 0x00008000 -#define GPL3_1111 0x0000C000 - -#define GPL4_0000 0x00000000 -#define GPL4_0001 0x00001000 -#define GPL4_1110 0x00002000 -#define GPL4_1111 0x00003000 - -#define GPL5_0000 0x00000000 -#define GPL5_0001 0x00000400 -#define GPL5_1110 0x00000800 -#define GPL5_1111 0x00000C00 -#define LOOP 0x00000080 - -#define EXEN 0x00000040 - -#define AMX_COL 0x00000000 -#define AMX_ROW 0x00000020 -#define AMX_MAR 0x00000030 - -#define NA 0x00000008 - -#define UTA 0x00000004 - -#define TODT 0x00000002 - -#define LAST 0x00000001 - -#define A10_AAAA GPL0_AAAA -#define A10_AAA0 GPL0_AAA0 -#define A10_AAA1 GPL0_AAA1 -#define A10_000A GPL0_000A -#define A10_0000 GPL0_0000 -#define A10_0001 GPL0_0001 -#define A10_111A GPL0_111A -#define A10_1110 GPL0_1110 -#define A10_1111 GPL0_1111 - -#define RAS_0000 GPL1_0000 -#define RAS_0001 GPL1_0001 -#define RAS_1110 GPL1_1110 -#define RAS_1111 GPL1_1111 - -#define CAS_0000 GPL2_0000 -#define CAS_0001 GPL2_0001 -#define CAS_1110 GPL2_1110 -#define CAS_1111 GPL2_1111 - -#define WE_0000 GPL3_0000 -#define WE_0001 GPL3_0001 -#define WE_1110 GPL3_1110 -#define WE_1111 GPL3_1111 - -/* #define CAS_LATENCY 3 */ -#define CAS_LATENCY 2 - -const uint sdram_table[0x40] = { - -#if CAS_LATENCY == 3 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, -#endif - -#if CAS_LATENCY == 2 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - -#endif - - /* UPT */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, - CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, -}; - -#if CONFIG_NETTA2_VERSION == 2 -static const uint nandcs_table[0x40] = { - /* RSS */ - CS_1000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0000 | GPL4_1110 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111, - CS_0000 | GPL4_0001 | GPL5_1111 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */ - - /* RBS */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_1000 | GPL4_1111 | GPL5_1110 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0001 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111, - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, - - /* WBS */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* UPT */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 , - CS_0001 | LAST, -}; -#endif - -/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ -/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ -#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) - -/* 8 */ -#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -void check_ram(unsigned int addr, unsigned int size) -{ - unsigned int i, j, v, vv; - volatile unsigned int *p; - unsigned int pv; - - p = (unsigned int *)addr; - pv = (unsigned int)p; - for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) - *p++ = pv; - - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - v = (unsigned int)p; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - p++; - } - - for (j = 0; j < 5; j++) { - switch (j) { - case 0: v = 0x00000000; break; - case 1: v = 0xffffffff; break; - case 2: v = 0x55555555; break; - case 3: v = 0xaaaaaaaa; break; - default:v = 0xdeadbeef; break; - } - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - *p = v; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - *p = ~v; - p++; - } - } -} - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size; - - upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0])); - - /* - * Preliminary prescaler for refresh - */ - memctl->memc_mptpr = MPTPR_PTP_DIV8; - - memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - - memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */ - - udelay(200); - - /* perform SDRAM initialisation sequence */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ - udelay(1); - - memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */ - - udelay(10000); - - { - u32 d1, d2; - - d1 = 0xAA55AA55; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - hang(); - } - - d1 = 0x55AA55AA; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - hang(); - } - } - - size = get_ram_size((long *)0, SDRAM_MAX_SIZE); - - if (size == 0) { - printf("SIZE is zero: LOOP on 0\n"); - for (;;) { - *(volatile u32 *)0 = 0; - (void)*(volatile u32 *)0; - } - } - - return size; -} - -/* ------------------------------------------------------------------------- */ - -void reset_phys(void) -{ - int phyno; - unsigned short v; - - udelay(10000); - /* reset the damn phys */ - mii_init(); - - for (phyno = 0; phyno < 32; ++phyno) { - fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v); - if (v == 0xFFFF) - continue; - fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN); - udelay(10000); - fec8xx_miiphy_write(NULL, phyno, MII_BMCR, - BMCR_RESET | BMCR_ANENABLE); - udelay(10000); - } -} - -/* ------------------------------------------------------------------------- */ - -/* GP = general purpose, SP = special purpose (on chip peripheral) */ - -/* bits that can have a special purpose or can be configured as inputs/outputs */ -#define PA_GP_INMASK 0 -#define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15)) -#define PA_SP_MASK 0 -#define PA_ODR_VAL 0 -#define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15)) -#define PA_SP_DIRVAL 0 - -#define PB_GP_INMASK _B(28) -#define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30)) -#define PB_SP_MASK (_BR(22, 25)) -#define PB_ODR_VAL 0 -#define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30)) -#define PB_SP_DIRVAL 0 - -#if CONFIG_NETTA2_VERSION == 1 -#define PC_GP_INMASK _BW(12) -#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15)) -#elif CONFIG_NETTA2_VERSION == 2 -#define PC_GP_INMASK (_BW(13) | _BW(15)) -#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(12)) -#endif -#define PC_SP_MASK 0 -#define PC_SOVAL 0 -#define PC_INTVAL 0 -#define PC_GP_OUTVAL (_BW(10) | _BW(11)) -#define PC_SP_DIRVAL 0 - -#if CONFIG_NETTA2_VERSION == 1 -#define PE_GP_INMASK _B(31) -#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30)) -#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28)) -#elif CONFIG_NETTA2_VERSION == 2 -#define PE_GP_INMASK _BR(28, 31) -#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27)) -#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27)) -#endif -#define PE_SP_MASK 0 -#define PE_ODR_VAL 0 -#define PE_SP_DIRVAL 0 - -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile iop8xx_t *ioport = &immap->im_ioport; - volatile cpm8xx_t *cpm = &immap->im_cpm; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* NAND chip select */ -#if CONFIG_NETTA2_VERSION == 1 - memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX); - memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); -#elif CONFIG_NETTA2_VERSION == 2 - upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0])); - memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS); - memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA); - memctl->memc_mamr = 0; /* all clear */ -#endif - - /* DSP chip select */ - memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX); - memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); - -#if CONFIG_NETTA2_VERSION == 1 - memctl->memc_br4 &= ~BR_V; -#endif - memctl->memc_br5 &= ~BR_V; - memctl->memc_br6 &= ~BR_V; - memctl->memc_br7 &= ~BR_V; - - ioport->iop_padat = PA_GP_OUTVAL; - ioport->iop_paodr = PA_ODR_VAL; - ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; - ioport->iop_papar = PA_SP_MASK; - - cpm->cp_pbdat = PB_GP_OUTVAL; - cpm->cp_pbodr = PB_ODR_VAL; - cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; - cpm->cp_pbpar = PB_SP_MASK; - - ioport->iop_pcdat = PC_GP_OUTVAL; - ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; - ioport->iop_pcso = PC_SOVAL; - ioport->iop_pcint = PC_INTVAL; - ioport->iop_pcpar = PC_SP_MASK; - - cpm->cp_pedat = PE_GP_OUTVAL; - cpm->cp_peodr = PE_ODR_VAL; - cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL; - cpm->cp_pepar = PE_SP_MASK; - - return 0; -} - -#ifdef CONFIG_HW_WATCHDOG - -void hw_watchdog_reset(void) -{ - /* XXX add here the really funky stuff */ -} - -#endif - -#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) -int overwrite_console(void) -{ - /* printf("overwrite_console called\n"); */ - return 0; -} -#endif - -extern int drv_phone_init(void); -extern int drv_phone_use_me(void); -extern int drv_phone_is_idle(void); - -int misc_init_r(void) -{ - return 0; -} - -int last_stage_init(void) -{ -#if CONFIG_NETTA2_VERSION == 2 - int i; -#endif - -#if CONFIG_NETTA2_VERSION == 2 - /* assert peripheral reset */ - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12); - for (i = 0; i < 10; i++) - udelay(1000); - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |= _BW(12); -#endif - reset_phys(); - - return 0; -} diff --git a/board/netta2/u-boot.lds b/board/netta2/u-boot.lds deleted file mode 100644 index 0dff5a4023..0000000000 --- a/board/netta2/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/netta2/u-boot.lds.debug b/board/netta2/u-boot.lds.debug deleted file mode 100644 index a198cf9520..0000000000 --- a/board/netta2/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/omicron/calimain/calimain.c b/board/omicron/calimain/calimain.c index dd28915cdc..32f2b20183 100644 --- a/board/omicron/calimain/calimain.c +++ b/board/omicron/calimain/calimain.c @@ -18,7 +18,7 @@ #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/gpio.h> -#include <asm/arch/emif_defs.h> +#include <asm/ti-common/davinci_nand.h> #include <asm/arch/emac_defs.h> #include <asm/arch/pinmux_defs.h> #include <asm/arch/davinci_misc.h> diff --git a/board/overo/overo.c b/board/overo/overo.c index 62b50a8a0b..13220c56dd 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -267,12 +267,14 @@ int misc_init_r(void) expansion_config.revision, expansion_config.fab_revision); setenv("defaultdisplay", "dvi"); + setenv("expansionname", "summit"); break; case GUMSTIX_TOBI: printf("Recognized Tobi expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); setenv("defaultdisplay", "dvi"); + setenv("expansionname", "tobi"); break; case GUMSTIX_TOBI_DUO: printf("Recognized Tobi Duo expansion board (rev %d %s)\n", @@ -293,12 +295,14 @@ int misc_init_r(void) expansion_config.revision, expansion_config.fab_revision); setenv("defaultdisplay", "lcd43"); + setenv("expansionname", "palo43"); break; case GUMSTIX_CHESTNUT43: printf("Recognized Chestnut43 expansion board (rev %d %s)\n", expansion_config.revision, expansion_config.fab_revision); setenv("defaultdisplay", "lcd43"); + setenv("expansionname", "chestnut43"); break; case GUMSTIX_PINTO: printf("Recognized Pinto expansion board (rev %d %s)\n", @@ -310,6 +314,7 @@ int misc_init_r(void) expansion_config.revision, expansion_config.fab_revision); setenv("defaultdisplay", "lcd43"); + setenv("expansionname", "gallop43"); break; case GUMSTIX_ALTO35: printf("Recognized Alto35 expansion board (rev %d %s)\n", @@ -317,6 +322,7 @@ int misc_init_r(void) expansion_config.fab_revision); MUX_ALTO35(); setenv("defaultdisplay", "lcd35"); + setenv("expansionname", "alto35"); break; case GUMSTIX_STAGECOACH: printf("Recognized Stagecoach expansion board (rev %d %s)\n", @@ -349,8 +355,11 @@ int misc_init_r(void) break; case GUMSTIX_NO_EEPROM: puts("No EEPROM on expansion board\n"); + setenv("expansionname", "tobi"); break; default: + if (expansion_id == 0x0) + setenv("expansionname", "tobi"); printf("Unrecognized expansion board 0x%08x\n", expansion_id); break; } @@ -360,6 +369,11 @@ int misc_init_r(void) dieid_num_r(); + if (get_cpu_family() == CPU_OMAP34XX) + setenv("boardname", "overo"); + else + setenv("boardname", "overo-storm"); + return 0; } diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index f90e809d15..267c001435 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -13,7 +13,7 @@ #include <asm/processor.h> #include <spd_sdram.h> #include <status_led.h> -#include <sha1.h> +#include <u-boot/sha1.h> #include <asm/io.h> #include <net.h> #include <ata.h> diff --git a/board/psyent/common/AMDLV065D.c b/board/psyent/common/AMDLV065D.c index 409a7a82fb..64cb97029e 100644 --- a/board/psyent/common/AMDLV065D.c +++ b/board/psyent/common/AMDLV065D.c @@ -7,11 +7,7 @@ #include <common.h> -#if defined(CONFIG_NIOS) -#include <nios.h> -#else #include <asm/io.h> -#endif #define SECTSZ (64 * 1024) flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; diff --git a/board/quad100hd/Makefile b/board/quad100hd/Makefile deleted file mode 100644 index b65e5ad471..0000000000 --- a/board/quad100hd/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = quad100hd.o nand.o diff --git a/board/quad100hd/nand.c b/board/quad100hd/nand.c deleted file mode 100644 index 47bbb6b262..0000000000 --- a/board/quad100hd/nand.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * (C) Copyright 2008 - * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <config.h> -#if defined(CONFIG_CMD_NAND) -#include <asm/ppc4xx-gpio.h> -#include <asm/io.h> -#include <nand.h> - -/* - * hardware specific access to control-lines - */ -static void quad100hd_hwcontrol(struct mtd_info *mtd, - int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - - if (ctrl & NAND_CTRL_CHANGE) { - gpio_write_bit(CONFIG_SYS_NAND_CLE, !!(ctrl & NAND_CLE)); - gpio_write_bit(CONFIG_SYS_NAND_ALE, !!(ctrl & NAND_ALE)); - gpio_write_bit(CONFIG_SYS_NAND_CE, !(ctrl & NAND_NCE)); - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -static int quad100hd_nand_ready(struct mtd_info *mtd) -{ - return gpio_read_in_bit(CONFIG_SYS_NAND_RDY); -} - -/* - * Main initialization routine - */ -int board_nand_init(struct nand_chip *nand) -{ - /* Set address of hardware control function */ - nand->cmd_ctrl = quad100hd_hwcontrol; - nand->dev_ready = quad100hd_nand_ready; - nand->ecc.mode = NAND_ECC_SOFT; - /* 15 us command delay time */ - nand->chip_delay = 20; - - /* Return happy */ - return 0; -} -#endif /* CONFIG_CMD_NAND */ diff --git a/board/quad100hd/quad100hd.c b/board/quad100hd/quad100hd.c deleted file mode 100644 index bb14ca7056..0000000000 --- a/board/quad100hd/quad100hd.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2008 - * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de. - * - * Based in part on board/icecube/icecube.c from PPCBoot - * (C) Copyright 2003 Intrinsyc Software - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <malloc.h> -#include <environment.h> -#include <logbuff.h> -#include <post.h> - -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* taken from PPCBoot */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); - mtdcr(UIC0PR, 0xFFFF7FFE); /* set int polarities */ - mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - - mtdcr(CPC0_SRR, 0x00040000); /* Hold PCI bridge in reset */ - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); -#ifdef DISPLAY_BOARD_INFO - sys_info_t sysinfo; -#endif - - puts("Board: Quad100hd"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - -#ifdef DISPLAY_BOARD_INFO - /* taken from ppcboot */ - get_sys_info(&sysinfo); - - printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz); - printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); - printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000); - printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000); - printf("\tEPB: %lu MHz\n", sysinfo.freqPLB / (sysinfo.pllExtBusDiv * - 1000000)); - printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000); -#endif - - return 0; -} diff --git a/board/quantum/Makefile b/board/quantum/Makefile deleted file mode 100644 index 6918f63c3e..0000000000 --- a/board/quantum/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = quantum.o fpga.o diff --git a/board/quantum/fpga.c b/board/quantum/fpga.c deleted file mode 100644 index 4bd391a546..0000000000 --- a/board/quantum/fpga.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* The DEBUG define must be before common to enable debugging */ -#undef DEBUG -#include <common.h> -#include <asm/processor.h> -#include <command.h> -#include "fpga.h" -/* ------------------------------------------------------------------------- */ - -#define MAX_ONES 226 - -/* MPC850 port D */ -#define PD(bit) (1 << (15 - (bit))) -# define FPGA_INIT PD(11) /* FPGA init pin (ppc input) */ -# define FPGA_PRG PD(12) /* FPGA program pin (ppc output) */ -# define FPGA_CLK PD(13) /* FPGA clk pin (ppc output) */ -# define FPGA_DATA PD(14) /* FPGA data pin (ppc output) */ -# define FPGA_DONE PD(15) /* FPGA done pin (ppc input) */ - - -/* DDR 0 - input, 1 - output */ -#define FPGA_INIT_PDDIR FPGA_PRG | FPGA_CLK | FPGA_DATA /* just set outputs */ - - -#define SET_FPGA(data) immr->im_ioport.iop_pddat = (data) -#define GET_FPGA immr->im_ioport.iop_pddat - -#define FPGA_WRITE_1 { \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ - -#define FPGA_WRITE_0 { \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \ - SET_FPGA(FPGA_PRG); /* set data to 0 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ - - -int fpga_boot (unsigned char *fpgadata, int size) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - int i, index, len; - int count; - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - int j; - unsigned char data; -#else - unsigned char b; - int bit; -#endif - - debug ("fpga_boot: fpgadata = %p, size = %d\n", fpgadata, size); - - /* display infos on fpgaimage */ - printf ("FPGA:"); - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf (" %s", &(fpgadata[index + 1])); - index += len + 3; - } - printf ("\n"); - - - index = 0; - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - /* search for preamble 0xFFFFFFFF */ - while (1) { - if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff) - && (fpgadata[index + 2] == 0xff) - && (fpgadata[index + 3] == 0xff)) - break; /* preamble found */ - else - index++; - } -#else - /* search for preamble 0xFF2X */ - for (index = 0; index < size - 1; index++) { - if ((fpgadata[index] == 0xff) - && ((fpgadata[index + 1] & 0xf0) == 0x30)) - break; - } - index += 2; -#endif - - debug ("FPGA: configdata starts at position 0x%x\n", index); - debug ("FPGA: length of fpga-data %d\n", size - index); - - /* - * Setup port pins for fpga programming - */ - immr->im_ioport.iop_pddir = FPGA_INIT_PDDIR; - - debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* - * Init fpga by asserting and deasserting PROGRAM* - */ - SET_FPGA (FPGA_CLK | FPGA_DATA); - - /* Wait for FPGA init line low */ - count = 0; - while (GET_FPGA & FPGA_INIT) { - udelay (1000); /* wait 1ms */ - /* Check for timeout - 100us max, so use 3ms */ - if (count++ > 3) { - debug ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_LOW; - } - } - - debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* deassert PROGRAM* */ - SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA); - - /* Wait for FPGA end of init period . */ - count = 0; - while (!(GET_FPGA & FPGA_INIT)) { - udelay (1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - debug ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_HIGH; - } - } - - debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - debug ("write configuration data into fpga\n"); - /* write configuration-data into fpga... */ - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - /* - * Load uncompressed image into fpga - */ - for (i = index; i < size; i++) { -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - if ((i % 1024) == 0) - printf ("%6d out of %6d\r", i, size); /* let them know we are alive */ -#endif - - data = fpgadata[i]; - for (j = 0; j < 8; j++) { - if ((data & 0x80) == 0x80) { - FPGA_WRITE_1; - } else { - FPGA_WRITE_0; - } - data <<= 1; - } - } - /* add some 0xff to the end of the file */ - for (i = 0; i < 8; i++) { - data = 0xff; - for (j = 0; j < 8; j++) { - if ((data & 0x80) == 0x80) { - FPGA_WRITE_1; - } else { - FPGA_WRITE_0; - } - data <<= 1; - } - } -#else - /* send 0xff 0x20 */ - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_1; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - - /* - ** Bit_DeCompression - ** Code 1 .. maxOnes : n '1's followed by '0' - ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0' - ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1' - ** 255 : '1' - */ - - for (i = index; i < size; i++) { - b = fpgadata[i]; - if ((b >= 1) && (b <= MAX_ONES)) { - for (bit = 0; bit < b; bit++) { - FPGA_WRITE_1; - } - FPGA_WRITE_0; - } else if (b == (MAX_ONES + 1)) { - for (bit = 1; bit < b; bit++) { - FPGA_WRITE_1; - } - } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) { - for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) { - FPGA_WRITE_0; - } - FPGA_WRITE_1; - } else if (b == 255) { - FPGA_WRITE_1; - } - } -#endif - debug ("\n\n"); - debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* - * Check if fpga's DONE signal - correctly booted ? - */ - - /* Wait for FPGA end of programming period . */ - count = 0; - while (!(GET_FPGA & FPGA_DONE)) { - udelay (1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - debug ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_DONE; - } - } - - debug ("FPGA: Booting successful!\n"); - return 0; -} diff --git a/board/quantum/fpga.h b/board/quantum/fpga.h deleted file mode 100644 index a9f4086297..0000000000 --- a/board/quantum/fpga.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Virtex2 FPGA configuration support for the QUANTUM computer - */ -int fpga_boot(unsigned char *fpgadata, int size); - -#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ -#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ -#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ diff --git a/board/quantum/quantum.c b/board/quantum/quantum.c deleted file mode 100644 index 17e3fc2679..0000000000 --- a/board/quantum/quantum.c +++ /dev/null @@ -1,243 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include <mpc8xx.h> -#include "fpga.h" - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -unsigned long flash_init (void); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = { - /* - * Single Read. (Offset 00h in UPMA RAM) - */ - 0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Read. (Offset 08h in UPMA RAM) - */ - 0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20, - 0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18h in UPMA RAM) - */ - 0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20h in UPMA RAM) - */ - 0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22, - 0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Refresh. (Offset 30h in UPMA RAM) - * (Initialization code at 0x36) - */ - 0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34, - 0x0FFACCB4, 0x0FF5CC34, 0x0FFCC34, 0x0FFFCCB4, - - /* - * Exception. (Offset 3Ch in UPMA RAM) - */ - 0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_ -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char buf[64]; - int i; - int l = getenv_f("serial#", buf, sizeof(buf)); - - puts ("Board QUANTUM, Serial No: "); - - for (i = 0; i < l; ++i) { - if (buf[i] == ' ') - break; - putc (buf[i]); - } - putc ('\n'); - return (0); /* success */ -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size9; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_mar = 0x00000088; - - /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002136; /* SDRAM bank 0 */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* Check Bank 0 Memory Size, - * 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - /* - * Final mapping: - */ - memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - udelay (1000); - - return (size9); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile ulong *addr; - ulong cnt, val, size; - ulong save[32]; /* to make test non-destructive */ - unsigned char i = 0; - - memctl->memc_mamr = mamr_value; - - for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { - addr = (volatile ulong *)(base + cnt); /* pointer arith! */ - - save[i++] = *addr; - *addr = ~cnt; - } - - /* write 0 to base address */ - addr = (volatile ulong *)base; - save[i] = *addr; - *addr = 0; - - /* check at base address */ - if ((val = *addr) != 0) { - /* Restore the original data before leaving the function. - */ - *addr = save[i]; - for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { - addr = (volatile ulong *) base + cnt; - *addr = save[--i]; - } - return (0); - } - - for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { - addr = (volatile ulong *)(base + cnt); /* pointer arith! */ - - val = *addr; - *addr = save[--i]; - - if (val != (~cnt)) { - size = cnt * sizeof (long); - /* Restore the original data before returning - */ - for (cnt <<= 1; cnt <= maxsize / sizeof (long); - cnt <<= 1) { - addr = (volatile ulong *) base + cnt; - *addr = save[--i]; - } - return (size); - } - } - return (maxsize); -} - -/* - * Miscellaneous intialization - */ -int misc_init_r (void) -{ - char *fpga_data_str = getenv ("fpgadata"); - char *fpga_size_str = getenv ("fpgasize"); - void *fpga_data; - int fpga_size; - int status; - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - int flash_size; - - /* Remap FLASH according to real size */ - flash_size = flash_init (); - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_size & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - if (fpga_data_str && fpga_size_str) { - fpga_data = (void *) simple_strtoul (fpga_data_str, NULL, 16); - fpga_size = simple_strtoul (fpga_size_str, NULL, 10); - - status = fpga_boot (fpga_data, fpga_size); - if (status != 0) { - printf ("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf ("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - } - } - return 0; -} diff --git a/board/quantum/u-boot.lds b/board/quantum/u-boot.lds deleted file mode 100644 index 0eb2fba00c..0000000000 --- a/board/quantum/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/quantum/u-boot.lds.debug b/board/quantum/u-boot.lds.debug deleted file mode 100644 index b2c562c33d..0000000000 --- a/board/quantum/u-boot.lds.debug +++ /dev/null @@ -1,114 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/rattler/Makefile b/board/rattler/Makefile deleted file mode 100644 index 9de89c8096..0000000000 --- a/board/rattler/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := rattler.o diff --git a/board/rattler/rattler.c b/board/rattler/rattler.c deleted file mode 100644 index f7fb349f71..0000000000 --- a/board/rattler/rattler.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * Copyright (C) 2004 Arabella Software Ltd. - * Yuli Barcohen <yuli@arabellasw.com> - * - * Support for Analogue&Micro Rattler boards family. - * Tested on Rattler8248. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8260.h> -#include <ioports.h> - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1) -#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2) - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ - /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ - /* PA22 */ { 1, 0, 0, 1, 0, 1 }, /* Eth PHYs reset */ - /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ - /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ - /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */ - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK10) */ - /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK11) */ - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ - /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */ - /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */ - /* PC17 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK15) */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */ - /* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */ - /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */ - /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ - /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ - /* PD15 */ { 0, 0, 0, 0, 0, 0 }, /* PD15 */ - /* PD14 */ { 0, 0, 0, 0, 0, 0 }, /* PD14 */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ - /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ - } -}; - -phys_size_t initdram(int board_type) -{ - long int msize = CONFIG_SYS_SDRAM_SIZE; - -#ifndef CONFIG_SYS_RAMBOOT - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE; - uchar c = 0xFF; - uint psdmr = CONFIG_SYS_PSDMR; - int i; - - immap->im_siu_conf.sc_ppc_acr = 0x02; - immap->im_siu_conf.sc_ppc_alrh = 0x30126745; - immap->im_siu_conf.sc_tescr1 = 0x00004000; - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - /* Initialise 60x bus SDRAM */ - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_or1 = CONFIG_SYS_SDRAM_OR; - memctl->memc_br1 = CONFIG_SYS_SDRAM_BR; - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ - for (i = 0; i < 8; i++) - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */ - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ - *ramaddr = c; -#endif /* !CONFIG_SYS_RAMBOOT */ - - /* Return total 60x bus SDRAM size */ - return msize * 1024 * 1024; -} - -int checkboard(void) -{ - vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; - - printf("Board: Rattler Rev. %c\n", bcsr[0x20] + 0x40); - return 0; -} diff --git a/board/rbc823/Makefile b/board/rbc823/Makefile deleted file mode 100644 index 060a144a92..0000000000 --- a/board/rbc823/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = rbc823.o flash.o kbd.o diff --git a/board/rbc823/flash.c b/board/rbc823/flash.c deleted file mode 100644 index 8a2265263c..0000000000 --- a/board/rbc823/flash.c +++ /dev/null @@ -1,445 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/* - * Functions - */ -static ulong flash_get_size(vu_long *addr, flash_info_t *info); -static int write_word(flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets(ulong base, flash_info_t *info); - -unsigned long flash_init(void) -{ - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* Detect size */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, - &flash_info[0]); - - /* Setup offsets */ - flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* Monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return size_b0; -} - -/*----------------------------------------------------------------------- - * Fix this to support variable sector sizes -*/ -static void flash_get_offsets(ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - /* set sector offsets for bottom boot block type */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - puts("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_BM: - printf("BRIGHT MICRO "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - if (info->size >> 20) { - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - } else { - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, - info->sector_count); - } - - puts(" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - puts("\n "); - - printf(" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - putc('\n'); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size(vu_long *addr, flash_info_t *info) -{ - short i; - volatile unsigned char *caddr; - char value; - - caddr = (volatile unsigned char *)addr ; - - /* Write auto select command: read Manufacturer ID */ - - debug("Base address is: %8p\n", caddr); - - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0x90; - - value = caddr[0]; - - debug("Manufact ID: %02x\n", value); - - switch (value) { - case 0x01: /*AMD_MANUFACT*/ - info->flash_id = FLASH_MAN_AMD; - break; - - case 0x04: /*FUJ_MANUFACT*/ - info->flash_id = FLASH_MAN_FUJ; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - value = caddr[1]; /* device ID */ - - debug("Device ID: %02x\n", value); - - switch (value) { - case AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512Kb */ - - default: - info->flash_id = FLASH_UNKNOWN; - return 0; /* => no or unknown flash */ - } - - flash_get_offsets((ulong)addr, &flash_info[0]); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* - * read sector protection at sector address, - * (A7 .. A0) = 0x02 - * D0 = 1 if protected - */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (volatile unsigned char *)info->start[0]; - *caddr = 0xF0; /* reset bank */ - } - - return info->size; -} - - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - volatile unsigned char *addr = - (volatile unsigned char *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (volatile unsigned char *)(info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = start; - addr = (volatile unsigned char *)(info->start[l_sect]); - - while ((addr[0] & 0xFF) != 0xFF) { - now = get_timer(start); - if (now > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned char *)info->start[0]; - - addr[0] = 0xF0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - l = addr - wp; - - if (l != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - - for (; cnt == 0 && i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - rc = write_word(info, wp, data); - - if (rc != 0) - return rc; - - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) - data = (data << 8) | *src++; - - rc = write_word(info, wp, data); - - if (rc != 0) - return rc; - - wp += 4; - cnt -= 4; - } - - if (cnt == 0) - return 0; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - return write_word(info, wp, data); -} - -/* - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word(flash_info_t *info, ulong dest, ulong data) -{ - volatile unsigned char *cdest, *cdata; - volatile unsigned char *addr = - (volatile unsigned char *)(info->start[0]); - ulong start; - int flag, count = 4 ; - - cdest = (volatile unsigned char *)dest ; - cdata = (volatile unsigned char *)&data ; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest)&data) != data) - return 2; - - while (count--) { - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *cdest = *cdata; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*cdest ^ *cdata) & 0x80) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return 1; - } - - cdata++ ; - cdest++ ; - } - return 0; -} diff --git a/board/rbc823/kbd.c b/board/rbc823/kbd.c deleted file mode 100644 index b35509ab39..0000000000 --- a/board/rbc823/kbd.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Modified by Udi Finkelstein - * - * This file includes communication routines for SMC1 that can run even if - * SMC2 have already been initialized. - */ - -#include <common.h> -#include <watchdog.h> -#include <commproc.h> -#include <stdio_dev.h> -#include <lcd.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define SMC_INDEX 0 -#define PROFF_SMC PROFF_SMC1 -#define CPM_CR_CH_SMC CPM_CR_CH_SMC1 - -#define RBC823_KBD_BAUDRATE 38400 -#define CPM_KEYBOARD_BASE 0x1000 -/* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. - */ - -void smc1_setbrg (void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - - /* Set up the baud rate generator. - * See 8xx_io/commproc.c for details. - * - * Wire BRG2 to SMC1, BRG1 to SMC2 - */ - - cp->cp_simode = 0x00001000; - - cp->cp_brgc2 = - (((gd->cpu_clk / 16 / RBC823_KBD_BAUDRATE)-1) << 1) | CPM_BRG_EN; -} - -int smc1_init (void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile smc_t *sp; - volatile smc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8xx_t *cp = &(im->im_cpm); - uint dpaddr; - - /* initialize pointers to SMC */ - - sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]); - up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC]; - - /* Disable transmitter/receiver. - */ - sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); - - /* Enable SDMA. - */ - im->im_siu_conf.sc_sdcr = 1; - - /* clear error conditions */ -#ifdef CONFIG_SYS_SDSR - im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR; -#else - im->im_sdma.sdma_sdsr = 0x83; -#endif - - /* clear SDMA interrupt mask */ -#ifdef CONFIG_SYS_SDMR - im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR; -#else - im->im_sdma.sdma_sdmr = 0x00; -#endif - - /* Use Port B for SMC1 instead of other functions. - */ - cp->cp_pbpar |= 0x000000c0; - cp->cp_pbdir &= ~0x000000c0; - cp->cp_pbodr &= ~0x000000c0; - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - -#ifdef CONFIG_SYS_ALLOC_DPRAM - dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ; -#else - dpaddr = CPM_KEYBOARD_BASE ; -#endif - - /* Allocate space for two buffer descriptors in the DP ram. - * For now, this address seems OK, but it may have to - * change with newer versions of the firmware. - * damm: allocating space after the two buffers for rx/tx data - */ - - rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = 0; - - /* Set up the uart parameters in the parameter ram. - */ - up->smc_rbase = dpaddr; - up->smc_tbase = dpaddr+sizeof(cbd_t); - up->smc_rfcr = SMC_EB; - up->smc_tfcr = SMC_EB; - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - */ - sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; - - /* Mask all interrupts and remove anything pending. - */ - sp->smc_smcm = 0; - sp->smc_smce = 0xff; - - /* Set up the baud rate generator. - */ - smc1_setbrg (); - - /* Make the first buffer the only buffer. - */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Single character receive. - */ - up->smc_mrblr = 1; - up->smc_maxidl = 0; - - /* Initialize Tx/Rx parameters. - */ - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. - */ - sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; - - return (0); -} - -void smc1_putc(const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; - - tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase]; - - /* Wait for last character to go. - */ - - buf = (char *)tbdf->cbd_bufaddr; - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; - __asm__("eieio"); - - while (tbdf->cbd_sc & BD_SC_READY) { - WATCHDOG_RESET (); - __asm__("eieio"); - } -} - -int smc1_getc(void) -{ - volatile cbd_t *rbdf; - volatile unsigned char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - unsigned char c; - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; - - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - /* Wait for character to show up. - */ - buf = (unsigned char *)rbdf->cbd_bufaddr; - - while (rbdf->cbd_sc & BD_SC_EMPTY) - WATCHDOG_RESET (); - - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return(c); -} - -int smc1_tstc(void) -{ - volatile cbd_t *rbdf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; - - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - return(!(rbdf->cbd_sc & BD_SC_EMPTY)); -} - -/* search for keyboard and register it if found */ -int drv_keyboard_init(void) -{ - int error = 0; - struct stdio_dev kbd_dev; - - if (0) { - /* register the keyboard */ - memset (&kbd_dev, 0, sizeof(struct stdio_dev)); - strcpy(kbd_dev.name, "kbd"); - kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - kbd_dev.putc = NULL; - kbd_dev.puts = NULL; - kbd_dev.getc = smc1_getc; - kbd_dev.tstc = smc1_tstc; - error = stdio_register (&kbd_dev); - } else { - lcd_is_enabled = 0; - lcd_disable(); - } - return error; -} diff --git a/board/rbc823/rbc823.c b/board/rbc823/rbc823.c deleted file mode 100644 index 5881111c70..0000000000 --- a/board/rbc823/rbc823.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include "mpc8xx.h" -#include <linux/mtd/doc2000.h> - -extern int kbd_init(void); -extern int drv_kbd_init(void); - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x1FF7FC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -const uint static_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x0FFFFC04, 0x0FF3FC04, 0x0FF3CC04, 0x0FF3CC04, - 0x0FF3EC04, 0x0FF3CC00, 0x0FF7FC04, 0x3FFFFC04, - 0xFFFFFC04, 0xFFFFFC05, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x0FFFFC04, 0x00FFFC04, 0x00FFFC04, 0x00FFFC04, - 0x01FFFC00, 0x3FFFFC04, 0xFFFFFC04, 0xFFFFFC05, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - * - * Test TQ ID string (TQM8xx...) - * If present, check for "L" type (no second DRAM bank), - * otherwise "L" type is assumed as default. - * - * Return 1 for "L" type, 0 else. - */ - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - if (i < 0 || strncmp(buf, "TQM8", 4)) { - printf ("### No HW ID - assuming RBC823\n"); - return (0); - } - - puts(buf); - putc('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0, size8, size9; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * 1 Bank of 64Mbit x 2 devices - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K; - memctl->memc_mar = 0x00000088; - - /* - * Map controller SDRAM bank 0 - */ - memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; - memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - udelay (200); - - /* - * Perform SDRAM initializsation sequence - */ - memctl->memc_mcr = 0x80008105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X; - udelay (200); - memctl->memc_mcr = 0x80008130; /* SDRAM bank 0 - execute twice */ - udelay (1); - memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X; - udelay (200); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - udelay (1000); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; /* 16: but should be: CONFIG_SYS_MPTPR_1BK_4K */ - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM, - SDRAM_MAX_SIZE); - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay (1000); - } - - /* SDRAM Bank 0 is bigger - map first */ - - memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br4 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - udelay (10000); - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} - -#ifdef CONFIG_CMD_DOC -void doc_init (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig (UPMB, (uint *) static_table, - sizeof (static_table) / sizeof (uint)); - memctl->memc_mbmr = MAMR_DSA_1_CYCL; - - doc_probe (FLASH_BASE1_PRELIM); -} -#endif diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds deleted file mode 100644 index 7676cf43b1..0000000000 --- a/board/rbc823/u-boot.lds +++ /dev/null @@ -1,92 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - lib/built-in.o (.text*) - net/built-in.o (.text*) - arch/powerpc/cpu/mpc8xx/built-in.o (.text*) - arch/powerpc/lib/built-in.o (.text*) - - . = env_offset; - common/env_embedded.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index ec3ac89593..1f7679a240 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -117,20 +117,20 @@ static void pm9261_dm9000_hw_init(void) #ifdef CONFIG_LCD vidinfo_t panel_info = { - vl_col: 240, - vl_row: 320, - vl_clk: 4965000, - vl_sync: ATMEL_LCDC_INVLINE_INVERTED | - ATMEL_LCDC_INVFRAME_INVERTED, - vl_bpix: 3, - vl_tft: 1, - vl_hsync_len: 5, - vl_left_margin: 1, - vl_right_margin:33, - vl_vsync_len: 1, - vl_upper_margin:1, - vl_lower_margin:0, - mmio: ATMEL_BASE_LCDC, + .vl_col = 240, + .vl_row = 320, + .vl_clk = 4965000, + .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + .vl_bpix = 3, + .vl_tft = 1, + .vl_hsync_len = 5, + .vl_left_margin = 1, + .vl_right_margin = 33, + .vl_vsync_len = 1, + .vl_upper_margin = 1, + .vl_lower_margin = 0, + .mmio = ATMEL_BASE_LCDC, }; void lcd_enable(void) diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 3aaffa803c..1b00f08835 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -115,20 +115,20 @@ static void pm9263_macb_hw_init(void) #ifdef CONFIG_LCD vidinfo_t panel_info = { - vl_col: 240, - vl_row: 320, - vl_clk: 4965000, - vl_sync: ATMEL_LCDC_INVLINE_INVERTED | - ATMEL_LCDC_INVFRAME_INVERTED, - vl_bpix: 3, - vl_tft: 1, - vl_hsync_len: 5, - vl_left_margin: 1, - vl_right_margin:33, - vl_vsync_len: 1, - vl_upper_margin:1, - vl_lower_margin:0, - mmio: ATMEL_BASE_LCDC, + .vl_col = 240, + .vl_row = 320, + .vl_clk = 4965000, + .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + .vl_bpix = 3, + .vl_tft = 1, + .vl_hsync_len = 5, + .vl_left_margin = 1, + .vl_right_margin = 33, + .vl_vsync_len = 1, + .vl_upper_margin = 1, + .vl_lower_margin = 0, + .mmio = ATMEL_BASE_LCDC, }; void lcd_enable(void) diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index de154e0f64..9dc7c832e6 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -243,13 +243,6 @@ int board_eth_init(bd_t *bis) int board_mmc_init(bd_t *bis) { int ret; - -#ifdef CONFIG_SDHCI - /* mmc initializattion for available channels */ - ret = exynos_mmc_init(gd->fdt_blob); - if (ret) - debug("mmc init failed\n"); -#endif #ifdef CONFIG_DWMMC /* dwmmc initializattion for available channels */ ret = exynos_dwmmc_init(gd->fdt_blob); @@ -257,6 +250,12 @@ int board_mmc_init(bd_t *bis) debug("dwmmc init failed\n"); #endif +#ifdef CONFIG_SDHCI + /* mmc initializattion for available channels */ + ret = exynos_mmc_init(gd->fdt_blob); + if (ret) + debug("mmc init failed\n"); +#endif return ret; } #endif diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index 4cea63b813..eb0f9bffae 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -14,6 +14,8 @@ #include <asm/arch/cpu.h> #include <power/max8998_pmic.h> #include <samsung/misc.h> +#include <usb.h> +#include <usb_mass_storage.h> DECLARE_GLOBAL_DATA_PTR; @@ -175,6 +177,12 @@ struct s3c_plat_otg_data s5pc110_otg_data = { .regs_otg = S5PC110_OTG_BASE, .usb_phy_ctrl = S5PC110_USB_PHY_CONTROL, }; + +int board_usb_init(int index, enum usb_init_type init) +{ + debug("USB_udc_probe\n"); + return s3c_udc_probe(&s5pc110_otg_data); +} #endif #ifdef CONFIG_MISC_INIT_R diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile index 6a586553e1..3d96b077b4 100644 --- a/board/samsung/smdk5250/Makefile +++ b/board/samsung/smdk5250/Makefile @@ -7,9 +7,5 @@ obj-y += smdk5250_spl.o ifndef CONFIG_SPL_BUILD -ifdef CONFIG_OF_CONTROL obj-y += exynos5-dt.o -else -obj-y += smdk5250.o -endif endif diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c index 58821c41a4..d6ce1337b9 100644 --- a/board/samsung/smdk5250/exynos5-dt.c +++ b/board/samsung/smdk5250/exynos5-dt.c @@ -11,15 +11,16 @@ #include <i2c.h> #include <netdev.h> #include <spi.h> +#include <asm/gpio.h> #include <asm/arch/cpu.h> #include <asm/arch/dwmmc.h> -#include <asm/arch/gpio.h> #include <asm/arch/mmc.h> #include <asm/arch/pinmux.h> #include <asm/arch/power.h> #include <asm/arch/sromc.h> #include <power/pmic.h> #include <power/max77686_pmic.h> +#include <power/tps65090_pmic.h> #include <tmu.h> DECLARE_GLOBAL_DATA_PTR; @@ -41,7 +42,197 @@ int exynos_init(void) return 0; } +#if defined(CONFIG_POWER) +#ifdef CONFIG_POWER_MAX77686 +static int pmic_reg_update(struct pmic *p, int reg, uint regval) +{ + u32 val; + int ret = 0; + + ret = pmic_reg_read(p, reg, &val); + if (ret) { + debug("%s: PMIC %d register read failed\n", __func__, reg); + return -1; + } + val |= regval; + ret = pmic_reg_write(p, reg, val); + if (ret) { + debug("%s: PMIC %d register write failed\n", __func__, reg); + return -1; + } + return 0; +} + +static int max77686_init(void) +{ + struct pmic *p; + + if (pmic_init(I2C_PMIC)) + return -1; + + p = pmic_get("MAX77686_PMIC"); + if (!p) + return -ENODEV; + + if (pmic_probe(p)) + return -1; + + if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) + return -1; + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, + MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) + return -1; + + /* VDD_MIF */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, + MAX77686_BUCK1OUT_1V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK1OUT); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, + MAX77686_BUCK1CTRL_EN)) + return -1; + + /* VDD_ARM */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, + MAX77686_BUCK2DVS1_1_3V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK2DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, + MAX77686_BUCK2CTRL_ON)) + return -1; + + /* VDD_INT */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, + MAX77686_BUCK3DVS1_1_0125V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK3DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, + MAX77686_BUCK3CTRL_ON)) + return -1; + + /* VDD_G3D */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, + MAX77686_BUCK4DVS1_1_2V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK4DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, + MAX77686_BUCK3CTRL_ON)) + return -1; + + /* VDD_LDO2 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, + MAX77686_LD02CTRL1_1_5V | EN_LDO)) + return -1; + + /* VDD_LDO3 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, + MAX77686_LD03CTRL1_1_8V | EN_LDO)) + return -1; + + /* VDD_LDO5 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, + MAX77686_LD05CTRL1_1_8V | EN_LDO)) + return -1; + + /* VDD_LDO10 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, + MAX77686_LD10CTRL1_1_8V | EN_LDO)) + return -1; + + return 0; +} +#endif /* CONFIG_POWER_MAX77686 */ + +int exynos_power_init(void) +{ + int ret = 0; + +#ifdef CONFIG_POWER_MAX77686 + ret = max77686_init(); + if (ret) + return ret; +#endif +#ifdef CONFIG_POWER_TPS65090 + /* + * The TPS65090 may not be in the device tree. If so, it is not + * an error. + */ + ret = tps65090_init(); + if (ret == 0 || ret == -ENODEV) + return 0; +#endif + + return ret; +} +#endif /* CONFIG_POWER */ + #ifdef CONFIG_LCD +static int board_dp_bridge_setup(void) +{ + const int max_tries = 10; + int num_tries, node; + + /* + * TODO(sjg): Use device tree for GPIOs when exynos GPIO + * numbering patch is in mainline. + */ + debug("%s\n", __func__); + node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_NXP_PTN3460); + if (node < 0) { + debug("%s: No node for DP bridge in device tree\n", __func__); + return -ENODEV; + } + + /* Setup the GPIOs */ + + /* PD is ACTIVE_LOW, and initially de-asserted */ + gpio_set_pull(EXYNOS5_GPIO_Y25, S5P_GPIO_PULL_NONE); + gpio_direction_output(EXYNOS5_GPIO_Y25, 1); + + /* Reset is ACTIVE_LOW */ + gpio_set_pull(EXYNOS5_GPIO_X15, S5P_GPIO_PULL_NONE); + gpio_direction_output(EXYNOS5_GPIO_X15, 0); + + udelay(10); + gpio_set_value(EXYNOS5_GPIO_X15, 1); + + gpio_direction_input(EXYNOS5_GPIO_X07); + + /* + * We need to wait for 90ms after bringing up the bridge since there + * is a phantom "high" on the HPD chip during its bootup. The phantom + * high comes within 7ms of de-asserting PD and persists for at least + * 15ms. The real high comes roughly 50ms after PD is de-asserted. The + * phantom high makes it hard for us to know when the NXP chip is up. + */ + mdelay(90); + + for (num_tries = 0; num_tries < max_tries; num_tries++) { + /* Check HPD. If it's high, we're all good. */ + if (gpio_get_value(EXYNOS5_GPIO_X07)) + return 0; + + debug("%s: eDP bridge failed to come up; try %d of %d\n", + __func__, num_tries, max_tries); + } + + /* Immediately go into bridge reset if the hp line is not high */ + return -ENODEV; +} + void exynos_cfg_lcd_gpio(void) { /* For Backlight */ @@ -60,4 +251,49 @@ void exynos_set_dp_phy(unsigned int onoff) { set_dp_phy_ctrl(onoff); } + +void exynos_backlight_on(unsigned int on) +{ + debug("%s(%u)\n", __func__, on); + + if (!on) + return; + +#ifdef CONFIG_POWER_TPS65090 + int ret; + + ret = tps65090_fet_enable(1); /* Enable FET1, backlight */ + if (ret) + return; + + /* T5 in the LCD timing spec (defined as > 10ms) */ + mdelay(10); + + /* board_dp_backlight_pwm */ + gpio_direction_output(EXYNOS5_GPIO_B20, 1); + + /* T6 in the LCD timing spec (defined as > 10ms) */ + mdelay(10); + + /* board_dp_backlight_en */ + gpio_direction_output(EXYNOS5_GPIO_X30, 1); +#endif +} + +void exynos_lcd_power_on(void) +{ + int ret; + + debug("%s\n", __func__); + +#ifdef CONFIG_POWER_TPS65090 + /* board_dp_lcd_vdd */ + tps65090_fet_enable(6); /* Enable FET6, lcd panel */ +#endif + + ret = board_dp_bridge_setup(); + if (ret && ret != -ENODEV) + printf("LCD bridge failed to enable: %d\n", ret); +} + #endif diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c deleted file mode 100644 index 014b7bdf89..0000000000 --- a/board/samsung/smdk5250/smdk5250.c +++ /dev/null @@ -1,363 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <cros_ec.h> -#include <fdtdec.h> -#include <asm/io.h> -#include <errno.h> -#include <i2c.h> -#include <lcd.h> -#include <netdev.h> -#include <spi.h> -#include <asm/arch/cpu.h> -#include <asm/arch/dwmmc.h> -#include <asm/arch/gpio.h> -#include <asm/arch/mmc.h> -#include <asm/arch/pinmux.h> -#include <asm/arch/power.h> -#include <asm/arch/sromc.h> -#include <asm/arch/dp_info.h> -#include <power/pmic.h> -#include <power/max77686_pmic.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SOUND_MAX98095 -static void board_enable_audio_codec(void) -{ - /* Enable MAX98095 Codec */ - gpio_direction_output(EXYNOS5_GPIO_X17, 1); - gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE); -} -#endif - -int exynos_init(void) -{ -#ifdef CONFIG_SOUND_MAX98095 - board_enable_audio_codec(); -#endif - return 0; -} - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_SMC911X - u32 smc_bw_conf, smc_bc_conf; - struct fdt_sromc config; - fdt_addr_t base_addr; - - /* Non-FDT configuration - bank number and timing parameters*/ - config.bank = CONFIG_ENV_SROM_BANK; - config.width = 2; - - config.timing[FDT_SROM_TACS] = 0x01; - config.timing[FDT_SROM_TCOS] = 0x01; - config.timing[FDT_SROM_TACC] = 0x06; - config.timing[FDT_SROM_TCOH] = 0x01; - config.timing[FDT_SROM_TAH] = 0x0C; - config.timing[FDT_SROM_TACP] = 0x09; - config.timing[FDT_SROM_PMC] = 0x01; - base_addr = CONFIG_SMC911X_BASE; - - /* Ethernet needs data bus width of 16 bits */ - if (config.width != 2) { - debug("%s: Unsupported bus width %d\n", __func__, - config.width); - return -1; - } - smc_bw_conf = SROMC_DATA16_WIDTH(config.bank) - | SROMC_BYTE_ENABLE(config.bank); - - smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |\ - SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\ - SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\ - SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\ - SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |\ - SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\ - SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); - - /* Select and configure the SROMC bank */ - exynos_pinmux_config(PERIPH_ID_SROMC, config.bank); - s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf); - return smc911x_initialize(0, base_addr); -#endif - return 0; -} - -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - printf("\nBoard: SMDK5250\n"); - return 0; -} -#endif - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - int err, ret = 0, index, bus_width; - u32 base; - - err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); - if (err) - debug("SDMMC0 not configured\n"); - ret |= err; - - /*EMMC: dwmmc Channel-0 with 8 bit bus width */ - index = 0; - base = samsung_get_base_mmc() + (0x10000 * index); - bus_width = 8; - err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL); - if (err) - debug("dwmmc Channel-0 init failed\n"); - ret |= err; - - err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); - if (err) - debug("SDMMC2 not configured\n"); - ret |= err; - - /*SD: dwmmc Channel-2 with 4 bit bus width */ - index = 2; - base = samsung_get_base_mmc() + (0x10000 * index); - bus_width = 4; - err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL); - if (err) - debug("dwmmc Channel-2 init failed\n"); - ret |= err; - - return ret; -} -#endif - -void board_i2c_init(const void *blob) -{ - int i; - - for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) { - exynos_pinmux_config((PERIPH_ID_I2C0 + i), - PINMUX_FLAG_NONE); - } -} - -#if defined(CONFIG_POWER) -#ifdef CONFIG_POWER_MAX77686 -static int pmic_reg_update(struct pmic *p, int reg, uint regval) -{ - u32 val; - int ret = 0; - - ret = pmic_reg_read(p, reg, &val); - if (ret) { - debug("%s: PMIC %d register read failed\n", __func__, reg); - return -1; - } - val |= regval; - ret = pmic_reg_write(p, reg, val); - if (ret) { - debug("%s: PMIC %d register write failed\n", __func__, reg); - return -1; - } - return 0; -} - -static int max77686_init(void) -{ - struct pmic *p; - - if (pmic_init(I2C_PMIC)) - return -1; - - p = pmic_get("MAX77686_PMIC"); - if (!p) - return -ENODEV; - - if (pmic_probe(p)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, - MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) - return -1; - - /* VDD_MIF */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, - MAX77686_BUCK1OUT_1V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK1OUT); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, - MAX77686_BUCK1CTRL_EN)) - return -1; - - /* VDD_ARM */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, - MAX77686_BUCK2DVS1_1_3V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK2DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, - MAX77686_BUCK2CTRL_ON)) - return -1; - - /* VDD_INT */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, - MAX77686_BUCK3DVS1_1_0125V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK3DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_G3D */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, - MAX77686_BUCK4DVS1_1_2V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK4DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_LDO2 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, - MAX77686_LD02CTRL1_1_5V | EN_LDO)) - return -1; - - /* VDD_LDO3 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, - MAX77686_LD03CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO5 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, - MAX77686_LD05CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO10 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, - MAX77686_LD10CTRL1_1_8V | EN_LDO)) - return -1; - - return 0; -} -#endif /* CONFIG_POWER_MAX77686 */ - -int exynos_power_init(void) -{ - int ret = 0; - -#ifdef CONFIG_POWER_MAX77686 - ret = max77686_init(); -#endif - return ret; -} -#endif /* CONFIG_POWER */ - -#ifdef CONFIG_LCD -void exynos_cfg_lcd_gpio(void) -{ - - /* For Backlight */ - gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT); - gpio_set_value(EXYNOS5_GPIO_B20, 1); - - /* LCD power on */ - gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT); - gpio_set_value(EXYNOS5_GPIO_X15, 1); - - /* Set Hotplug detect for DP */ - gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3)); -} - -void exynos_set_dp_phy(unsigned int onoff) -{ - set_dp_phy_ctrl(onoff); -} - -vidinfo_t panel_info = { - .vl_freq = 60, - .vl_col = 2560, - .vl_row = 1600, - .vl_width = 2560, - .vl_height = 1600, - .vl_clkp = CONFIG_SYS_LOW, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_LOW, - .vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */ - - /* wDP panel timing infomation */ - .vl_hspw = 32, - .vl_hbpd = 80, - .vl_hfpd = 48, - - .vl_vspw = 6, - .vl_vbpd = 37, - .vl_vfpd = 3, - .vl_cmd_allow_len = 0xf, - - .win_id = 3, - .dual_lcd_enabled = 0, - - .init_delay = 0, - .power_on_delay = 0, - .reset_delay = 0, - .interface_mode = FIMD_RGB_INTERFACE, - .dp_enabled = 1, -}; - -static struct edp_device_info edp_info = { - .disp_info = { - .h_res = 2560, - .h_sync_width = 32, - .h_back_porch = 80, - .h_front_porch = 48, - .v_res = 1600, - .v_sync_width = 6, - .v_back_porch = 37, - .v_front_porch = 3, - .v_sync_rate = 60, - }, - .lt_info = { - .lt_status = DP_LT_NONE, - }, - .video_info = { - .master_mode = 0, - .bist_mode = DP_DISABLE, - .bist_pattern = NO_PATTERN, - .h_sync_polarity = 0, - .v_sync_polarity = 0, - .interlaced = 0, - .color_space = COLOR_RGB, - .dynamic_range = VESA, - .ycbcr_coeff = COLOR_YCBCR601, - .color_depth = COLOR_8, - }, -}; - -static struct exynos_dp_platform_data dp_platform_data = { - .edp_dev_info = &edp_info, -}; - -void init_panel_info(vidinfo_t *vid) -{ - vid->rgb_mode = MODE_RGB_P; - exynos_set_dp_platform_data(&dp_platform_data); -} -#endif diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index 9207522953..183c52248a 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -42,9 +42,6 @@ int exynos_init(void) #ifdef CONFIG_LCD void cfg_lcd_gpio(void) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1(); - /* For Backlight */ gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_OUTPUT); gpio_set_value(EXYNOS5420_GPIO_B20, 1); diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index fec72d4c54..3dd340b7d8 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -332,7 +332,7 @@ int exynos_power_init(void) if (!p_chrg->chrg->chrg_bat_present(p_chrg)) { puts("No battery detected\n"); - return -1; + return 0; } p_fg->fg->fg_battery_check(p_fg, p_bat); diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index e4987ce8b4..fa26e61244 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -214,7 +214,7 @@ int exynos_power_init(void) if (!p_chrg->chrg->chrg_bat_present(p_chrg)) { puts("No battery detected\n"); - return -1; + return 0; } p_fg->fg->fg_battery_check(p_fg, p_bat); diff --git a/board/sheldon/simpc8313/Makefile b/board/sheldon/simpc8313/Makefile deleted file mode 100644 index a824c41d9c..0000000000 --- a/board/sheldon/simpc8313/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := simpc8313.o sdram.o diff --git a/board/sheldon/simpc8313/README.simpc8313 b/board/sheldon/simpc8313/README.simpc8313 deleted file mode 100644 index b362c6aeea..0000000000 --- a/board/sheldon/simpc8313/README.simpc8313 +++ /dev/null @@ -1,80 +0,0 @@ -Sheldon Instruments SIMPC8313 Board ------------------------------------------ - -1. Board Switches and Jumpers - - S2 is used to set CFG_RESET_SOURCE. - - To boot the image in Large page NAND flash, use these DIP - switch settings for S2: - - +----------+ ON - | * * **** | - | * * | - +----------+ - 12345678 - - To boot the image in Small page NAND flash, use these DIP - switch settings for S2: - - +----------+ ON - | *** **** | - | * | - +----------+ - 12345678 - (where the '*' indicates the position of the tab of the switch.) - -2. Memory Map - The memory map looks like this: - - 0x0000_0000 0x1fff_ffff DDR 512M - 0x8000_0000 0x8fff_ffff PCI MEM 256M - 0x9000_0000 0x9fff_ffff PCI_MMIO 256M - 0xe000_0000 0xe00f_ffff IMMR 1M - 0xe200_0000 0xe20f_ffff PCI IO 16M - 0xe280_0000 0xe280_7fff NAND FLASH (CS0) 32K - or - 0xe280_0000 0xe281_ffff NAND FLASH (CS0) 128K - 0xff00_0000 0xff00_7fff FPGA (CS1) 1M - -3. Compilation - - Assuming you're using BASH (or similar) as your shell: - - export CROSS_COMPILE=your-cross-compiler-prefix- - make distclean - make SIMPC8313_LP_config - (or make SIMPC8313_SP_config, depending on the page size - of your NAND flash) - make - -4. Downloading and Flashing Images - -4.1 Reflash U-boot Image using U-boot - - =>run update_uboot - - You may want to try - =>tftp $loadaddr $uboot - first, to make sure that the TFTP load will succeed before it - goes ahead and wipes out your current firmware. And of course, - if the new u-boot doesn't boot, you can plug the board into - your PCI slot and with the supplied driver and sample app - you can reburn a working u-boot. - -4.2 Downloading and Booting Linux Kernel - - Ensure that all networking-related environment variables are set - properly (including ipaddr, serverip, gatewayip (if needed), - netmask, ethaddr, eth1addr, fdtfile, and bootfile). - - =>tftp $loadaddr uImage - =>nand write $loadaddr kernel $filesize - =>tftp $loadaddr $fdtfile - =>nand write $loadaddr 7e0000 1800 - - =>boot - -5 Notes - - The console baudrate for SIMPC8313 is 115200bps. diff --git a/board/sheldon/simpc8313/sdram.c b/board/sheldon/simpc8313/sdram.c deleted file mode 100644 index 7c12fe851c..0000000000 --- a/board/sheldon/simpc8313/sdram.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 - * Copyright (C) Sheldon Instruments, Inc. 2008 - * - * Author: Ron Madrid <info@sheldoninst.com> - * - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc83xx.h> -#include <spd_sdram.h> -#include <asm/bitops.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <asm/mmu.h> - -DECLARE_GLOBAL_DATA_PTR; - -static long fixed_sdram(void); - -#if defined(CONFIG_NAND_SPL) -void si_wait_i2c(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - - while (!(__raw_readb(&im->i2c[0].sr) & 0x02)) - ; - - __raw_writeb(0x00, &im->i2c[0].sr); - - sync(); - - return; -} - -void si_read_i2c(u32 lbyte, int count, u8 *buffer) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 i; - u8 chip = 0x50 << 1; /* boot sequencer I2C */ - u32 ubyte = (lbyte & 0xff00) >> 8; - - lbyte &= 0xff; - - /* - * Set up controller - */ - __raw_writeb(0x3f, &im->i2c[0].fdr); - __raw_writeb(0x00, &im->i2c[0].adr); - __raw_writeb(0x00, &im->i2c[0].sr); - __raw_writeb(0x00, &im->i2c[0].dr); - - while (__raw_readb(&im->i2c[0].sr) & 0x20) - ; - - /* - * Writing address to device - */ - __raw_writeb(0xb0, &im->i2c[0].cr); - sync(); - __raw_writeb(chip, &im->i2c[0].dr); - si_wait_i2c(); - - __raw_writeb(0xb0, &im->i2c[0].cr); - sync(); - __raw_writeb(ubyte, &im->i2c[0].dr); - si_wait_i2c(); - - __raw_writeb(lbyte, &im->i2c[0].dr); - si_wait_i2c(); - - __raw_writeb(0xb4, &im->i2c[0].cr); - sync(); - __raw_writeb(chip + 1, &im->i2c[0].dr); - si_wait_i2c(); - - __raw_writeb(0xa0, &im->i2c[0].cr); - sync(); - - /* - * Dummy read - */ - __raw_readb(&im->i2c[0].dr); - - si_wait_i2c(); - - /* - * Read actual data - */ - for (i = 0; i < count; i++) - { - if (i == (count - 2)) /* Reached next to last byte, No ACK */ - __raw_writeb(0xa8, &im->i2c[0].cr); - if (i == (count - 1)) /* Reached last byte, STOP */ - __raw_writeb(0x88, &im->i2c[0].cr); - - /* Read byte of data */ - buffer[i] = __raw_readb(&im->i2c[0].dr); - - if (i == (count - 1)) - break; - si_wait_i2c(); - } - - return; -} -#endif /* CONFIG_NAND_SPL */ - -phys_size_t initdram(int board_type) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile fsl_lbc_t *lbc = &im->im_lbc; - u32 msize; - - if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im) - return -1; - - /* DDR SDRAM - Main SODIMM */ - __raw_writel(CONFIG_SYS_DDR_BASE & LAWBAR_BAR, &im->sysconf.ddrlaw[0].bar); - - msize = fixed_sdram(); - - /* Local Bus setup lbcr and mrtpr */ - __raw_writel(CONFIG_SYS_LBC_LBCR, &lbc->lbcr); - __raw_writel(CONFIG_SYS_LBC_MRTPR, &lbc->mrtpr); - sync(); - - /* return total bus SDRAM size(bytes) -- DDR */ - return (msize * 1024 * 1024); -} - -/************************************************************************* - * fixed sdram init -- reads values from boot sequencer I2C - ************************************************************************/ -static long fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msizelog2, msize = 1; -#if defined(CONFIG_NAND_SPL) - u32 i; - const u8 bytecount = 135; - u8 buffer[bytecount]; - u32 addr, data; - - si_read_i2c(0, bytecount, buffer); - - for (i = 18; i < bytecount; i += 7){ - addr = (u32)buffer[i]; - addr <<= 8; - addr |= (u32)buffer[i + 1]; - addr <<= 2; - data = (u32)buffer[i + 2]; - data <<= 8; - data |= (u32)buffer[i + 3]; - data <<= 8; - data |= (u32)buffer[i + 4]; - data <<= 8; - data |= (u32)buffer[i + 5]; - - __raw_writel(data, (u32 *)(CONFIG_SYS_IMMR + addr)); - } - - sync(); - - /* enable DDR controller */ - __raw_writel((__raw_readl(&im->ddr.sdram_cfg) | SDRAM_CFG_MEM_EN), &im->ddr.sdram_cfg); -#endif /* (CONFIG_NAND_SPL) */ - - msizelog2 = ((__raw_readl(&im->sysconf.ddrlaw[0].ar) & LAWAR_SIZE) + 1); - msize <<= (msizelog2 - 20); - - return msize; -} diff --git a/board/sheldon/simpc8313/simpc8313.c b/board/sheldon/simpc8313/simpc8313.c deleted file mode 100644 index 31406fa66d..0000000000 --- a/board/sheldon/simpc8313/simpc8313.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 - * Copyright (C) Sheldon Instruments, Inc. 2008 - * - * Author: Ron Madrid <info@sheldoninst.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <libfdt.h> -#include <pci.h> -#include <mpc83xx.h> -#include <ns16550.h> -#include <nand.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_NAND_SPL -int checkboard(void) -{ - puts("Board: Sheldon Instruments SIMPC8313\n"); - return 0; -} - -static struct pci_region pci_regions[] = { - { - bus_start: CONFIG_SYS_PCI1_MEM_BASE, - phys_start: CONFIG_SYS_PCI1_MEM_PHYS, - size: CONFIG_SYS_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI1_MMIO_BASE, - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, - size: CONFIG_SYS_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, - { - bus_start: CONFIG_SYS_PCI1_IO_BASE, - phys_start: CONFIG_SYS_PCI1_IO_PHYS, - size: CONFIG_SYS_PCI1_IO_SIZE, - flags: PCI_REGION_IO - } -}; - -void pci_init_board(void) -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - struct pci_region *reg[] = { pci_regions }; - - /* Enable all 3 PCI_CLK_OUTPUTs. */ - clk->occr |= 0xe0000000; - - /* - * Configure PCI Local Access Windows - */ - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - mpc83xx_pci_init(1, reg); -} - -/* - * Miscellaneous late-boot configurations - */ -int misc_init_r(void) -{ - int rc = 0; - immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - fsl_lbc_t *lbus = &immap->im_lbc; - u32 *mxmr = &lbus->mamr; /* Pointer to mamr */ - - /* UPM Table Configuration Code */ - static uint UPMATable[] = { - /* Read Single-Beat (RSS) */ - 0x0fff0c00, 0x0fffdc00, 0x0fff0c05, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - /* Read Burst (RBS) */ - 0x0fff0c00, 0x0ffcdc00, 0x0ffc0c00, 0x0ffc0f0c, - 0x0ffccf0c, 0x0ffc0f0c, 0x0ffcce0c, 0x3ffc0c05, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - /* Write Single-Beat (WSS) */ - 0x0ffc0c00, 0x0ffcdc00, 0x0ffc0c05, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - /* Write Burst (WBS) */ - 0x0ffc0c00, 0x0fffcc0c, 0x0fff0c00, 0x0fffcc00, - 0x0fff1c00, 0x0fffcf0c, 0x0fff0f0c, 0x0fffcf0c, - 0x0fff0c0c, 0x0fffcc0c, 0x0fff0c05, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - /* Refresh Timer (RTS) */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - /* Exception Condition (EXS) */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 - }; - - upmconfig(UPMA, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); - - /* Set LUPWAIT to be active low and enabled */ - out_be32(mxmr, MxMR_UWPL | MxMR_GPL_x4DIS); - - return rc; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif -} -#endif -#else /* CONFIG_NAND_SPL */ -void board_init_f(ulong bootflag) -{ - NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); - puts("NAND boot... "); - init_timebase(); - initdram(0); - relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd, - CONFIG_SYS_NAND_U_BOOT_RELOC); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - nand_boot(); -} - -void putc(char c) -{ - if (gd->flags & GD_FLG_SILENT) - return; - - if (c == '\n') - NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r'); - - NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c); -} -#endif diff --git a/board/snmc/qs850/Makefile b/board/snmc/qs850/Makefile deleted file mode 100644 index 5867d900b7..0000000000 --- a/board/snmc/qs850/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = qs850.o flash.o diff --git a/board/snmc/qs850/flash.c b/board/snmc/qs850/flash.c deleted file mode 100644 index 2fc23f2f1d..0000000000 --- a/board/snmc/qs850/flash.c +++ /dev/null @@ -1,600 +0,0 @@ -/* - * (C) Copyright 2003 - * MuLogic B.V. - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/u-boot.h> -#include <asm/processor.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -#define FLASH_WORD_SIZE unsigned long -#define FLASH_ID_MASK 0xFFFFFFFF - -/*----------------------------------------------------------------------- - * Functions - */ -/* stolen from esteem192e/flash.c */ -ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info); - -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - volatile FLASH_WORD_SIZE* flash_base; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here */ - /* Test for 8M Flash first */ - debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_8M_PRELIM); - flash_base = (volatile FLASH_WORD_SIZE*)(FLASH_BASE0_8M_PRELIM); - size_b0 = flash_get_size(flash_base, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - return 0; - } - - if (size_b0 < 8*1024*1024) { - /* Not quite 8M, try 4M Flash base address */ - debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_4M_PRELIM); - flash_base = (volatile FLASH_WORD_SIZE*)(FLASH_BASE0_4M_PRELIM); - size_b0 = flash_get_size(flash_base, &flash_info[0]); - } - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - return 0; - } - - /* Only one bank */ - if (CONFIG_SYS_MAX_FLASH_BANKS == 1) { - /* Setup offsets */ - flash_get_offsets ((ulong)flash_base, &flash_info[0]); - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, &flash_info[0]); - size_b1 = 0 ; - flash_info[0].size = size_b0; - return(size_b0); - } - - /* We have 2 banks */ - size_b1 = flash_get_size(flash_base, &flash_info[1]); - - /* Re-do sizing to get full correct info */ - if (size_b1) { - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB0CR); - base_b1 = -size_b1; - pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17); - mtdcr(EBC0_CFGDATA, pbcr); - } - - if (size_b0) { - mtdcr(EBC0_CFGADDR, PB1CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB1CR); - base_b0 = base_b1 - size_b0; - pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(EBC0_CFGDATA, pbcr); - } - - size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]); - flash_get_offsets (base_b0, &flash_info[0]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, &flash_info[0]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b1, &flash_info[1]); - flash_get_offsets (base_b1, &flash_info[1]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, base_b1+size_b1-CONFIG_SYS_MONITOR_LEN, - base_b1+size_b1-1, &flash_info[1]); - - /* monitor protection OFF by default (one is enough) */ - (void)flash_protect(FLAG_PROTECT_CLEAR, base_b0+size_b0-CONFIG_SYS_MONITOR_LEN, - base_b0+size_b0-1, &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - return (size_b0 + size_b1); -} - - -/*----------------------------------------------------------------------- - This code is specific to the AM29DL163/AM29DL232 for the QS850/QS823. - */ - -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - long large_sect_size; - long small_sect_size; - - /* set up sector start adress table */ - large_sect_size = info->size / (info->sector_count - 8 + 1); - small_sect_size = large_sect_size / 8; - - if (info->flash_id & FLASH_BTYPE) { - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 7; i++) { - info->start[i] = base; - base += small_sect_size; - } - - for (; i < info->sector_count; i++) { - info->start[i] = base; - base += large_sect_size; - } - } - else - { - /* set sector offsets for top boot block type */ - for (i = 0; i < (info->sector_count - 8); i++) { - info->start[i] = base; - base += large_sect_size; - } - - for (; i < info->sector_count; i++) { - info->start[i] = base; - base += small_sect_size; - } - } -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar botboot[]=", bottom boot sect)\n"; - uchar topboot[]=", top boot sector)\n"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_SST: - printf ("SST "); - break; - case FLASH_MAN_STM: - printf ("STM "); - break; - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - if (info->flash_id & 0x0001 ) { - boottype = botboot; - } else { - boottype = topboot; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit%s",boottype); - break; - case FLASH_AM160T: - printf ("AM29LV160T (16 Mbit%s",boottype); - break; - case FLASH_AMDL163T: - printf ("AM29DL163T (16 Mbit%s",boottype); - break; - case FLASH_AMDL163B: - printf ("AM29DL163B (16 Mbit%s",boottype); - break; - case FLASH_AM320B: - printf ("AM29LV320B (32 Mbit%s",boottype); - break; - case FLASH_AM320T: - printf ("AM29LV320T (32 Mbit%s",boottype); - break; - case FLASH_AMDL323T: - printf ("AM29DL323T (32 Mbit%s",boottype); - break; - case FLASH_AMDL323B: - printf ("AM29DL323B (32 Mbit%s",boottype); - break; - case FLASH_AMDL322T: - printf ("AM29DL322T (32 Mbit%s",boottype); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - - -/*----------------------------------------------------------------------- - * The following code cannot be run from FLASH! - */ -ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info) -{ - short i; - ulong base = (ulong)addr; - FLASH_WORD_SIZE value; - - /* Write auto select command: read Manufacturer ID */ - - /* - * Note: if it is an AMD flash and the word at addr[0000] - * is 0x00890089 this routine will think it is an Intel - * flash device and may(most likely) cause trouble. - */ - - addr[0x0000] = 0x00900090; - if(addr[0x0000] != 0x00890089){ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - } - value = addr[0]; - - switch (value) { - case (AMD_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_FUJ; - break; - case (STM_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_STM; - break; - case (SST_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_SST; - break; - case (INTEL_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case (AMD_ID_LV160T & FLASH_ID_MASK): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV160B & FLASH_ID_MASK): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_DL163T & FLASH_ID_MASK): - info->flash_id += FLASH_AMDL163T; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_DL163B & FLASH_ID_MASK): - info->flash_id += FLASH_AMDL163B; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_DL323T & FLASH_ID_MASK): - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (AMD_ID_DL323B & FLASH_ID_MASK): - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (AMD_ID_DL322T & FLASH_ID_MASK): - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - default: - /* FIXME*/ - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets(base, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile FLASH_WORD_SIZE *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile FLASH_WORD_SIZE *)info->start[0]; - *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP) ) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]); - addr[0] = (0x00300030 & FLASH_ID_MASK); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]); - while ((addr[0] & (0x00800080&FLASH_ID_MASK)) != - (0x00800080&FLASH_ID_MASK) ) - { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int l; - int i, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* AMD stuff */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - - return (0); -} diff --git a/board/snmc/qs850/qs850.c b/board/snmc/qs850/qs850.c deleted file mode 100644 index dc4a4768cd..0000000000 --- a/board/snmc/qs850/qs850.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * (C) Copyright 2003 - * MuLogic B.V. - * - * (C) Copyright 2002 - * Simple Network Magic Corporation, dnevil@snmc.com - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/u-boot.h> -#include <commproc.h> -#include "mpc8xx.h" - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x0f07cc04, 0x00adcc04, 0x00a74c00, 0x00bfcc04, - 0x1fffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x0ff7fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00, - 0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05, - 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, - 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x0f07cc04, 0x0fafcc00, 0x01ad0c04, 0x1ff74c07, - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x0ff7fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00, - 0x00fffc00, 0x00fffc00, 0x0ffffc04, 0x0ff77c04, - 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, - 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0xffffcc04, 0x1ff5cc84, 0xffffcc04, 0xffffcc04, - 0xffffcc84, 0xffffcc05, 0xffffcc04, 0xffffcc04, - 0xffffcc04, 0xffffcc04, 0xffffcc04, 0xffffcc04, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x1ff74c04, 0xffffcc07, 0xffffaa34, 0x1fb54a37 -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Test ID string (QS850, QS823, ...) - * - * Always return 1 - */ -#if defined(CONFIG_QS850) -#define BOARD_IDENTITY "QS850" -#elif defined(CONFIG_QS823) -#define BOARD_IDENTITY "QS823" -#else -#define BOARD_IDENTITY "QS???" -#endif - -int checkboard (void) -{ - char *s, *e; - char buf[64]; - int i; - - i = getenv_f("serial#", buf, sizeof(buf)); - s = (i>0) ? buf : NULL; - - if (!s || strncmp(s, BOARD_IDENTITY, 5)) { - puts ("### No HW ID - assuming " BOARD_IDENTITY); - } else { - for (e=s; *e; ++e) { - if (*e == ' ') - break; - } - - for ( ; s<e; ++s) { - putc (*s); - } - } - putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ -/* SDRAM Mode Register Definitions */ - -/* Set SDRAM Burst Length to 4 (010) */ -/* See Motorola MPC850 User Manual, Page 13-14 */ -#define SDRAM_BURST_LENGTH (2) - -/* Set Wrap Type to Sequential (0) */ -/* See Motorola MPC850 User Manual, Page 13-14 */ -#define SDRAM_WRAP_TYPE (0 << 3) - -/* Set /CAS Latentcy to 2 clocks */ -#define SDRAM_CAS_LATENTCY (2 << 4) - -/* The Mode Register value must be shifted left by 2, since it is */ -/* placed on the address bus, and the 2 LSBs are ignored for 32-bit accesses */ -#define SDRAM_MODE_REG ((SDRAM_BURST_LENGTH|SDRAM_WRAP_TYPE|SDRAM_CAS_LATENTCY) << 2) - -#define UPMA_RUN(loops,index) (0x80002000 + (loops<<8) + index) - -/* Please note a value of zero = 16 loops */ -#define REFRESH_INIT_LOOPS (0) - - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size; - - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* - * Prescaler for refresh - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - /* - * Map controller bank 1 to the SDRAM address - */ - memctl->memc_or1 = CONFIG_SYS_OR1; - memctl->memc_br1 = CONFIG_SYS_BR1; - udelay(1000); - - /* perform SDRAM initialization sequence */ - memctl->memc_mamr = CONFIG_SYS_16M_MAMR; - udelay(100); - - /* Program the SDRAM's Mode Register */ - memctl->memc_mar = SDRAM_MODE_REG; - - /* Run the Prechard Pattern at 0x3C */ - memctl->memc_mcr = UPMA_RUN(1,0x3c); - udelay(1); - - /* Run the Refresh program residing at MAD index 0x30 */ - /* This contains the CBR Refresh command with a loop */ - /* The SDRAM must be refreshed at least 2 times */ - /* Please note a value of zero = 16 loops */ - memctl->memc_mcr = UPMA_RUN(REFRESH_INIT_LOOPS,0x30); - udelay(1); - - /* Run the Exception program residing at MAD index 0x3E */ - /* This contains the Write Mode Register command */ - /* The Write Mode Register command uses the value written to MAR */ - memctl->memc_mcr = UPMA_RUN(1,0x3e); - - udelay (1000); - - /* - * Check for 32M SDRAM Memory Size - */ - size = dram_size(CONFIG_SYS_32M_MAMR|MAMR_PTAE, - (long *)SDRAM_BASE, SDRAM_32M_MAX_SIZE); - udelay (1000); - - /* - * Check for 16M SDRAM Memory Size - */ - if (size != SDRAM_32M_MAX_SIZE) { - size = dram_size(CONFIG_SYS_16M_MAMR|MAMR_PTAE, - (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE); - udelay (1000); - } - - udelay(10000); - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} diff --git a/board/snmc/qs850/u-boot.lds b/board/snmc/qs850/u-boot.lds deleted file mode 100644 index 667dc54e17..0000000000 --- a/board/snmc/qs850/u-boot.lds +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/snmc/qs860t/Makefile b/board/snmc/qs860t/Makefile deleted file mode 100644 index 802f67e384..0000000000 --- a/board/snmc/qs860t/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = qs860t.o flash.o diff --git a/board/snmc/qs860t/flash.c b/board/snmc/qs860t/flash.c deleted file mode 100644 index c24d9792de..0000000000 --- a/board/snmc/qs860t/flash.c +++ /dev/null @@ -1,1099 +0,0 @@ -/* - * (C) Copyright 2003 - * MuLogic B.V. - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/u-boot.h> -#include <asm/processor.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -#ifdef CONFIG_SYS_FLASH_16BIT -#define FLASH_WORD_SIZE unsigned short -#define FLASH_ID_MASK 0xFFFF -#else -#define FLASH_WORD_SIZE unsigned long -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -/* stolen from esteem192e/flash.c */ -ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info); - -#ifndef CONFIG_SYS_FLASH_16BIT -static int write_word (flash_info_t *info, ulong dest, ulong data); -#else -static int write_short (flash_info_t *info, ulong dest, ushort data); -#endif -static void flash_get_offsets (ulong base, flash_info_t *info); - - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Only one bank */ - if (CONFIG_SYS_MAX_FLASH_BANKS == 1) { - /* Setup offsets */ - flash_get_offsets (FLASH_BASE1_PRELIM, &flash_info[0]); - - /* Monitor protection ON by default */ -#if 0 /* sand: */ - (void)flash_protect(FLAG_PROTECT_SET, - FLASH_BASE1_PRELIM-CONFIG_SYS_MONITOR_LEN+size_b0, - FLASH_BASE1_PRELIM-1+size_b0, - &flash_info[0]); -#else - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, - &flash_info[0]); -#endif - size_b1 = 0 ; - flash_info[0].size = size_b0; - } else { /* 2 banks */ - size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM, &flash_info[1]); - - /* Re-do sizing to get full correct info */ - if (size_b1) { - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB0CR); - base_b1 = -size_b1; - pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17); - mtdcr(EBC0_CFGDATA, pbcr); - } - - if (size_b0) { - mtdcr(EBC0_CFGADDR, PB1CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB1CR); - base_b0 = base_b1 - size_b0; - pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(EBC0_CFGDATA, pbcr); - } - - size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]); - - flash_get_offsets (base_b0, &flash_info[0]); - - /* monitor protection ON by default */ -#if 0 /* sand: */ - (void)flash_protect(FLAG_PROTECT_SET, - FLASH_BASE1_PRELIM-CONFIG_SYS_MONITOR_LEN+size_b0, - FLASH_BASE1_PRELIM-1+size_b0, - &flash_info[0]); -#else - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, - &flash_info[0]); -#endif - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b1, &flash_info[1]); - - flash_get_offsets (base_b1, &flash_info[1]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - base_b1+size_b1-CONFIG_SYS_MONITOR_LEN, - base_b1+size_b1-1, - &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - (void)flash_protect(FLAG_PROTECT_CLEAR, - base_b0+size_b0-CONFIG_SYS_MONITOR_LEN, - base_b0+size_b0-1, - &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - }/* else 2 banks */ - return (size_b0 + size_b1); -} - - -/*----------------------------------------------------------------------- - */ - -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start adress table */ - if ((info->flash_id & FLASH_TYPEMASK) == INTEL_ID_28F320J3A || - (info->flash_id & FLASH_TYPEMASK) == INTEL_ID_28F640J3A || - (info->flash_id & FLASH_TYPEMASK) == INTEL_ID_28F128J3A) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * info->size/info->sector_count); - } - } - else if (info->flash_id & FLASH_BTYPE) { - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - -#ifndef CONFIG_SYS_FLASH_16BIT - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00008000; - info->start[3] = base + 0x0000C000; - info->start[4] = base + 0x00010000; - info->start[5] = base + 0x00014000; - info->start[6] = base + 0x00018000; - info->start[7] = base + 0x0001C000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x000E0000; - } - } else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } -#else - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00002000; - info->start[2] = base + 0x00004000; - info->start[3] = base + 0x00006000; - info->start[4] = base + 0x00008000; - info->start[5] = base + 0x0000A000; - info->start[6] = base + 0x0000C000; - info->start[7] = base + 0x0000E000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00070000; - } - } else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } -#endif - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - -#ifndef CONFIG_SYS_FLASH_16BIT - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00014000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x0001C000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } else { - - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#else - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000A000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x0000E000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } else { - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } -#endif - } -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar botboot[]=", bottom boot sect)\n"; - uchar topboot[]=", top boot sector)\n"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - if (info->flash_id & 0x0001 ) { - boottype = botboot; - } else { - boottype = topboot; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit%s",boottype); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit%s",boottype); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit%s",boottype); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit%s",boottype); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit%s",boottype); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit%s",boottype); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit%s",boottype); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit%s",boottype); - break; - case FLASH_INTEL800B: printf ("INTEL28F800B (8 Mbit%s",boottype); - break; - case FLASH_INTEL800T: printf ("INTEL28F800T (8 Mbit%s",boottype); - break; - case FLASH_INTEL160B: printf ("INTEL28F160B (16 Mbit%s",boottype); - break; - case FLASH_INTEL160T: printf ("INTEL28F160T (16 Mbit%s",boottype); - break; - case FLASH_INTEL320B: printf ("INTEL28F320B (32 Mbit%s",boottype); - break; - case FLASH_INTEL320T: printf ("INTEL28F320T (32 Mbit%s",boottype); - break; - case FLASH_AMDL322T: printf ("AM29DL322T (32 Mbit%s",boottype); - break; - -#if 0 /* enable when devices are available */ - - case FLASH_INTEL640B: printf ("INTEL28F640B (64 Mbit%s",boottype); - break; - case FLASH_INTEL640T: printf ("INTEL28F640T (64 Mbit%s",boottype); - break; -#endif - case INTEL_ID_28F320J3A: printf ("INTEL28F320JA3 (32 Mbit%s",boottype); - break; - case INTEL_ID_28F640J3A: printf ("INTEL28F640JA3 (64 Mbit%s",boottype); - break; - case INTEL_ID_28F128J3A: printf ("INTEL28F128JA3 (128 Mbit%s",boottype); - break; - - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info) -{ - short i; - ulong base = (ulong)addr; - FLASH_WORD_SIZE value; - - /* Write auto select command: read Manufacturer ID */ - - -#ifndef CONFIG_SYS_FLASH_16BIT - - /* - * Note: if it is an AMD flash and the word at addr[0000] - * is 0x00890089 this routine will think it is an Intel - * flash device and may(most likely) cause trouble. - */ - - addr[0x0000] = 0x00900090; - if(addr[0x0000] != 0x00890089){ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; -#else - - /* - * Note: if it is an AMD flash and the word at addr[0000] - * is 0x0089 this routine will think it is an Intel - * flash device and may(most likely) cause trouble. - */ - - addr[0x0000] = 0x0090; - - if(addr[0x0000] != 0x0089){ - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x0090; -#endif - } - value = addr[0]; - - switch (value) { - case (AMD_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_FUJ; - break; - case (STM_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_STM; - break; - case (SST_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_SST; - break; - case (INTEL_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - - } - - value = addr[1]; /* device ID */ - - switch (value) { - - case (AMD_ID_LV400T & FLASH_ID_MASK): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV400B & FLASH_ID_MASK): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800T & FLASH_ID_MASK): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV800B & FLASH_ID_MASK): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160T & FLASH_ID_MASK): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV160B & FLASH_ID_MASK): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & FLASH_ID_MASK): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (AMD_ID_LV320B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - - case (AMD_ID_DL322T & FLASH_ID_MASK): - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (INTEL_ID_28F800B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL800T; - info->sector_count = 23; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (INTEL_ID_28F800B3B & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (INTEL_ID_28F160B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL160T; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (INTEL_ID_28F160B3B & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (INTEL_ID_28F320B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL320T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (INTEL_ID_28F320B3B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - -#if 0 /* enable when devices are available */ - case (INTEL_ID_28F320B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL320T; - info->sector_count = 135; - info->size = 0x01000000; - break; /* => 16 MB */ - - case (INTEL_ID_28F320B3B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 135; - info->size = 0x01000000; - break; /* => 16 MB */ -#endif - case (INTEL_ID_28F320J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 32 MBit */ - case (INTEL_ID_28F640J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 64 MBit */ - case (INTEL_ID_28F128J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 128 MBit */ - - default: - /* FIXME*/ - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets(base, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile FLASH_WORD_SIZE *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile FLASH_WORD_SIZE *)info->start[0]; - if( (info->flash_id & 0xFF00) == FLASH_MAN_INTEL){ - *addr = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ - } else { - *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ - } - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - - volatile FLASH_WORD_SIZE *addr = - (volatile FLASH_WORD_SIZE *) (info->start[0]); - int flag, prot, sect, l_sect, barf; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - ((info->flash_id > FLASH_AMD_COMP) && - ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL))) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - if (info->flash_id < FLASH_AMD_COMP) { -#ifndef CONFIG_SYS_FLASH_16BIT - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; -#else - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x0080; - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; -#endif - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (volatile FLASH_WORD_SIZE *) (info->start[sect]); - addr[0] = (0x00300030 & FLASH_ID_MASK); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]); - while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) != - (0x00800080 & FLASH_ID_MASK)) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ - } else { - - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - barf = 0; -#ifndef CONFIG_SYS_FLASH_16BIT - addr = (vu_long *) (info->start[sect]); - addr[0] = 0x00200020; - addr[0] = 0x00D000D0; - while (!(addr[0] & 0x00800080)); /* wait for error or finish */ - if (addr[0] & 0x003A003A) { /* check for error */ - barf = addr[0] & 0x003A0000; - if (barf) { - barf >>= 16; - } else { - barf = addr[0] & 0x0000003A; - } - } -#else - addr = (vu_short *) (info->start[sect]); - addr[0] = 0x0020; - addr[0] = 0x00D0; - while (!(addr[0] & 0x0080)); /* wait for error or finish */ - if (addr[0] & 0x003A) /* check for error */ - barf = addr[0] & 0x003A; -#endif - if (barf) { - printf ("\nFlash error in sector at %lx\n", - (unsigned long) addr); - if (barf & 0x0002) - printf ("Block locked, not erased.\n"); - if ((barf & 0x0030) == 0x0030) - printf ("Command Sequence error.\n"); - if ((barf & 0x0030) == 0x0020) - printf ("Block Erase error.\n"); - if (barf & 0x0008) - printf ("Vpp Low error.\n"); - rcode = 1; - } else - printf ("."); - l_sect = sect; - } - addr = (volatile FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ - - } - - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ - -/*flash_info_t *addr2info (ulong addr) -{ - flash_info_t *info; - int i; - - for (i=0, info=&flash_info[0]; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i, ++info) { - if ((addr >= info->start[0]) && - (addr < (info->start[0] + info->size)) ) { - return (info); - } - } - - return (NULL); -} -*/ -/*----------------------------------------------------------------------- - * Copy memory to flash. - * Make sure all target addresses are within Flash bounds, - * and no protected sectors are hit. - * Returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - target range includes protected sectors - * 8 - target address not in Flash memory - */ - -/*int flash_write (uchar *src, ulong addr, ulong cnt) -{ - int i; - ulong end = addr + cnt - 1; - flash_info_t *info_first = addr2info (addr); - flash_info_t *info_last = addr2info (end ); - flash_info_t *info; - - if (cnt == 0) { - return (0); - } - - if (!info_first || !info_last) { - return (8); - } - - for (info = info_first; info <= info_last; ++info) { - ulong b_end = info->start[0] + info->size;*/ /* bank end addr */ -/* short s_end = info->sector_count - 1; - for (i=0; i<info->sector_count; ++i) { - ulong e_addr = (i == s_end) ? b_end : info->start[i + 1]; - - if ((end >= info->start[i]) && (addr < e_addr) && - (info->protect[i] != 0) ) { - return (4); - } - } - } - -*/ /* finally write data to flash */ -/* for (info = info_first; info <= info_last && cnt>0; ++info) { - ulong len; - - len = info->start[0] + info->size - addr; - if (len > cnt) - len = cnt; - if ((i = write_buff(info, src, addr, len)) != 0) { - return (i); - } - cnt -= len; - addr += len; - src += len; - } - return (0); -} -*/ -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ -#ifndef CONFIG_SYS_FLASH_16BIT - ulong cp, wp, data; - int l; -#else - ulong cp, wp; - ushort data; -#endif - int i, rc; - -#ifndef CONFIG_SYS_FLASH_16BIT - - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); - -#else - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start byte - */ - if (addr - wp) { - data = 0; - data = (data << 8) | *src++; - --cnt; - if ((rc = write_short(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ -/* l = 0; used for debuging */ - while (cnt >= 2) { - data = 0; - for (i=0; i<2; ++i) { - data = (data << 8) | *src++; - } - -/* if(!l){ - printf("%x",data); - l = 1; - } used for debuging */ - - if ((rc = write_short(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<2; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_short(info, wp, data)); - - -#endif -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -#ifndef CONFIG_SYS_FLASH_16BIT -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start,barf; - int flag; - - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - if(info->flash_id > FLASH_AMD_COMP) { - /* AMD stuff */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - } else { - /* intel stuff */ - *addr = 0x00400040; - } - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - - if(info->flash_id > FLASH_AMD_COMP) { - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } else { - while(!(addr[0] & 0x00800080)) { /* wait for error or finish */ - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - - if( addr[0] & 0x003A003A) { /* check for error */ - barf = addr[0] & 0x003A0000; - if( barf ) { - barf >>=16; - } else { - barf = addr[0] & 0x0000003A; - } - printf("\nFlash write error at address %lx\n",(unsigned long)dest); - if(barf & 0x0002) printf("Block locked, not erased.\n"); - if(barf & 0x0010) printf("Programming error.\n"); - if(barf & 0x0008) printf("Vpp Low error.\n"); - return(2); - } - } - - return (0); -} - -#else - -static int write_short (flash_info_t *info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short*)(info->start[0]); - ulong start,barf; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_short *)dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - if(info->flash_id < FLASH_AMD_COMP) { - /* AMD stuff */ - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x00A0; - } else { - /* intel stuff */ - *addr = 0x00D0; - *addr = 0x0040; - } - *((vu_short *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - - if(info->flash_id < FLASH_AMD_COMP) { - /* AMD stuff */ - while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - - } else { - /* intel stuff */ - while(!(addr[0] & 0x0080)){ /* wait for error or finish */ - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); - } - - if( addr[0] & 0x003A) { /* check for error */ - barf = addr[0] & 0x003A; - printf("\nFlash write error at address %lx\n",(unsigned long)dest); - if(barf & 0x0002) printf("Block locked, not erased.\n"); - if(barf & 0x0010) printf("Programming error.\n"); - if(barf & 0x0008) printf("Vpp Low error.\n"); - return(2); - } - *addr = 0x00B0; - *addr = 0x0070; - while(!(addr[0] & 0x0080)){ /* wait for error or finish */ - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); - } - *addr = 0x00FF; - } - return (0); -} - -#endif - -/*-----------------------------------------------------------------------*/ diff --git a/board/snmc/qs860t/qs860t.c b/board/snmc/qs860t/qs860t.c deleted file mode 100644 index 7ff99459b7..0000000000 --- a/board/snmc/qs860t/qs860t.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * (C) Copyright 2003 - * MuLogic B.V. - * - * (C) Copyright 2002 - * Simple Network Magic Corporation, dnevil@snmc.com - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/u-boot.h> -#include <commproc.h> -#include "mpc8xx.h" - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, - 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, - 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, - 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, 0xFFFFEC04, - 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, - 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, 0xFFFFEC04, 0xFFFFEC04, - 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04 -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Test ID string (QS860T...) - * - * Always return 1 - */ - -int checkboard (void) -{ - char *s, *e; - char buf[64]; - int i; - - i = getenv_f("serial#", buf, sizeof(buf)); - s = (i>0) ? buf : NULL; - - if (!s || strncmp(s, "QS860T", 6)) { - puts ("### No HW ID - assuming QS860T"); - } else { - for (e=s; *e; ++e) { - if (*e == ' ') - break; - } - - for ( ; s<e; ++s) { - putc (*s); - } - } - putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size; - - upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* - * Prescaler for refresh - */ - memctl->memc_mptpr = 0x0400; - - /* - * Map controller bank 2 to the SDRAM address - */ - memctl->memc_or2 = CONFIG_SYS_OR2; - memctl->memc_br2 = CONFIG_SYS_BR2; - udelay(200); - - /* perform SDRAM initialization sequence */ - memctl->memc_mbmr = CONFIG_SYS_16M_MBMR; - udelay(100); - - memctl->memc_mar = 0x00000088; - memctl->memc_mcr = 0x80804105; /* run precharge pattern */ - udelay(1); - - /* Run two refresh cycles on SDRAM */ - memctl->memc_mbmr = 0x18802118; - memctl->memc_mcr = 0x80804130; - memctl->memc_mbmr = 0x18802114; - memctl->memc_mcr = 0x80804106; - - udelay (1000); - -#if 0 - /* - * Check for 64M SDRAM Memory Size - */ - size = dram_size (CONFIG_SYS_64M_MBMR, (ulong *)SDRAM_BASE, SDRAM_64M_MAX_SIZE); - udelay (1000); - - /* - * Check for 16M SDRAM Memory Size - */ - if (size != SDRAM_64M_MAX_SIZE) { -#endif - size = dram_size (CONFIG_SYS_16M_MBMR, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE); - udelay (1000); -#if 0 - } - - memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING; -#endif - - - udelay(10000); - - -#if 0 - - /* - * Also, map other memory to correct position - */ - - /* - * Map the 8M Intel Flash device to chip select 1 - */ - memctl->memc_or1 = CONFIG_SYS_OR1; - memctl->memc_br1 = CONFIG_SYS_BR1; - - - /* - * Map 64K NVRAM, Sipex Device, NAND Ctl Reg, and LED Ctl Reg - * to chip select 3 - */ - memctl->memc_or3 = CONFIG_SYS_OR3; - memctl->memc_br3 = CONFIG_SYS_BR3; - - /* - * Map chip selects 4, 5, 6, & 7 for external expansion connector - */ - memctl->memc_or4 = CONFIG_SYS_OR4; - memctl->memc_br4 = CONFIG_SYS_BR4; - - memctl->memc_or5 = CONFIG_SYS_OR5; - memctl->memc_br5 = CONFIG_SYS_BR5; - - memctl->memc_or6 = CONFIG_SYS_OR6; - memctl->memc_br6 = CONFIG_SYS_BR6; - - memctl->memc_or7 = CONFIG_SYS_OR7; - memctl->memc_br7 = CONFIG_SYS_BR7; - -#endif - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mbmr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mbmr = mbmr_value; - - return (get_ram_size(base, maxsize)); -} diff --git a/board/snmc/qs860t/u-boot.lds b/board/snmc/qs860t/u-boot.lds deleted file mode 100644 index 0eb2fba00c..0000000000 --- a/board/snmc/qs860t/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/spc1920/Makefile b/board/spc1920/Makefile deleted file mode 100644 index c0c9a32588..0000000000 --- a/board/spc1920/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = spc1920.o hpi.o diff --git a/board/spc1920/hpi.c b/board/spc1920/hpi.c deleted file mode 100644 index c593837ad6..0000000000 --- a/board/spc1920/hpi.c +++ /dev/null @@ -1,596 +0,0 @@ -/* - * (C) Copyright 2006 - * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Host Port Interface (HPI) - */ - -/* debug levels: - * 0 : errors - * 1 : usefull info - * 2 : lots of info - * 3 : noisy - */ - -#define DEBUG 0 - -#include <config.h> -#include <common.h> -#include <mpc8xx.h> - -#include "pld.h" -#include "hpi.h" - -#define _NOT_USED_ 0xFFFFFFFF - -/* original table: - * - inserted loops to achieve long CS low and high Periods (~217ns) - * - move cs high 2/4 to the right - */ -const uint dsp_table_slow[] = -{ - /* single read (offset 0x00 in upm ram) */ - 0x8fffdc04, 0x0fffdc84, 0x0fffdc84, 0x0fffdc00, - 0x3fffdc04, 0xffffdc84, 0xffffdc84, 0xffffdc05, - - /* burst read (offset 0x08 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* single write (offset 0x18 in upm ram) */ - 0x8fffd004, 0x0fffd084, 0x0fffd084, 0x3fffd000, - 0xffffd084, 0xffffd084, 0xffffd005, _NOT_USED_, - - /* burst write (offset 0x20 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* refresh (offset 0x30 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* exception (offset 0x3C in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* dsp hpi upm ram table - * works fine for noninc access, failes on incremental. - * - removed first word - */ -const uint dsp_table_fast[] = -{ - /* single read (offset 0x00 in upm ram) */ - 0x8fffdc04, 0x0fffdc04, 0x0fffdc00, 0x3fffdc04, - 0xffffdc05, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* burst read (offset 0x08 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* single write (offset 0x18 in upm ram) */ - 0x8fffd004, 0x0fffd004, 0x3fffd000, 0xffffd005, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* burst write (offset 0x20 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* refresh (offset 0x30 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* exception (offset 0x3C in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - - -#ifdef CONFIG_SPC1920_HPI_TEST -#undef HPI_TEST_OSZI - -#define HPI_TEST_CHUNKSIZE 0x1000 -#define HPI_TEST_PATTERN 0x00000000 -#define HPI_TEST_START 0x0 -#define HPI_TEST_END 0x30000 - -#define TINY_AUTOINC_DATA_SIZE 16 /* 32bit words */ -#define TINY_AUTOINC_BASE_ADDR 0x0 - -static int hpi_activate(void); -#if 0 -static void hpi_inactivate(void); -#endif -static void dsp_reset(void); - -static int hpi_write_inc(u32 addr, u32 *data, u32 count); -static int hpi_read_inc(u32 addr, u32 *buf, u32 count); -static int hpi_write_noinc(u32 addr, u32 data); -static u32 hpi_read_noinc(u32 addr); - -int hpi_test(void); -static int hpi_write_addr_test(u32 addr); -static int hpi_read_write_test(u32 addr, u32 data); -#ifdef DO_TINY_TEST -static int hpi_tiny_autoinc_test(void); -#endif /* DO_TINY_TEST */ -#endif /* CONFIG_SPC1920_HPI_TEST */ - - -/* init the host port interface on UPMA */ -int hpi_init(void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; - - upmconfig(UPMA, (uint *)dsp_table_slow, sizeof(dsp_table_slow)/sizeof(uint)); - udelay(100); - - memctl->memc_mamr = CONFIG_SYS_MAMR; - memctl->memc_or3 = CONFIG_SYS_OR3; - memctl->memc_br3 = CONFIG_SYS_BR3; - - /* reset dsp */ - dsp_reset(); - - /* activate hpi switch*/ - pld->dsp_hpi_on = 0x1; - - udelay(100); - - return 0; -} - -#ifdef CONFIG_SPC1920_HPI_TEST -/* activate the Host Port interface */ -static int hpi_activate(void) -{ - volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; - - /* turn on hpi */ - pld->dsp_hpi_on = 0x1; - - udelay(5); - - /* turn on the power EN_DSP_POWER high*/ - /* currently always on TBD */ - - /* setup hpi control register */ - HPI_HPIC_1 = (u16) 0x0008; - HPI_HPIC_2 = (u16) 0x0008; - - udelay(100); - - return 0; -} - -#if 0 -/* turn off the host port interface */ -static void hpi_inactivate(void) -{ - volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; - - /* deactivate hpi */ - pld->dsp_hpi_on = 0x0; - - /* reset the dsp */ - /* pld->dsp_reset = 0x0; */ - - /* turn off the power EN_DSP_POWER# high*/ - /* currently always on TBD */ - -} -#endif - -/* reset the DSP */ -static void dsp_reset(void) -{ - volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; - pld->dsp_reset = 0x1; - pld->dsp_hpi_on = 0x0; - - udelay(300000); - - pld->dsp_reset = 0x0; - pld->dsp_hpi_on = 0x1; -} - - -/* write using autoinc (count is number of 32bit words) */ -static int hpi_write_inc(u32 addr, u32 *data, u32 count) -{ - int i; - u16 addr1, addr2; - - addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */ - addr2 = (u16) (addr & 0xffff); - - /* write address */ - HPI_HPIA_1 = addr1; - HPI_HPIA_2 = addr2; - - debug("writing from data=0x%lx to 0x%lx\n", - (ulong)data, (ulong)(data+count)); - - for(i=0; i<count; i++) { - HPI_HPID_INC_1 = (u16) ((data[i] >> 16) & 0xffff); - HPI_HPID_INC_2 = (u16) (data[i] & 0xffff); - debug("hpi_write_inc: data1=0x%x, data2=0x%x\n", - (u16) ((data[i] >> 16) & 0xffff), - (u16) (data[i] & 0xffff)); - } -#if 0 - while(data_ptr < (u16*) (data + count)) { - HPI_HPID_INC_1 = *(data_ptr++); - HPI_HPID_INC_2 = *(data_ptr++); - } -#endif - - /* return number of bytes written */ - return count; -} - -/* - * read using autoinc (count is number of 32bit words) - */ -static int hpi_read_inc(u32 addr, u32 *buf, u32 count) -{ - int i; - u16 addr1, addr2, data1, data2; - - addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */ - addr2 = (u16) (addr & 0xffff); - - /* write address */ - HPI_HPIA_1 = addr1; - HPI_HPIA_2 = addr2; - - for(i=0; i<count; i++) { - data1 = HPI_HPID_INC_1; - data2 = HPI_HPID_INC_2; - debug("hpi_read_inc: data1=0x%x, data2=0x%x\n", data1, data2); - buf[i] = (((u32) data1) << 16) | (data2 & 0xffff); - } - -#if 0 - while(buf_ptr < (u16*) (buf + count)) { - *(buf_ptr++) = HPI_HPID_INC_1; - *(buf_ptr++) = HPI_HPID_INC_2; - } -#endif - - /* return number of bytes read */ - return count; -} - - -/* write to non- auto inc regs */ -static int hpi_write_noinc(u32 addr, u32 data) -{ - - u16 addr1, addr2, data1, data2; - - addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */ - addr2 = (u16) (addr & 0xffff); - - /* printf("hpi_write_noinc: addr1=0x%x, addr2=0x%x\n", addr1, addr2); */ - - HPI_HPIA_1 = addr1; - HPI_HPIA_2 = addr2; - - data1 = (u16) ((data >> 16) & 0xffff); - data2 = (u16) (data & 0xffff); - - /* printf("hpi_write_noinc: data1=0x%x, data2=0x%x\n", data1, data2); */ - - HPI_HPID_NOINC_1 = data1; - HPI_HPID_NOINC_2 = data2; - - return 0; -} - -/* read from non- auto inc regs */ -static u32 hpi_read_noinc(u32 addr) -{ - u16 addr1, addr2, data1, data2; - u32 ret; - - addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */ - addr2 = (u16) (addr & 0xffff); - - HPI_HPIA_1 = addr1; - HPI_HPIA_2 = addr2; - - /* printf("hpi_read_noinc: addr1=0x%x, addr2=0x%x\n", addr1, addr2); */ - - data1 = HPI_HPID_NOINC_1; - data2 = HPI_HPID_NOINC_2; - - /* printf("hpi_read_noinc: data1=0x%x, data2=0x%x\n", data1, data2); */ - - ret = (((u32) data1) << 16) | (data2 & 0xffff); - return ret; - -} - -/* - * Host Port Interface Tests - */ - -#ifndef HPI_TEST_OSZI -/* main test function */ -int hpi_test(void) -{ - int err = 0; - u32 i, ii, pattern, tmp; - - pattern = HPI_TEST_PATTERN; - - u32 test_data[HPI_TEST_CHUNKSIZE]; - u32 read_data[HPI_TEST_CHUNKSIZE]; - - debug("hpi_test: activating hpi..."); - hpi_activate(); - debug("OK.\n"); - -#if 0 - /* Dump the first 1024 bytes - * - */ - for(i=0; i<1024; i+=4) { - if(i%16==0) - printf("\n0x%08x: ", i); - printf("0x%08x ", hpi_read_noinc(i)); - } -#endif - - /* HPIA read-write test - * - */ - debug("hpi_test: starting HPIA read-write tests...\n"); - err |= hpi_write_addr_test(0xdeadc0de); - err |= hpi_write_addr_test(0xbeefd00d); - err |= hpi_write_addr_test(0xabcd1234); - err |= hpi_write_addr_test(0xaaaaaaaa); - if(err) { - debug("hpi_test: HPIA read-write tests: *** FAILED ***\n"); - return -1; - } - debug("hpi_test: HPIA read-write tests: OK\n"); - - - /* read write test using nonincremental data regs - * - */ - debug("hpi_test: starting nonincremental tests...\n"); - for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) { - err |= hpi_read_write_test(i, pattern); - - /* stolen from cmd_mem.c */ - if(pattern & 0x80000000) { - pattern = -pattern; /* complement & increment */ - } else { - pattern = ~pattern; - } - err |= hpi_read_write_test(i, pattern); - - if(err) { - debug("hpi_test: nonincremental tests *** FAILED ***\n"); - return -1; - } - } - debug("hpi_test: nonincremental test OK\n"); - - /* read write a chunk of data using nonincremental data regs - * - */ - debug("hpi_test: starting nonincremental chunk tests...\n"); - pattern = HPI_TEST_PATTERN; - for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) { - hpi_write_noinc(i, pattern); - - /* stolen from cmd_mem.c */ - if(pattern & 0x80000000) { - pattern = -pattern; /* complement & increment */ - } else { - pattern = ~pattern; - } - } - pattern = HPI_TEST_PATTERN; - for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) { - tmp = hpi_read_noinc(i); - - if(tmp != pattern) { - debug("hpi_test: noninc chunk test *** FAILED *** @ 0x%x, written=0x%x, read=0x%x\n", i, pattern, tmp); - err = -1; - } - /* stolen from cmd_mem.c */ - if(pattern & 0x80000000) { - pattern = -pattern; /* complement & increment */ - } else { - pattern = ~pattern; - } - } - if(err) - return -1; - debug("hpi_test: nonincremental chunk test OK\n"); - - -#ifdef DO_TINY_TEST - /* small verbose test using autoinc and nonautoinc to compare - * - */ - debug("hpi_test: tiny_autoinc_test...\n"); - hpi_tiny_autoinc_test(); - debug("hpi_test: tiny_autoinc_test done\n"); -#endif /* DO_TINY_TEST */ - - - /* $%& write a chunk of data using the autoincremental regs - * - */ - debug("hpi_test: starting autoinc test %d chunks with 0x%x bytes...\n", - ((HPI_TEST_END - HPI_TEST_START) / HPI_TEST_CHUNKSIZE), - HPI_TEST_CHUNKSIZE); - - for(i=HPI_TEST_START; - i < ((HPI_TEST_END - HPI_TEST_START) / HPI_TEST_CHUNKSIZE); - i++) { - /* generate the pattern data */ - debug("generating pattern data: "); - for(ii = 0; ii < HPI_TEST_CHUNKSIZE; ii++) { - debug("0x%x ", pattern); - - test_data[ii] = pattern; - read_data[ii] = 0x0; /* zero to be sure */ - - /* stolen from cmd_mem.c */ - if(pattern & 0x80000000) { - pattern = -pattern; /* complement & increment */ - } else { - pattern = ~pattern; - } - } - debug("done\n"); - - debug("Writing autoinc data @ 0x%x\n", i); - hpi_write_inc(i, test_data, HPI_TEST_CHUNKSIZE); - - debug("Reading autoinc data @ 0x%x\n", i); - hpi_read_inc(i, read_data, HPI_TEST_CHUNKSIZE); - - /* compare */ - for(ii = 0; ii < HPI_TEST_CHUNKSIZE; ii++) { - debug("hpi_test_autoinc: @ 0x%x, written=0x%x, read=0x%x", i+ii, test_data[ii], read_data[ii]); - if(read_data[ii] != test_data[ii]) { - debug("hpi_test: autoinc test @ 0x%x, written=0x%x, read=0x%x *** FAILED ***\n", i+ii, test_data[ii], read_data[ii]); - return -1; - } - } - } - debug("hpi_test: autoinc test OK\n"); - - return 0; -} -#else /* HPI_TEST_OSZI */ -int hpi_test(void) -{ - int i; - u32 read_data[TINY_AUTOINC_DATA_SIZE]; - - unsigned int dummy_data[TINY_AUTOINC_DATA_SIZE] = { - 0x11112222, 0x33334444, 0x55556666, 0x77778888, - 0x9999aaaa, 0xbbbbcccc, 0xddddeeee, 0xffff1111, - 0x00010002, 0x00030004, 0x00050006, 0x00070008, - 0x0009000a, 0x000b000c, 0x000d000e, 0x000f0001 - }; - - debug("hpi_test: activating hpi..."); - hpi_activate(); - debug("OK.\n"); - - while(1) { - led9(1); - debug(" writing to autoinc...\n"); - hpi_write_inc(TINY_AUTOINC_BASE_ADDR, - dummy_data, TINY_AUTOINC_DATA_SIZE); - - debug(" reading from autoinc...\n"); - hpi_read_inc(TINY_AUTOINC_BASE_ADDR, - read_data, TINY_AUTOINC_DATA_SIZE); - - for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++) { - debug(" written=0x%x, read(inc)=0x%x\n", - dummy_data[i], read_data[i]); - } - led9(0); - udelay(2000000); - } - return 0; -} -#endif - -/* test if Host Port Address Register can be written correctly */ -static int hpi_write_addr_test(u32 addr) -{ - u32 read_back; - /* write address */ - HPI_HPIA_1 = ((u16) (addr >> 16)); /* First HW is most significant */ - HPI_HPIA_2 = ((u16) addr); - - read_back = (((u32) HPI_HPIA_1)<<16) | ((u32) HPI_HPIA_2); - - if(read_back == addr) { - debug(" hpi_write_addr_test OK: written=0x%x, read=0x%x\n", - addr, read_back); - return 0; - } else { - debug(" hpi_write_addr_test *** FAILED ***: written=0x%x, read=0x%x\n", - addr, read_back); - return -1; - } - - return 0; -} - -/* test if a simple read/write sequence succeeds */ -static int hpi_read_write_test(u32 addr, u32 data) -{ - u32 read_back; - - hpi_write_noinc(addr, data); - read_back = hpi_read_noinc(addr); - - if(read_back == data) { - debug(" hpi_read_write_test: OK, addr=0x%x written=0x%x, read=0x%x\n", addr, data, read_back); - return 0; - } else { - debug(" hpi_read_write_test: *** FAILED ***, addr=0x%x written=0x%x, read=0x%x\n", addr, data, read_back); - return -1; - } - - return 0; -} - -#ifdef DO_TINY_TEST -static int hpi_tiny_autoinc_test(void) -{ - int i; - u32 read_data[TINY_AUTOINC_DATA_SIZE]; - u32 read_data_noinc[TINY_AUTOINC_DATA_SIZE]; - - unsigned int dummy_data[TINY_AUTOINC_DATA_SIZE] = { - 0x11112222, 0x33334444, 0x55556666, 0x77778888, - 0x9999aaaa, 0xbbbbcccc, 0xddddeeee, 0xffff1111, - 0x00010002, 0x00030004, 0x00050006, 0x00070008, - 0x0009000a, 0x000b000c, 0x000d000e, 0x000f0001 - }; - - printf(" writing to autoinc...\n"); - hpi_write_inc(TINY_AUTOINC_BASE_ADDR, dummy_data, TINY_AUTOINC_DATA_SIZE); - - printf(" reading from autoinc...\n"); - hpi_read_inc(TINY_AUTOINC_BASE_ADDR, read_data, TINY_AUTOINC_DATA_SIZE); - - printf(" reading from noinc for comparison...\n"); - for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++) - read_data_noinc[i] = hpi_read_noinc(TINY_AUTOINC_BASE_ADDR+i*4); - - for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++) { - printf(" written=0x%x, read(inc)=0x%x, read(noinc)=0x%x\n", - dummy_data[i], read_data[i], read_data_noinc[i]); - } - return 0; -} -#endif /* DO_TINY_TEST */ - -#endif /* CONFIG_SPC1920_HPI_TEST */ diff --git a/board/spc1920/hpi.h b/board/spc1920/hpi.h deleted file mode 100644 index db67672a8e..0000000000 --- a/board/spc1920/hpi.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * (C) Copyright 2006 - * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -int hpi_init(void); - -#ifdef CONFIG_SPC1920_HPI_TEST -int hpi_test(void); -#endif diff --git a/board/spc1920/pld.h b/board/spc1920/pld.h deleted file mode 100644 index 5beb71b5cc..0000000000 --- a/board/spc1920/pld.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef __PLD_H__ -#define __PLD_H__ - -typedef struct spc1920_pld { - uchar com1_en; - uchar dsp_reset; - uchar dsp_hpi_on; - uchar superv_mode; - uchar codec_dsp_power_en; - uchar clk3_select; - uchar clk4_select; -} spc1920_pld_t; - -#endif /* __PLD_H__ */ diff --git a/board/spc1920/spc1920.c b/board/spc1920/spc1920.c deleted file mode 100644 index 1775433f0d..0000000000 --- a/board/spc1920/spc1920.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <mpc8xx.h> -#include "pld.h" -#include "hpi.h" - -#define _NOT_USED_ 0xFFFFFFFF - -static long int dram_size (long int, long int *, long int); - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMB RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMB RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMB RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMB RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMB RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMB RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMB RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - /* volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; */ - - long int size_b0; - long int size8, size9; - int i; - - /* - * Configure UPMB for SDRAM - */ - upmconfig (UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - udelay(100); - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - /* burst length=4, burst type=sequential, CAS latency=2 */ - memctl->memc_mar = CONFIG_SYS_MAR; - - /* - * Map controller bank 1 to the SDRAM bank at preliminary address. - */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - /* initialize memory address register */ - memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */ - - /* mode initialization (offset 5) */ - udelay (200); /* 0x80006105 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x05); - - /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */ - udelay (1); /* 0x80006130 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30); - udelay (1); /* 0x80006130 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30); - udelay (1); /* 0x80006106 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x06); - - memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */ - - udelay (200); - - /* Need at least 10 DRAM accesses to stabilize */ - for (i = 0; i < 10; ++i) { - volatile unsigned long *addr = - (volatile unsigned long *) CONFIG_SYS_SDRAM_BASE; - unsigned long val; - - val = *(addr + i); - *(addr + i) = val; - } - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MBMR_8COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MBMR_9COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; - memctl->memc_mbmr = CONFIG_SYS_MBMR_9COL | MBMR_PTBE; - udelay (500); - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE; - udelay (500); - } - - /* - * Final mapping: - */ - - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | - OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING; - memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V; - udelay (1000); - - /* initalize the DSP Host Port Interface */ - hpi_init(); - - /* FRAM Setup */ - memctl->memc_or4 = CONFIG_SYS_OR4; - memctl->memc_br4 = CONFIG_SYS_BR4; - udelay(1000); - - return (size_b0); -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -static long int dram_size (long int mbmr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mbmr = mbmr_value; - - return (get_ram_size (base, maxsize)); -} - - -/************* other stuff ******************/ - - -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - /* Set Go/NoGo led (PA15) to color red */ - immap->im_ioport.iop_papar &= ~0x1; - immap->im_ioport.iop_paodr &= ~0x1; - immap->im_ioport.iop_padir |= 0x1; - immap->im_ioport.iop_padat |= 0x1; - -#if 0 - /* Turn on LED PD9 */ - immap->im_ioport.iop_pdpar &= ~(0x0040); - immap->im_ioport.iop_pddir |= 0x0040; - immap->im_ioport.iop_pddat |= 0x0040; -#endif - - /* - * Enable console on SMC1. This requires turning on - * the com2_en signal and SMC1_DISABLE - */ - - /* SMC1_DISABLE: PB17 */ - immap->im_cpm.cp_pbodr &= ~0x4000; - immap->im_cpm.cp_pbpar &= ~0x4000; - immap->im_cpm.cp_pbdir |= 0x4000; - immap->im_cpm.cp_pbdat &= ~0x4000; - - /* COM2_EN: PD10 */ - immap->im_ioport.iop_pdpar &= ~0x0020; - immap->im_ioport.iop_pddir &= ~0x4000; - immap->im_ioport.iop_pddir |= 0x0020; - immap->im_ioport.iop_pddat |= 0x0020; - - -#ifdef CONFIG_SYS_SMC1_PLD_CLK4 /* SMC1 uses CLK4 from PLD */ - immap->im_cpm.cp_simode |= 0x7000; - immap->im_cpm.cp_simode &= ~(0x8000); -#endif - - return 0; -} - -int last_stage_init(void) -{ -#ifdef CONFIG_SPC1920_HPI_TEST - printf("CMB1920 Host Port Interface Test: %s\n", - hpi_test() ? "Failed!" : "OK"); -#endif - return 0; -} - -int checkboard (void) -{ - puts("Board: SPC1920\n"); - return 0; -} diff --git a/board/spc1920/u-boot.lds b/board/spc1920/u-boot.lds deleted file mode 100644 index 0eb2fba00c..0000000000 --- a/board/spc1920/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds index 2c5a0f8a11..78f294af40 100644 --- a/board/ti/am335x/u-boot.lds +++ b/board/ti/am335x/u-boot.lds @@ -78,6 +78,8 @@ SECTIONS *(.__rel_dyn_end) } + .hash : { *(.hash*) } + .end : { *(.__end) @@ -118,7 +120,6 @@ SECTIONS .dynbss : { *(.dynbss) } .dynstr : { *(.dynstr*) } .dynamic : { *(.dynamic*) } - .hash : { *(.hash*) } .gnu.hash : { *(.gnu.hash) } .plt : { *(.plt*) } .interp : { *(.interp*) } diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile index cb5fe88901..36ecb302c1 100644 --- a/board/ti/am43xx/Makefile +++ b/board/ti/am43xx/Makefile @@ -6,7 +6,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) obj-y := mux.o endif diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index d7449770a3..7e239f1c88 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -19,6 +19,7 @@ #include <asm/arch/gpio.h> #include <asm/emif.h> #include "board.h" +#include <power/tps65218.h> #include <miiphy.h> #include <cpsw.h> @@ -67,10 +68,13 @@ static int read_eeprom(struct am43xx_board_id *header) strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name)); am43xx_board_name[sizeof(header->name)] = 0; + strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version)); + am43xx_board_rev[sizeof(header->version)] = 0; + return 0; } -#ifdef CONFIG_SPL_BUILD +#ifndef CONFIG_SKIP_LOWLEVEL_INIT #define NUM_OPPS 6 @@ -153,12 +157,16 @@ const struct emif_regs emif_regs_lpddr2 = { .emif_rd_wr_lvl_rmp_ctl = 0x0, .emif_rd_wr_lvl_ctl = 0x0, .emif_ddr_phy_ctlr_1 = 0x0E084006, - .emif_rd_wr_exec_thresh = 0x00000405, + .emif_rd_wr_exec_thresh = 0x80000405, .emif_ddr_ext_phy_ctrl_1 = 0x04010040, .emif_ddr_ext_phy_ctrl_2 = 0x00500050, .emif_ddr_ext_phy_ctrl_3 = 0x00500050, .emif_ddr_ext_phy_ctrl_4 = 0x00500050, - .emif_ddr_ext_phy_ctrl_5 = 0x00500050 + .emif_ddr_ext_phy_ctrl_5 = 0x00500050, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF }; const u32 ext_phy_ctrl_const_base_lpddr2[] = { @@ -213,7 +221,83 @@ const struct emif_regs ddr3_emif_regs_400Mhz = { .emif_rd_wr_lvl_rmp_win = 0x0, .emif_rd_wr_lvl_rmp_ctl = 0x0, .emif_rd_wr_lvl_ctl = 0x0, - .emif_rd_wr_exec_thresh = 0x00000405 + .emif_rd_wr_exec_thresh = 0x80000405, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +/* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */ +const struct emif_regs ddr3_emif_regs_400Mhz_beta = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E004008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00000065, + .emif_ddr_ext_phy_ctrl_3 = 0x00000091, + .emif_ddr_ext_phy_ctrl_4 = 0x000000B5, + .emif_ddr_ext_phy_ctrl_5 = 0x000000E5, + .emif_rd_wr_exec_thresh = 0x80000405, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ +const struct emif_regs ddr3_emif_regs_400Mhz_production = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E004008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00000066, + .emif_ddr_ext_phy_ctrl_3 = 0x00000091, + .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, + .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, + .emif_rd_wr_exec_thresh = 0x80000405, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { + .sdram_config = 0x638413b2, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x00000c30, + .sdram_tim1 = 0xeaaad4db, + .sdram_tim2 = 0x266b7fda, + .sdram_tim3 = 0x107f8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074be4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0e084008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x89, + .emif_ddr_ext_phy_ctrl_3 = 0x90, + .emif_ddr_ext_phy_ctrl_4 = 0x8e, + .emif_ddr_ext_phy_ctrl_5 = 0x8d, + .emif_rd_wr_lvl_rmp_win = 0x0, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x80000000, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF }; const u32 ext_phy_ctrl_const_base_ddr3[] = { @@ -239,14 +323,111 @@ const u32 ext_phy_ctrl_const_base_ddr3[] = { 0x08102040 }; +const u32 ext_phy_ctrl_const_base_ddr3_beta[] = { + 0x00000000, + 0x00000045, + 0x00000046, + 0x00000048, + 0x00000047, + 0x00000000, + 0x0000004C, + 0x00000070, + 0x00000085, + 0x000000A3, + 0x00000000, + 0x0000000C, + 0x00000030, + 0x00000045, + 0x00000063, + 0x00000000, + 0x0, + 0x0, + 0x40000000, + 0x08102040 +}; + +const u32 ext_phy_ctrl_const_base_ddr3_production[] = { + 0x00000000, + 0x00000044, + 0x00000044, + 0x00000046, + 0x00000046, + 0x00000000, + 0x00000059, + 0x00000077, + 0x00000093, + 0x000000A8, + 0x00000000, + 0x00000019, + 0x00000037, + 0x00000053, + 0x00000068, + 0x00000000, + 0x0, + 0x0, + 0x40000000, + 0x08102040 +}; + +static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = { + /* first 5 are taken care by emif_regs */ + 0x00700070, + + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + + 0x00150015, + 0x00150015, + 0x00150015, + 0x00150015, + 0x00150015, + + 0x00800080, + 0x00800080, + + 0x40000000, + + 0x08102040, + + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) { if (board_is_eposevm()) { *regs = ext_phy_ctrl_const_base_lpddr2; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); + } else if (board_is_evm_14_or_later()) { + *regs = ext_phy_ctrl_const_base_ddr3_production; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production); + } else if (board_is_evm_12_or_later()) { + *regs = ext_phy_ctrl_const_base_ddr3_beta; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta); } else if (board_is_gpevm()) { *regs = ext_phy_ctrl_const_base_ddr3; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); + } else if (board_is_sk()) { + *regs = ext_phy_ctrl_const_base_ddr3_sk; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk); } return; @@ -254,19 +435,12 @@ void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) const struct dpll_params *get_dpll_ddr_params(void) { - struct am43xx_board_id header; - - enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - if (read_eeprom(&header) < 0) - puts("Could not get board ID.\n"); - if (board_is_eposevm()) return &epos_evm_dpll_ddr; - else if (board_is_gpevm()) + else if (board_is_gpevm() || board_is_sk()) return &gp_evm_dpll_ddr; - puts(" Board not supported\n"); + printf(" Board '%s' not supported\n", am43xx_board_name); return NULL; } @@ -302,7 +476,10 @@ static u32 get_sys_clk_index(void) static int get_opp_offset(int max_off, int min_off) { struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; - int opp = readl(&ctrl->dev_attr), offset, i; + int opp, offset, i; + + /* Bits 0:11 are defined to be the MPU_MAX_FREQ */ + opp = readl(&ctrl->dev_attr) & ~0xFFFFF000; for (i = max_off; i >= min_off; i--) { offset = opp & (1 << i); @@ -335,6 +512,46 @@ const struct dpll_params *get_dpll_per_params(void) return &dpll_per[ind]; } +void scale_vcores(void) +{ + const struct dpll_params *mpu_params; + int mpu_vdd; + struct am43xx_board_id header; + + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); + + /* Get the frequency */ + mpu_params = get_dpll_mpu_params(); + + if (i2c_probe(TPS65218_CHIP_PM)) + return; + + if (mpu_params->m == 1000) { + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; + } else if (mpu_params->m == 600) { + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; + } else { + puts("Unknown MPU clock, not scaling\n"); + return; + } + + /* Set DCDC1 (CORE) voltage to 1.1V */ + if (tps65218_voltage_update(TPS65218_DCDC1, + TPS65218_DCDC_VOLT_SEL_1100MV)) { + puts("tps65218_voltage_update failure\n"); + return; + } + + /* Set DCDC2 (MPU) voltage */ + if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { + puts("tps65218_voltage_update failure\n"); + return; + } +} + void set_uart_mux_conf(void) { enable_uart0_pin_mux(); @@ -369,18 +586,65 @@ void sdram_init(void) */ if (board_is_eposevm()) { config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); + } else if (board_is_evm_14_or_later()) { + enable_vtt_regulator(); + config_ddr(0, &ioregs_ddr3, NULL, NULL, + &ddr3_emif_regs_400Mhz_production, 0); + } else if (board_is_evm_12_or_later()) { + enable_vtt_regulator(); + config_ddr(0, &ioregs_ddr3, NULL, NULL, + &ddr3_emif_regs_400Mhz_beta, 0); } else if (board_is_gpevm()) { enable_vtt_regulator(); config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs_400Mhz, 0); + } else if (board_is_sk()) { + config_ddr(400, &ioregs_ddr3, NULL, NULL, + &ddr3_sk_emif_regs_400Mhz, 0); } } #endif int board_init(void) { + struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER; + u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, + modena_init0_bw_integer, modena_init0_watermark_0; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + /* Clear all important bits for DSS errata that may need to be tweaked*/ + mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & + MREQPRIO_0_SAB_INIT0_MASK; + + mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK; + + modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) & + BW_LIMITER_BW_FRAC_MASK; + + modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) & + BW_LIMITER_BW_INT_MASK; + + modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) & + BW_LIMITER_BW_WATERMARK_MASK; + + /* Setting MReq Priority of the DSS*/ + mreqprio_0 |= 0x77; + + /* + * Set L3 Fast Configuration Register + * Limiting bandwith for ARM core to 700 MBPS + */ + modena_init0_bw_fractional |= 0x10; + modena_init0_bw_integer |= 0x3; + + writel(mreqprio_0, &cdev->mreqprio_0); + writel(mreqprio_1, &cdev->mreqprio_1); + + writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional); + writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer); + writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0); + return 0; } @@ -487,6 +751,11 @@ int board_eth_init(bd_t *bis) writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; cpsw_slaves[0].phy_addr = 16; + } else if (board_is_sk()) { + writel(RGMII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; + cpsw_slaves[0].phy_addr = 4; + cpsw_slaves[1].phy_addr = 5; } else { writel(RGMII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h index 091162ee20..8e121914e3 100644 --- a/board/ti/am43xx/board.h +++ b/board/ti/am43xx/board.h @@ -15,6 +15,7 @@ #include <asm/arch/omap.h> static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START; +static char *const am43xx_board_rev = (char *)AM4372_BOARD_VERSION_START; /* * TI AM437x EVMs define a system EEPROM that defines certain sub-fields. @@ -47,6 +48,21 @@ static inline int board_is_gpevm(void) return !strncmp(am43xx_board_name, "AM43__GP", HDR_NAME_LEN); } +static inline int board_is_sk(void) +{ + return !strncmp(am43xx_board_name, "AM43__SK", HDR_NAME_LEN); +} + +static inline int board_is_evm_14_or_later(void) +{ + return (board_is_gpevm() && strncmp("1.4", am43xx_board_rev, 3) <= 0); +} + +static inline int board_is_evm_12_or_later(void) +{ + return (board_is_gpevm() && strncmp("1.2", am43xx_board_rev, 3) <= 0); +} + void enable_uart0_pin_mux(void); void enable_board_pin_mux(void); void enable_i2c0_pin_mux(void); diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 77c53d2e90..50967e1a82 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -97,6 +97,9 @@ void enable_board_pin_mux(void) if (board_is_gpevm()) { configure_module_pin_mux(gpio5_7_pin_mux); configure_module_pin_mux(rgmii1_pin_mux); + } else if (board_is_sk()) { + configure_module_pin_mux(rgmii1_pin_mux); + configure_module_pin_mux(qspi_pin_mux); } else if (board_is_eposevm()) { configure_module_pin_mux(rmii1_pin_mux); configure_module_pin_mux(qspi_pin_mux); diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 073d15127c..7f19655cfe 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -82,6 +82,12 @@ int board_init(void) int board_late_init(void) { +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + if (omap_revision() == DRA722_ES1_0) + setenv("board_name", "dra72x"); + else + setenv("board_name", "dra7xx"); +#endif init_sata(0); return 0; } diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 38de9d5a8b..c9e202af68 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -31,10 +31,15 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ +#if (CONFIG_CONS_INDEX == 1) {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */ {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */ {UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */ {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */ +#elif (CONFIG_CONS_INDEX == 3) + {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */ + {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */ +#endif {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c index dc39139565..ef90f9d821 100644 --- a/board/ti/k2hk_evm/board.c +++ b/board/ti/k2hk_evm/board.c @@ -16,9 +16,9 @@ #include <asm/arch/clock.h> #include <asm/io.h> #include <asm/mach-types.h> -#include <asm/arch/nand_defs.h> #include <asm/arch/emac_defs.h> #include <asm/arch/psc_defs.h> +#include <asm/ti-common/ti-aemif.h> DECLARE_GLOBAL_DATA_PTR; @@ -40,9 +40,9 @@ unsigned int external_clk[ext_clk_count] = { what is that */ }; -static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = { +static struct aemif_config aemif_configs[] = { { /* CS0 */ - .mode = ASYNC_EMIF_MODE_NAND, + .mode = AEMIF_MODE_NAND, .wr_setup = 0xf, .wr_strobe = 0x3f, .wr_hold = 7, @@ -50,7 +50,7 @@ static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = { .rd_strobe = 0x3f, .rd_hold = 7, .turn_around = 3, - .width = ASYNC_EMIF_8, + .width = AEMIF_WIDTH_8, }, }; @@ -67,7 +67,7 @@ int dram_init(void) gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); - init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config); + aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); return 0; } diff --git a/board/ti/tnetv107xevm/sdb_board.c b/board/ti/tnetv107xevm/sdb_board.c index a95434b5ef..a84ec84bae 100644 --- a/board/ti/tnetv107xevm/sdb_board.c +++ b/board/ti/tnetv107xevm/sdb_board.c @@ -11,7 +11,7 @@ #include <asm/arch/clock.h> #include <asm/io.h> #include <asm/mach-types.h> -#include <asm/arch/nand_defs.h> +#include <asm/ti-common/davinci_nand.h> #include <asm/arch/mux.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/ttcontrol/vision2/imximage_hynix.cfg b/board/ttcontrol/vision2/imximage_hynix.cfg index 4e6583ac76..c74973edec 100644 --- a/board/ttcontrol/vision2/imximage_hynix.cfg +++ b/board/ttcontrol/vision2/imximage_hynix.cfg @@ -124,7 +124,7 @@ DATA 4 0x73fa889c 0x00000000 /* ESDCTL0: Enable controller */ DATA 4 0x83fd9000 0x83220000 -/* Init DRAM on CS0 / +/* Init DRAM on CS0 */ /* ESDSCR: Precharge command */ DATA 4 0x83fd9014 0x04008008 /* ESDSCR: Refresh command */ diff --git a/board/v37/Makefile b/board/v37/Makefile deleted file mode 100644 index 2df4b82fb8..0000000000 --- a/board/v37/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = v37.o flash.o diff --git a/board/v37/flash.c b/board/v37/flash.c deleted file mode 100644 index 5b34af249b..0000000000 --- a/board/v37/flash.c +++ /dev/null @@ -1,543 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * Some of flash control words are modified. (from 2x16bit device - * to 4x8bit device) - * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices - * are not tested. - * - * (?) Does an RPXLite board which - * does not use AM29LV800 flash memory exist ? - * I don't know... - */ - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size ( short manu, short dev_id, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info, int two_chips); -static void flash_get_id_word( void *ptr, short *ptr_manuf, short *ptr_dev_id); -static void flash_get_id_long( void *ptr, short *ptr_manuf, short *ptr_dev_id); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - short manu, dev_id; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Do sizing to get full correct info */ - - flash_get_id_word((void*)CONFIG_SYS_FLASH_BASE0,&manu,&dev_id); - - size_b0 = flash_get_size(manu, dev_id, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE0, &flash_info[0],0); - - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (0 - size_b0); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE0 - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_get_id_long((void*)CONFIG_SYS_FLASH_BASE1,&manu,&dev_id); - - size_b1 = 2 * flash_get_size(manu, dev_id, &flash_info[1]); - - flash_get_offsets(CONFIG_SYS_FLASH_BASE1, &flash_info[1],1); - - memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (0 - size_b1); - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0+size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info, int two_chips) -{ - int i, addr_shift; - vu_short *addr = (vu_short*)base; - - addr[0x555] = 0x00AA ; - addr[0xAAA] = 0x0055 ; - addr[0x555] = 0x0090 ; - - addr_shift = (two_chips ? 2 : 1 ); - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + (0x00000000<<addr_shift); - info->start[1] = base + (0x00002000<<addr_shift); - info->start[2] = base + (0x00003000<<addr_shift); - info->start[3] = base + (0x00004000<<addr_shift); - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i-3) * (0x00008000<<addr_shift)) ; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - (0x00002000<<addr_shift); - info->start[i--] = base + info->size - (0x00003000<<addr_shift); - info->start[i--] = base + info->size - (0x00004000<<addr_shift); - for (; i >= 0; i--) { - info->start[i] = base + i * (0x00008000<<addr_shift); - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (vu_short *)(info->start[i]); - info->protect[i] = addr[1<<addr_shift] & 1 ; - } - - addr = (vu_short *)info->start[0]; - *addr = 0xF0F0; /* reset bank */ -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_TOSH: printf ("TOSHIBA "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static void flash_get_id_word( void *ptr, short *ptr_manuf, short *ptr_dev_id) -{ - vu_short *addr = (vu_short*)ptr; - - addr[0x555] = 0x00AA ; - addr[0xAAA] = 0x0055 ; - addr[0x555] = 0x0090 ; - - *ptr_manuf = addr[0]; - *ptr_dev_id = addr[1]; - - addr[0] = 0xf0f0; /* return to normal */ -} - -static void flash_get_id_long( void *ptr, short *ptr_manuf, short *ptr_dev_id) -{ - vu_short *addr = (vu_short*)ptr; - vu_short *addr1, *addr2, *addr3; - - addr1 = (vu_short*) ( ((int)ptr) + (0x5555<<2) ); - addr2 = (vu_short*) ( ((int)ptr) + (0x2AAA<<2) ); - addr3 = (vu_short*) ( ((int)ptr) + (0x5555<<2) ); - - *addr1 = 0xAAAA; - *addr2 = 0x5555; - *addr3 = 0x9090; - - *ptr_manuf = addr[0]; - *ptr_dev_id = addr[2]; - - addr[0] = 0xf0f0; /* return to normal */ -} - -static ulong flash_get_size ( short manu, short dev_id, flash_info_t *info) -{ - switch (manu) { - case ((short)AMD_MANUFACT): - info->flash_id = FLASH_MAN_AMD; - break; - case ((short)FUJ_MANUFACT): - info->flash_id = FLASH_MAN_FUJ; - break; - case ((short)TOSH_MANUFACT): - info->flash_id = FLASH_MAN_TOSH; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - - switch (dev_id) { - case ((short)TOSH_ID_FVT160): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 1 MB */ - - case ((short)TOSH_ID_FVB160): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 1 MB */ - - case ((short)AMD_ID_LV400T): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case ((short)AMD_ID_LV400B): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case ((short)AMD_ID_LV800T): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case ((short)AMD_ID_LV800B): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; /*%%% Size doubled by yooth */ - break; /* => 4 MB */ - - case ((short)AMD_ID_LV160T): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 4 MB */ - - case ((short)AMD_ID_LV160B): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 4 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_short *addr = (vu_short*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x555] = (vu_short)0xAAAAAAAA; - addr[0xAAA] = (vu_short)0x55555555; - addr[0x555] = (vu_short)0x80808080; - addr[0x555] = (vu_short)0xAAAAAAAA; - addr[0xAAA] = (vu_short)0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_short *)(info->start[sect]) ; - addr[0] = (vu_short)0x30303030 ; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_short *)(info->start[l_sect]); - while ((addr[0] & 0x8080) != 0x8080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_short *)info->start[0]; - addr[0] = (vu_short)0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_short *addr = (vu_short *)(info->start[0]); - vu_short sdata; - - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - /* First write upper 16 bits */ - sdata = (short)(data>>16); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x555] = 0xAAAA; - addr[0xAAA] = 0x5555; - addr[0x555] = 0xA0A0; - - *((vu_short *)dest) = sdata; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_short *)dest) & 0x8080) != (sdata & 0x8080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - - /* Now write lower 16 bits */ - sdata = (short)(data&0xffff); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x555] = 0xAAAA; - addr[0xAAA] = 0x5555; - addr[0x555] = 0xA0A0; - - *((vu_short *)dest + 1) = sdata; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_short *)dest + 1) & 0x8080) != (sdata & 0x8080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/v37/u-boot.lds b/board/v37/u-boot.lds deleted file mode 100644 index 6e19b3f458..0000000000 --- a/board/v37/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2003-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/v37/v37.c b/board/v37/v37.c deleted file mode 100644 index 438117e60c..0000000000 --- a/board/v37/v37.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * DRAM related UPMA register values are modified. - * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS - */ - -#include <common.h> -#include "mpc8xx.h" - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (void); - -/* ------------------------------------------------------------------------- */ - -#define MBYTE (1024*1024) -#define DRAM_DELAY 0x00000379 /* DRAM delay count */ -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = -{ - /* single read. (offset 0 in upm RAM) */ - 0x1F07D004, 0xEEAEE004, 0x11ADD004, 0xEFBBA000, - 0x1FF75447, 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, - - /* burst read. (Offset 8 in upm RAM) */ - 0x1F07D004, 0xEEAEE004, 0x00ADC004, 0x00AFC000, - 0x00AFC000, 0x01AFC000, 0x0FBB8000, 0x1FF75447, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* single write. (Offset 0x18 in upm RAM) */ - 0x1F27D004, 0xEEAEA000, 0x01B90004, 0x1FF75447, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* burst write. (Offset 0x20 in upm RAM) */ - 0x1F07D004, 0xEEAEA000, 0x00AD4000, 0x00AFC000, - 0x00AFC000, 0x01BB8004, 0x1FF75447, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Refresh cycle, offset 0x30 */ - 0x1FF5DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Exception, 0ffset 0x3C */ - 0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, -}; -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Return 1 for now. - * - */ - -int checkboard (void) -{ - printf("Marel V37\n") ; - return (0) ; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long temp; - volatile int delay_cnt; - long int ramsize; - - ramsize = dram_size(); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = 0x400 ; - - if( ramsize == 32*MBYTE ) - temp = 0xd0904110; - else /* 16MB */ - temp = 0xd0802110; - - memctl->memc_mbmr = temp; - - upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* Map controller banks 2 to the SDRAM bank */ - memctl->memc_or2 = 0xA00 | (0 - ramsize); - memctl->memc_br2 = 0xC1; - - memctl->memc_mbmr = temp | 0x08; - memctl->memc_mcr = 0x80804130; - - delay_cnt = 0; - while( delay_cnt++ < DRAM_DELAY ) - ; - - /* Run MRS command in location 5-8 of UPMB */ - - memctl->memc_mbmr = temp | 0x04; - memctl->memc_mar = 0x88; - - memctl->memc_mcr = 0x80804105; - - delay_cnt = 0; - while( delay_cnt++ < DRAM_DELAY ) - ; - -#ifdef CONFIG_CAN_DRIVER - /* Initialize OR3 / BR3 */ - memctl->memc_or3 = CONFIG_SYS_OR3_CAN; - memctl->memc_br3 = CONFIG_SYS_BR3_CAN; - - /* Initialize MBMR */ - memctl->memc_mamr = MAMR_GPL_A4DIS; /* GPL_A4 ouput line Disable */ - - /* Initialize UPMB for CAN: single read */ - memctl->memc_mdr = 0xFFFFC004; - memctl->memc_mcr = 0x0100 | UPMA; - - memctl->memc_mdr = 0x0FFFD004; - memctl->memc_mcr = 0x0101 | UPMA; - - memctl->memc_mdr = 0x0FFFC000; - memctl->memc_mcr = 0x0102 | UPMA; - - memctl->memc_mdr = 0x3FFFC004; - memctl->memc_mcr = 0x0103 | UPMA; - - memctl->memc_mdr = 0xFFFFDC05; - memctl->memc_mcr = 0x0104 | UPMA; - - /* Initialize UPMB for CAN: single write */ - memctl->memc_mdr = 0xFFFCC004; - memctl->memc_mcr = 0x0118 | UPMA; - - memctl->memc_mdr = 0xCFFCD004; - memctl->memc_mcr = 0x0119 | UPMA; - - memctl->memc_mdr = 0x0FFCC000; - memctl->memc_mcr = 0x011A | UPMA; - - memctl->memc_mdr = 0x7FFCC004; - memctl->memc_mcr = 0x011B | UPMA; - - memctl->memc_mdr = 0xFFFDCC05; - memctl->memc_mcr = 0x011C | UPMA; -#endif /* CONFIG_CAN_DRIVER */ - - return (dram_size()); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Find size of RAM from configuration pins. - * The input pins that contain the memory size are also the debug port - * pins. Normally they are configured as debug port pins. To be able - * to read the memory configuration, we must deactivate the debug port - * and enable the pcmcia input pins. Then return the register to - * previous state. - */ - -static long int dram_size () -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile sysconf8xx_t *siu = &immap->im_siu_conf; - volatile pcmconf8xx_t *pcm = &immap->im_pcmcia; - long int i, memory=1; - unsigned long siu_mcr; - - siu_mcr = siu->sc_siumcr; - siu->sc_siumcr = siu_mcr & 0xFF9FFFFF; - for(i=0; i<10; i++) i = i; - - memory = (pcm->pcmc_pipr>>12) & 0x3; - - siu->sc_siumcr = siu_mcr; - - switch( memory ) - { - case 1: - return( 32*MBYTE ); - case 2: - return( 64*MBYTE ); - default: - break; - } - return( 16*MBYTE ); -} diff --git a/board/zpc1900/Makefile b/board/zpc1900/Makefile deleted file mode 100644 index e636365777..0000000000 --- a/board/zpc1900/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := zpc1900.o diff --git a/board/zpc1900/zpc1900.c b/board/zpc1900/zpc1900.c deleted file mode 100644 index fed4934afd..0000000000 --- a/board/zpc1900/zpc1900.c +++ /dev/null @@ -1,288 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003-2005 Arabella Software Ltd. - * Yuli Barcohen <yuli@arabellasw.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> -#include <miiphy.h> - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN CLSN */ - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */ - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RENA */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT972 MDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT972 MDIO */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -#ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE -void *nvram_read(void *dest, long src, size_t count) -{ - return memcpy(dest, (const void *)src, count); -} - -void nvram_write(long dest, const void *src, size_t count) -{ - vu_char *p1 = (vu_char *)(CONFIG_SYS_EEPROM + 0x1555); - vu_char *p2 = (vu_char *)(CONFIG_SYS_EEPROM + 0x0AAA); - vu_char *d = (vu_char *)dest; - const uchar *s = (const uchar *)src; - - /* Unprotect the EEPROM */ - *p1 = 0xAA; - *p2 = 0x55; - *p1 = 0x80; - *p1 = 0xAA; - *p2 = 0x55; - *p1 = 0x20; - udelay(10000); - - /* Write the data to the EEPROM */ - while (count--) { - *d++ = *s++; - while (*(d - 1) != *(s - 1)) - /* wait */; - } - - /* Protect the EEPROM */ - *p1 = 0xAA; - *p2 = 0x55; - *p1 = 0xA0; - udelay(10000); -} -#endif /* CONFIG_SYS_NVRAM_ACCESS_ROUTINE */ - -phys_size_t initdram(int board_type) -{ - vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - vu_char *ramaddr; - uchar c = 0xFF; - long int msize = CONFIG_SYS_SDRAM_SIZE; - int i; - - if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */ - immap->im_clkrst.car_sccr |= SCCR_PCI_MODE; - immap->im_siu_conf.sc_siumcr = - (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) - | SIUMCR_LBPC01; - } - -#ifndef CONFIG_SYS_RAMBOOT - immap->im_siu_conf.sc_ppc_acr = 0x03; - immap->im_siu_conf.sc_ppc_alrh = 0x30126745; - immap->im_siu_conf.sc_tescr1 = 0x00004000; - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#ifdef CONFIG_SYS_LSDRAM_BASE - /* - Initialise local bus SDRAM only if the pins - are configured as local bus pins and not as PCI. - */ - if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) { - memctl->memc_lsrt = CONFIG_SYS_LSRT; - memctl->memc_or4 = CONFIG_SYS_LSDRAM_OR; - memctl->memc_br4 = CONFIG_SYS_LSDRAM_BR; - ramaddr = (vu_char *)CONFIG_SYS_LSDRAM_BASE; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_PREA; - *ramaddr = c; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_MRW; - *ramaddr = c; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_RFEN; - } -#endif /* CONFIG_SYS_LSDRAM_BASE */ - - /* Initialise 60x bus SDRAM */ - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_or2 = CONFIG_SYS_PSDRAM_OR; - memctl->memc_br2 = CONFIG_SYS_PSDRAM_BR; - /* - * The mode data for Mode Register Write command must appear on - * the address lines during a mode-set cycle. It is driven by - * the memory controller, in single PowerQUICC II mode, - * according to PSDMR[CL] and PSDMR[BL] fields. In - * 60x-compatible mode, software must drive the correct value on - * the address lines. BL=0 because for 64-bit port size burst - * length must be 4. - */ - ramaddr = (vu_char *)(CONFIG_SYS_SDRAM_BASE | - ((CONFIG_SYS_PSDMR & PSDMR_CL_MSK) << 7) | 0x10); - memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */ - *ramaddr = c; - memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */ - for (i = 0; i < 8; i++) - *ramaddr = c; - memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_MRW; /* Mode Register write */ - *ramaddr = c; - memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_RFEN; /* Refresh enable */ - *ramaddr = c; -#endif /* CONFIG_SYS_RAMBOOT */ - - /* Return total 60x bus SDRAM size */ - return msize * 1024 * 1024; -} - -int checkboard(void) -{ - vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; - - printf("Board: Zephyr ZPC.1900 Rev. %c\n", bcsr[2] + 0x40); - return 0; -} |