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authorTom Rini <trini@konsulko.com>2018-05-30 08:43:04 -0400
committerTom Rini <trini@konsulko.com>2018-05-30 08:43:04 -0400
commit964d4f7211ec85b890e852d0226adba0b4f8c1c9 (patch)
tree7b682f156a9bde3b9c3d82a184091bd4445f15cd /doc/README.AX25
parent9c2369a554437f072733c53ba0f5f5384f35b6d3 (diff)
parent6ffea11b89099d72029bc644f7664736ee7ca667 (diff)
Merge git://git.denx.de/u-boot-riscv
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+AX25 is Andes CPU IP to adopt RISC-V architecture.
+
+Features
+========
+
+CPU Core
+ - 5-stage in-order execution pipeline
+ - Hardware Multiplier
+ - radix-2/radix-4/radix-16/radix-256/fast
+ - Hardware Divider
+ - Optional branch prediction
+ - Machine mode and optional user mode
+ - Optional performance monitoring
+
+ISA
+ - RV64I base integer instructions
+ - RVC for 16-bit compressed instructions
+ - RVM for multiplication and division instructions
+
+Memory subsystem
+ - I & D local memory
+ - Size: 4KB to 16MB
+ - Memory subsyetem soft-error protection
+ - Protection scheme: parity-checking or error-checking-and-correction (ECC)
+ - Automatic hardware error correction
+
+Bus
+ - Interface Protocol
+ - Synchronous AHB (32-bit/64-bit data-width), or
+ - Synchronous AXI4 (64-bit data-width)
+
+Power management
+ - Wait for interrupt (WFI) mode
+
+Debug
+ - Configurable number of breakpoints: 2/4/8
+ - External Debug Module
+ - AHB slave port
+ - External JTAG debug transport module
+
+Platform Level Interrupt Controller (PLIC)
+ - AHB slave port
+ - Configurable number of interrupts: 1-1023
+ - Configurable number of interrupt priorities: 3/7/15/63/127/255
+ - Configurable number of targets: 1-16
+ - Preempted interrupt priority stack