diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2019-05-22 00:09:44 -0700 |
|---|---|---|
| committer | Joe Hershberger <joe.hershberger@ni.com> | 2019-06-01 13:33:17 -0500 |
| commit | 49191d259f433f8341a71ab6f821c1d89e2f5092 (patch) | |
| tree | 351793b9b2eaab40e8563d018ed53fe0c3d051ad /drivers/clk/sifive/Kconfig | |
| parent | 379af67ab3ba1a16e032c8d082fe85efa4bf21fe (diff) | |
clk: sifive: Add clock driver for GEMGXL MGMT
This adds a clock driver to support the GEMGXL management IP block
found in FU540 SoCs to control GEM TX clock operation mode for
10/100/1000 Mbps.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Diffstat (limited to 'drivers/clk/sifive/Kconfig')
| -rw-r--r-- | drivers/clk/sifive/Kconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig index 81fc9f8fda..644881b948 100644 --- a/drivers/clk/sifive/Kconfig +++ b/drivers/clk/sifive/Kconfig @@ -17,3 +17,10 @@ config CLK_SIFIVE_FU540_PRCI Supports the Power Reset Clock interface (PRCI) IP block found in FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC, enable this driver. + +config CLK_SIFIVE_GEMGXL_MGMT + bool "GEMGXL management for SiFive FU540 SoCs" + depends on CLK_SIFIVE + help + Supports the GEMGXL management IP block found in FU540 SoCs to + control GEM TX clock operation mode for 10/100/1000 Mbps. |