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authorPeng Fan <peng.fan@nxp.com>2018-10-18 14:28:28 +0200
committerStefano Babic <sbabic@denx.de>2018-10-22 12:59:01 +0200
commit38b6686f05d4609334b5796bc352ec01d54c5eb4 (patch)
treec59f1ed1d46669c6342c840ab025f42d8cbc8e76 /drivers/pinctrl/nxp/pinctrl-scu.c
parent8b2a31f13362521e65ccb4c7d73db467068e8e6a (diff)
pinctrl: Add pinctrl driver for i.MX8
Add pinctrl driver for i.MX8. The pads configuration is controlled by SCU, so need to ask SCU to configure pads through scfw API. Add pinctrl-scu to invoke sc_pad_set to configure pads. Add a new flag IMX8_USE_SCU to differentiate i.MX8 from other platforms which could directly configure pads from Acore side. Add CONFIG_PINCTRL_IMX8 as the built gate. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'drivers/pinctrl/nxp/pinctrl-scu.c')
-rw-r--r--drivers/pinctrl/nxp/pinctrl-scu.c66
1 files changed, 66 insertions, 0 deletions
diff --git a/drivers/pinctrl/nxp/pinctrl-scu.c b/drivers/pinctrl/nxp/pinctrl-scu.c
new file mode 100644
index 0000000000..aa11075e0a
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-scu.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <linux/bitops.h>
+#include <asm/io.h>
+#include <asm/arch/sci/sci.h>
+#include <misc.h>
+
+#include "pinctrl-imx.h"
+
+#define PADRING_IFMUX_EN_SHIFT 31
+#define PADRING_IFMUX_EN_MASK BIT(31)
+#define PADRING_GP_EN_SHIFT 30
+#define PADRING_GP_EN_MASK BIT(30)
+#define PADRING_IFMUX_SHIFT 27
+#define PADRING_IFMUX_MASK GENMASK(29, 27)
+
+static int imx_pinconf_scu_set(struct imx_pinctrl_soc_info *info, u32 pad,
+ u32 mux, u32 val)
+{
+ int ret;
+
+ /*
+ * Mux should be done in pmx set, but we do not have a good api
+ * to handle that in scfw, so config it in pad conf func
+ */
+
+ val |= PADRING_IFMUX_EN_MASK;
+ val |= PADRING_GP_EN_MASK;
+ val |= (mux << PADRING_IFMUX_SHIFT) & PADRING_IFMUX_MASK;
+
+ ret = sc_pad_set(-1, pad, val);
+ if (ret)
+ printf("%s %d\n", __func__, ret);
+
+ return 0;
+}
+
+int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info, u32 *pin_data,
+ int npins)
+{
+ int pin_id, mux, config_val;
+ int i, j = 0;
+ int ret;
+
+ /*
+ * Refer to linux documentation for details:
+ * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
+ */
+ for (i = 0; i < npins; i++) {
+ pin_id = pin_data[j++];
+ mux = pin_data[j++];
+ config_val = pin_data[j++];
+
+ ret = imx_pinconf_scu_set(info, pin_id, mux, config_val);
+ if (ret)
+ printf("Set pin %d, mux %d, val %d, error\n", pin_id,
+ mux, config_val);
+ }
+
+ return 0;
+}