diff options
| author | Ruslan Bilovol <ruslan.bilovol@gmail.com> | 2018-03-01 03:15:48 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-03-16 09:42:38 -0400 |
| commit | 87c692cbc17bc987c8a5f8c0377d8326348786ea (patch) | |
| tree | e0b0c2549d2b35c6a69a9462408fdfc254f8662a /drivers/watchdog | |
| parent | fc228dc96c64674bc6fc85635708eb39708fafc4 (diff) | |
watchdog: omap_wdt: improve watchdog reset path
Remove busy looping during watchdog reset.
Each polling of W_PEND_WTGR bit ("finish posted
write") after watchdog reset takes 120-140us
on BeagleBone Black board. Current U-Boot code
has watchdog resets in random places and often
there is situation when watchdog is reset
few times in a row in nested functions.
This adds extra delays and slows the whole system.
Instead of polling W_PEND_WTGR bit, we skip
watchdog reset if the bit is set. Anyway, watchdog
is in the middle of reset *right now*, so we can
just return.
This noticeably increases performance of the
system. Below are some measurements on BBB:
- DFU upload over USB 15% faster
- fastboot image upload 3x times faster
- USB ep0 transfers with 4k packets 20% faster
Signed-off-by: Ruslan Bilovol <ruslan.bilovol@gmail.com>
Tested-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Alex Kiernan <alex.kiernan@gmail.com>
Diffstat (limited to 'drivers/watchdog')
| -rw-r--r-- | drivers/watchdog/omap_wdt.c | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index 7b1f429432..d724c964ed 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c @@ -53,16 +53,25 @@ void hw_watchdog_reset(void) { struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; - /* wait for posted write to complete */ - while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR) - ; + /* + * Somebody just triggered watchdog reset and write to WTGR register + * is in progress. It is resetting right now, no need to trigger it + * again + */ + if ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR) + return; wdt_trgr_pattern = ~wdt_trgr_pattern; writel(wdt_trgr_pattern, &wdt->wdtwtgr); - /* wait for posted write to complete */ - while ((readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WTGR)) - ; + /* + * Don't wait for posted write to complete, i.e. don't check + * WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to + * WTGR register outside of this func, and if entering it + * we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset + * was just triggered. This prevents us from wasting time in busy + * polling of WDT_WWPS_PEND_WTGR bit. + */ } static int omap_wdt_set_timeout(unsigned int timeout) |