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authorDavid Wu <david.wu@rock-chips.com>2018-01-13 14:02:07 +0800
committerPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>2018-01-28 17:12:37 +0100
commitdfb886d4f2ef5c915ad13144c502c26c8d9d8517 (patch)
tree6cf62f13236a536be3269748a1c194de69b5ffd5 /drivers
parent301fff4e574d373a139dd47aceabc5b4259873da (diff)
rockchip: pinctrl: Add rk3328 gmac pinctrl support
Need to set gmac m1 pins iomux, gmac m0 tx pins, select bit2 and bit10 at com iomux register. After that, set rgmii m1 tx pins to 12ma drive-strength, and clean others to 2ma. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pinctrl/rockchip/pinctrl_rk3328.c275
1 files changed, 275 insertions, 0 deletions
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
index 3c2253fdaf..fa2356a7a1 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
@@ -31,6 +31,37 @@ enum {
GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT,
GPIO0A7_EMMC_DATA0 = 2,
+ /* GPIO0B_IOMUX*/
+ GPIO0B0_SEL_SHIFT = 0,
+ GPIO0B0_SEL_MASK = 3 << GPIO0B0_SEL_SHIFT,
+ GPIO0B0_GAMC_CLKTXM0 = 1,
+
+ GPIO0B4_SEL_SHIFT = 8,
+ GPIO0B4_SEL_MASK = 3 << GPIO0B4_SEL_SHIFT,
+ GPIO0B4_GAMC_TXENM0 = 1,
+
+ /* GPIO0C_IOMUX*/
+ GPIO0C0_SEL_SHIFT = 0,
+ GPIO0C0_SEL_MASK = 3 << GPIO0C0_SEL_SHIFT,
+ GPIO0C0_GAMC_TXD1M0 = 1,
+
+ GPIO0C1_SEL_SHIFT = 2,
+ GPIO0C1_SEL_MASK = 3 << GPIO0C1_SEL_SHIFT,
+ GPIO0C1_GAMC_TXD0M0 = 1,
+
+ GPIO0C6_SEL_SHIFT = 12,
+ GPIO0C6_SEL_MASK = 3 << GPIO0C6_SEL_SHIFT,
+ GPIO0C6_GAMC_TXD2M0 = 1,
+
+ GPIO0C7_SEL_SHIFT = 14,
+ GPIO0C7_SEL_MASK = 3 << GPIO0C7_SEL_SHIFT,
+ GPIO0C7_GAMC_TXD3M0 = 1,
+
+ /* GPIO0D_IOMUX*/
+ GPIO0D0_SEL_SHIFT = 0,
+ GPIO0D0_SEL_MASK = 3 << GPIO0D0_SEL_SHIFT,
+ GPIO0D0_GMAC_CLKM0 = 1,
+
GPIO0D6_SEL_SHIFT = 12,
GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT,
GPIO0D6_GPIO = 0,
@@ -41,6 +72,69 @@ enum {
GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT,
GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555,
+ /* GPIO1B_IOMUX */
+ GPIO1B0_SEL_SHIFT = 0,
+ GPIO1B0_SEL_MASK = 3 << GPIO1B0_SEL_SHIFT,
+ GPIO1B0_GMAC_TXD1M1 = 2,
+
+ GPIO1B1_SEL_SHIFT = 2,
+ GPIO1B1_SEL_MASK = 3 << GPIO1B1_SEL_SHIFT,
+ GPIO1B1_GMAC_TXD0M1 = 2,
+
+ GPIO1B2_SEL_SHIFT = 4,
+ GPIO1B2_SEL_MASK = 3 << GPIO1B2_SEL_SHIFT,
+ GPIO1B2_GMAC_RXD1M1 = 2,
+
+ GPIO1B3_SEL_SHIFT = 6,
+ GPIO1B3_SEL_MASK = 3 << GPIO1B3_SEL_SHIFT,
+ GPIO1B3_GMAC_RXD0M1 = 2,
+
+ GPIO1B4_SEL_SHIFT = 8,
+ GPIO1B4_SEL_MASK = 3 << GPIO1B4_SEL_SHIFT,
+ GPIO1B4_GMAC_TXCLKM1 = 2,
+
+ GPIO1B5_SEL_SHIFT = 10,
+ GPIO1B5_SEL_MASK = 3 << GPIO1B5_SEL_SHIFT,
+ GPIO1B5_GMAC_RXCLKM1 = 2,
+
+ GPIO1B6_SEL_SHIFT = 12,
+ GPIO1B6_SEL_MASK = 3 << GPIO1B6_SEL_SHIFT,
+ GPIO1B6_GMAC_RXD3M1 = 2,
+
+ GPIO1B7_SEL_SHIFT = 14,
+ GPIO1B7_SEL_MASK = 3 << GPIO1B7_SEL_SHIFT,
+ GPIO1B7_GMAC_RXD2M1 = 2,
+
+ /* GPIO1C_IOMUX */
+ GPIO1C0_SEL_SHIFT = 0,
+ GPIO1C0_SEL_MASK = 3 << GPIO1C0_SEL_SHIFT,
+ GPIO1C0_GMAC_TXD3M1 = 2,
+
+ GPIO1C1_SEL_SHIFT = 2,
+ GPIO1C1_SEL_MASK = 3 << GPIO1C1_SEL_SHIFT,
+ GPIO1C1_GMAC_TXD2M1 = 2,
+
+ GPIO1C3_SEL_SHIFT = 6,
+ GPIO1C3_SEL_MASK = 3 << GPIO1C3_SEL_SHIFT,
+ GPIO1C3_GMAC_MDIOM1 = 2,
+
+ GPIO1C5_SEL_SHIFT = 10,
+ GPIO1C5_SEL_MASK = 3 << GPIO1C5_SEL_SHIFT,
+ GPIO1C5_GMAC_CLKM1 = 2,
+
+ GPIO1C6_SEL_SHIFT = 12,
+ GPIO1C6_SEL_MASK = 3 << GPIO1C6_SEL_SHIFT,
+ GPIO1C6_GMAC_RXDVM1 = 2,
+
+ GPIO1C7_SEL_SHIFT = 14,
+ GPIO1C7_SEL_MASK = 3 << GPIO1C7_SEL_SHIFT,
+ GPIO1C7_GMAC_MDCM1 = 2,
+
+ /* GPIO1D_IOMUX */
+ GPIO1D1_SEL_SHIFT = 2,
+ GPIO1D1_SEL_MASK = 3 << GPIO1D1_SEL_SHIFT,
+ GPIO1D1_GMAC_TXENM1 = 2,
+
/* GPIO2A_IOMUX */
GPIO2A0_SEL_SHIFT = 0,
GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
@@ -118,6 +212,11 @@ enum {
IOMUX_SEL_UART2_M0 = 0,
IOMUX_SEL_UART2_M1,
+ IOMUX_SEL_GMAC_SHIFT = 2,
+ IOMUX_SEL_GMAC_MASK = 1 << IOMUX_SEL_GMAC_SHIFT,
+ IOMUX_SEL_GMAC_M0 = 0,
+ IOMUX_SEL_GMAC_M1,
+
IOMUX_SEL_SPI_SHIFT = 4,
IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT,
IOMUX_SEL_SPI_M0 = 0,
@@ -128,6 +227,55 @@ enum {
IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT,
IOMUX_SEL_SDMMC_M0 = 0,
IOMUX_SEL_SDMMC_M1,
+
+ IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT = 10,
+ IOMUX_SEL_GMACM1_OPTIMIZATION_MASK = 1 << IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT,
+ IOMUX_SEL_GMACM1_OPTIMIZATION_BEFORE = 0,
+ IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER,
+
+ /* GRF_GPIO1B_E */
+ GRF_GPIO1B0_E_SHIFT = 0,
+ GRF_GPIO1B0_E_MASK = 3 << GRF_GPIO1B0_E_SHIFT,
+ GRF_GPIO1B1_E_SHIFT = 2,
+ GRF_GPIO1B1_E_MASK = 3 << GRF_GPIO1B1_E_SHIFT,
+ GRF_GPIO1B2_E_SHIFT = 4,
+ GRF_GPIO1B2_E_MASK = 3 << GRF_GPIO1B2_E_SHIFT,
+ GRF_GPIO1B3_E_SHIFT = 6,
+ GRF_GPIO1B3_E_MASK = 3 << GRF_GPIO1B3_E_SHIFT,
+ GRF_GPIO1B4_E_SHIFT = 8,
+ GRF_GPIO1B4_E_MASK = 3 << GRF_GPIO1B4_E_SHIFT,
+ GRF_GPIO1B5_E_SHIFT = 10,
+ GRF_GPIO1B5_E_MASK = 3 << GRF_GPIO1B5_E_SHIFT,
+ GRF_GPIO1B6_E_SHIFT = 12,
+ GRF_GPIO1B6_E_MASK = 3 << GRF_GPIO1B6_E_SHIFT,
+ GRF_GPIO1B7_E_SHIFT = 14,
+ GRF_GPIO1B7_E_MASK = 3 << GRF_GPIO1B7_E_SHIFT,
+
+ /* GRF_GPIO1C_E */
+ GRF_GPIO1C0_E_SHIFT = 0,
+ GRF_GPIO1C0_E_MASK = 3 << GRF_GPIO1C0_E_SHIFT,
+ GRF_GPIO1C1_E_SHIFT = 2,
+ GRF_GPIO1C1_E_MASK = 3 << GRF_GPIO1C1_E_SHIFT,
+ GRF_GPIO1C3_E_SHIFT = 6,
+ GRF_GPIO1C3_E_MASK = 3 << GRF_GPIO1C3_E_SHIFT,
+ GRF_GPIO1C5_E_SHIFT = 10,
+ GRF_GPIO1C5_E_MASK = 3 << GRF_GPIO1C5_E_SHIFT,
+ GRF_GPIO1C6_E_SHIFT = 12,
+ GRF_GPIO1C6_E_MASK = 3 << GRF_GPIO1C6_E_SHIFT,
+ GRF_GPIO1C7_E_SHIFT = 14,
+ GRF_GPIO1C7_E_MASK = 3 << GRF_GPIO1C7_E_SHIFT,
+
+ /* GRF_GPIO1D_E */
+ GRF_GPIO1D1_E_SHIFT = 2,
+ GRF_GPIO1D1_E_MASK = 3 << GRF_GPIO1D1_E_SHIFT,
+};
+
+/* GPIO Bias drive strength settings */
+enum GPIO_BIAS {
+ GPIO_BIAS_2MA = 0,
+ GPIO_BIAS_4MA,
+ GPIO_BIAS_8MA,
+ GPIO_BIAS_12MA,
};
struct rk3328_pinctrl_priv {
@@ -313,6 +461,124 @@ static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf,
}
}
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+static void pinctrl_rk3328_gmac_config(struct rk3328_grf_regs *grf, int gmac_id)
+{
+ switch (gmac_id) {
+ case PERIPH_ID_GMAC:
+ /* set rgmii m1 pins mux */
+ rk_clrsetreg(&grf->gpio1b_iomux,
+ GPIO1B0_SEL_MASK |
+ GPIO1B1_SEL_MASK |
+ GPIO1B2_SEL_MASK |
+ GPIO1B3_SEL_MASK |
+ GPIO1B4_SEL_MASK |
+ GPIO1B5_SEL_MASK |
+ GPIO1B6_SEL_MASK |
+ GPIO1B7_SEL_MASK,
+ GPIO1B0_GMAC_TXD1M1 << GPIO1B0_SEL_SHIFT |
+ GPIO1B1_GMAC_TXD0M1 << GPIO1B1_SEL_SHIFT |
+ GPIO1B2_GMAC_RXD1M1 << GPIO1B2_SEL_SHIFT |
+ GPIO1B3_GMAC_RXD0M1 << GPIO1B3_SEL_SHIFT |
+ GPIO1B4_GMAC_TXCLKM1 << GPIO1B4_SEL_SHIFT |
+ GPIO1B5_GMAC_RXCLKM1 << GPIO1B5_SEL_SHIFT |
+ GPIO1B6_GMAC_RXD3M1 << GPIO1B6_SEL_SHIFT |
+ GPIO1B7_GMAC_RXD2M1 << GPIO1B7_SEL_SHIFT);
+
+ rk_clrsetreg(&grf->gpio1c_iomux,
+ GPIO1C0_SEL_MASK |
+ GPIO1C1_SEL_MASK |
+ GPIO1C3_SEL_MASK |
+ GPIO1C5_SEL_MASK |
+ GPIO1C6_SEL_MASK |
+ GPIO1C7_SEL_MASK,
+ GPIO1C0_GMAC_TXD3M1 << GPIO1C0_SEL_SHIFT |
+ GPIO1C1_GMAC_TXD2M1 << GPIO1C1_SEL_SHIFT |
+ GPIO1C3_GMAC_MDIOM1 << GPIO1C3_SEL_SHIFT |
+ GPIO1C5_GMAC_CLKM1 << GPIO1C5_SEL_SHIFT |
+ GPIO1C6_GMAC_RXDVM1 << GPIO1C6_SEL_SHIFT |
+ GPIO1C7_GMAC_MDCM1 << GPIO1C7_SEL_SHIFT);
+
+ rk_clrsetreg(&grf->gpio1d_iomux,
+ GPIO1D1_SEL_MASK,
+ GPIO1D1_GMAC_TXENM1 << GPIO1D1_SEL_SHIFT);
+
+ /* set rgmii m0 tx pins mux */
+ rk_clrsetreg(&grf->gpio0b_iomux,
+ GPIO0B0_SEL_MASK |
+ GPIO0B4_SEL_MASK,
+ GPIO0B0_GAMC_CLKTXM0 << GPIO0B0_SEL_SHIFT |
+ GPIO0B4_GAMC_TXENM0 << GPIO0B4_SEL_SHIFT);
+
+ rk_clrsetreg(&grf->gpio0c_iomux,
+ GPIO0C0_SEL_MASK |
+ GPIO0C1_SEL_MASK |
+ GPIO0C6_SEL_MASK |
+ GPIO0C7_SEL_MASK,
+ GPIO0C0_GAMC_TXD1M0 << GPIO0C0_SEL_SHIFT |
+ GPIO0C1_GAMC_TXD0M0 << GPIO0C1_SEL_SHIFT |
+ GPIO0C6_GAMC_TXD2M0 << GPIO0C6_SEL_SHIFT |
+ GPIO0C7_GAMC_TXD3M0 << GPIO0C7_SEL_SHIFT);
+
+ rk_clrsetreg(&grf->gpio0d_iomux,
+ GPIO0D0_SEL_MASK,
+ GPIO0D0_GMAC_CLKM0 << GPIO0D0_SEL_SHIFT);
+
+ /* set com mux */
+ rk_clrsetreg(&grf->com_iomux,
+ IOMUX_SEL_GMAC_MASK |
+ IOMUX_SEL_GMACM1_OPTIMIZATION_MASK,
+ IOMUX_SEL_GMAC_M1 << IOMUX_SEL_GMAC_SHIFT |
+ IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER <<
+ IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT);
+
+ /*
+ * set rgmii m1 tx pins to 12ma drive-strength,
+ * and clean others to 2ma.
+ */
+ rk_clrsetreg(&grf->gpio1b_e,
+ GRF_GPIO1B0_E_MASK |
+ GRF_GPIO1B1_E_MASK |
+ GRF_GPIO1B2_E_MASK |
+ GRF_GPIO1B3_E_MASK |
+ GRF_GPIO1B4_E_MASK |
+ GRF_GPIO1B5_E_MASK |
+ GRF_GPIO1B6_E_MASK |
+ GRF_GPIO1B7_E_MASK,
+ GPIO_BIAS_12MA << GRF_GPIO1B0_E_SHIFT |
+ GPIO_BIAS_12MA << GRF_GPIO1B1_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1B2_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1B3_E_SHIFT |
+ GPIO_BIAS_12MA << GRF_GPIO1B4_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1B5_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1B6_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1B7_E_SHIFT);
+
+ rk_clrsetreg(&grf->gpio1c_e,
+ GRF_GPIO1C0_E_MASK |
+ GRF_GPIO1C1_E_MASK |
+ GRF_GPIO1C3_E_MASK |
+ GRF_GPIO1C5_E_MASK |
+ GRF_GPIO1C6_E_MASK |
+ GRF_GPIO1C7_E_MASK,
+ GPIO_BIAS_12MA << GRF_GPIO1C0_E_SHIFT |
+ GPIO_BIAS_12MA << GRF_GPIO1C1_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1C3_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1C5_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1C6_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1C7_E_SHIFT);
+
+ rk_clrsetreg(&grf->gpio1d_e,
+ GRF_GPIO1D1_E_MASK,
+ GPIO_BIAS_12MA << GRF_GPIO1D1_E_SHIFT);
+ break;
+ default:
+ debug("gmac id = %d iomux error!\n", gmac_id);
+ break;
+ }
+}
+#endif
+
static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags)
{
struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
@@ -349,6 +615,11 @@ static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags)
case PERIPH_ID_SDMMC1:
pinctrl_rk3328_sdmmc_config(priv->grf, func);
break;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+ case PERIPH_ID_GMAC:
+ pinctrl_rk3328_gmac_config(priv->grf, func);
+ break;
+#endif
default:
return -EINVAL;
}
@@ -383,6 +654,10 @@ static int rk3328_pinctrl_get_periph_id(struct udevice *dev,
return PERIPH_ID_SDCARD;
case 14:
return PERIPH_ID_EMMC;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+ case 24:
+ return PERIPH_ID_GMAC;
+#endif
}
return -ENOENT;