Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm:
  run arm_pci_init after relocation
  IXP42x PCI rewrite
  update/fix PDNB3 board
  update/fix IXDP425 / IXDPG425 boards
  add dvlhost (dLAN 200 AV Wireless G) board
  IXP NPE: add support for fixed-speed MII ports
  update/fix AcTux4 board
  update/fix AcTux3 board
  update/fix AcTux2 board
  update/fix AcTux1 board
  use -ffunction-sections / --gc-sections on IXP42x
  support CONFIG_SYS_LDSCRIPT on ARM
  fix "depend" target in npe directory
  Fix IXP code to work after relocation was added
  trigger hardware watchdog in IXP42x serial driver
  add support for IXP42x Rev. B1 and newer
  add XScale sub architecture (IXP/PXA) to maintainer list

Conflicts:
	arch/arm/lib/board.c

Signed-off-by: Wolfgang Denk <wd@denx.de>

8 files changed, 507 insertions, 131 deletions

diff --git a/include/configs/actux1.h b/include/configs/actux1.h
index 8121b27229..160c10af29 100644
--- a/include/configs/actux1.h
+++ b/include/configs/actux1.h
@@ -26,13 +26,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/* 1: modified board with 32MB DRAM */
-#define CONFIG_ACTUX1_32MB		0
-/* 1: 2*2MB FLASH (standard) */
-#define CONFIG_ACTUX1_FLASH2X2		1
-/* 1: 1*8MB FLASH (upgraded boards) */
-#define CONFIG_ACTUX1_FLASH1X8		0
-
 #define CONFIG_IXP425			1
 #define CONFIG_ACTUX1			1
 
@@ -44,12 +37,12 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_BOARD_EARLY_INIT_F	1
+#define CONFIG_SYS_LDSCRIPT	"board/actux1/u-boot.lds"
 
 /***************************************************************
  * U-boot generic defines start here.
  ***************************************************************/
-#undef CONFIG_USE_IRQ
-
 /*
  * Size of malloc() pool
  */
@@ -62,8 +55,13 @@
 #include <config_cmd_default.h>
 
 #define CONFIG_CMD_ELF
-#undef CONFIG_CMD_PCI
-#undef CONFIG_PCI
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_IXP_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI_ENUM
+#endif
 
 #define CONFIG_BOOTCOMMAND		"run boot_flash"
 /* enable passing of ATAGs */
@@ -93,8 +91,9 @@
 #define CONFIG_SYS_MEMTEST_START		0x00400000
 #define CONFIG_SYS_MEMTEST_END			0x00800000
 
-/* spec says 66.666 MHz, but it appears to be 33 */
-#define CONFIG_SYS_HZ				3333333
+/* timer clock - 2* OSC_IN system clock */
+#define CONFIG_IXP425_TIMER_CLK                 66666666
+#define CONFIG_SYS_HZ				1000
 
 /* default load address */
 #define CONFIG_SYS_LOAD_ADDR			0x00010000
@@ -109,10 +108,6 @@
  * The stack sizes are set up in start.S using the settings below
  */
 #define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-# define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
-# define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
-#endif
 
 /* Expansion bus settings */
 #define CONFIG_SYS_EXP_CS0			0xbd113842
@@ -120,9 +115,9 @@
 /* SDRAM settings */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM_1			0x00000000
-#define CONFIG_SYS_DRAM_BASE			0x00000000
+#define CONFIG_SYS_SDRAM_BASE			0x00000000
 
-#if CONFIG_ACTUX1_32MB
+#ifdef CONFIG_RAM_32MB
 # define CONFIG_SYS_SDR_CONFIG			0x18
 # define PHYS_SDRAM_1_SIZE		0x02000000
 # define CONFIG_SYS_SDRAM_REFRESH_CNT		0x81a
@@ -136,8 +131,11 @@
 # define CONFIG_SYS_DRAM_SIZE			0x01000000
 #endif
 
+
+
 /* FLASH organization */
-#if CONFIG_ACTUX1_FLASH2X2
+#define CONFIG_SYS_TEXT_BASE		0x50000000
+#ifdef CONFIG_FLASH2X2
 # define CONFIG_SYS_MAX_FLASH_BANKS		2
 /* max number of sectors on one chip */
 # define CONFIG_SYS_MAX_FLASH_SECT		40
@@ -145,7 +143,7 @@
 # define PHYS_FLASH_2			0x50200000
 # define CONFIG_SYS_FLASH_BANKS_LIST		{ PHYS_FLASH_1, PHYS_FLASH_2 }
 #endif
-#if CONFIG_ACTUX1_FLASH1X8
+#ifdef CONFIG_FLASH1X8
 # define CONFIG_SYS_MAX_FLASH_BANKS		1
 /* max number of sectors on one chip */
 # define CONFIG_SYS_MAX_FLASH_SECT		140
@@ -156,6 +154,7 @@
 #define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_LEN			(256 << 10)
+#define CONFIG_BOARD_SIZE_LIMIT			262144
 
 /* Use common CFI driver */
 #define CONFIG_SYS_FLASH_CFI
@@ -172,12 +171,16 @@
 #define CONFIG_NET_MULTI		1
 /* NPE0 PHY address */
 #define	CONFIG_PHY_ADDR			0
+/* NPE1 PHY address (HW Release E only) */
+#define	CONFIG_PHY1_ADDR		1
 /* MII PHY management */
 #define CONFIG_MII			1
 /* Number of ethernet rx buffers & descriptors */
 #define CONFIG_SYS_RX_ETH_BUFFER		16
 #define CONFIG_RESET_PHY_R		1
 
+#define CONFIG_HAS_ETH1			1
+
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_MII
@@ -202,17 +205,19 @@
 #define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x4000)
 #define CONFIG_SYS_USE_PPCENV			1
 
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CONFIG_EXTRA_ENV_SETTINGS					\
 	"npe_ucode=50040000\0"						\
 	"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
 	"kerneladdr=50050000\0"						\
+	"kernelfile=actux1/uImage\0"					\
+	"rootfile=actux1/rootfs\0"					\
 	"rootaddr=50170000\0"						\
 	"loadaddr=10000\0"						\
 	"updateboot_ser=mw.b 10000 ff 40000;"				\
 	" loady ${loadaddr};"						\
 	" run eraseboot writeboot\0"					\
 	"updateboot_net=mw.b 10000 ff 40000;"				\
-	" tftp ${loadaddr} u-boot.bin;"					\
+	" tftp ${loadaddr} actux1/u-boot.bin;"				\
 	" run eraseboot writeboot\0"					\
 	"eraseboot=protect off 50000000 50003fff;"			\
 	" protect off 50006000 5003ffff;"				\
@@ -220,8 +225,9 @@
 	" erase 50006000 5003ffff\0"					\
 	"writeboot=cp.b 10000 50000000 4000;"				\
 	" cp.b 16000 50006000 3a000\0"					\
-	"eraseenv=protect off 50004000 50005fff;"			\
-	" erase 50004000 50005fff\0"					\
+	"updateucode=loady;"						\
+	" era ${npe_ucode} +${filesize};"				\
+	" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0"			\
 	"updateroot=tftp ${loadaddr} ${rootfile};"			\
 	" era ${rootaddr} +${filesize};"				\
 	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
@@ -232,7 +238,7 @@
 	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
 	"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3"	\
 	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \
 	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
 	"boot_flash=run flashargs addtty addeth;"			\
 	" bootm ${kerneladdr}\0"					\
@@ -240,4 +246,8 @@
 	" tftpboot ${loadaddr} ${kernelfile};"				\
 	" bootm\0"
 
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_INIT_SP_ADDR						\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/actux2.h b/include/configs/actux2.h
index 8ab3b19933..eca814b3ee 100644
--- a/include/configs/actux2.h
+++ b/include/configs/actux2.h
@@ -37,12 +37,12 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_BOOTDELAY		5
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_BOARD_EARLY_INIT_F	1
+#define CONFIG_SYS_LDSCRIPT	"board/actux2/u-boot.lds"
 
 /***************************************************************
  * U-boot generic defines start here.
  ***************************************************************/
-#undef CONFIG_USE_IRQ
-
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
 
@@ -84,8 +84,9 @@
 #define CONFIG_SYS_MEMTEST_START		0x00400000
 #define CONFIG_SYS_MEMTEST_END			0x00800000
 
-/* spec says 66.666 MHz, but it appears to be 33 */
-#define CONFIG_SYS_HZ				3333333
+/* timer clock - 2* OSC_IN system clock */
+#define CONFIG_IXP425_TIMER_CLK                 66666666
+#define CONFIG_SYS_HZ				1000
 
 /* default load address */
 #define CONFIG_SYS_LOAD_ADDR			0x00010000
@@ -100,10 +101,6 @@
  * The stack sizes are set up in start.S using the settings below
  */
 #define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-# define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
-# define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
-#endif
 
 /* Expansion bus settings */
 #define CONFIG_SYS_EXP_CS0			0xbd113042
@@ -111,7 +108,7 @@
 /* SDRAM settings */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM_1			0x00000000
-#define CONFIG_SYS_DRAM_BASE			0x00000000
+#define CONFIG_SYS_SDRAM_BASE			0x00000000
 
 /* 16MB SDRAM */
 #define CONFIG_SYS_SDR_CONFIG			0x3A
@@ -121,6 +118,7 @@
 #define CONFIG_SYS_DRAM_SIZE			0x01000000
 
 /* FLASH organization */
+#define CONFIG_SYS_TEXT_BASE		0x50000000
 #define CONFIG_SYS_MAX_FLASH_BANKS		1
 /* max number of sectors on one chip */
 #define CONFIG_SYS_MAX_FLASH_SECT		140
@@ -130,6 +128,7 @@
 #define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_LEN			(256 << 10)
+#define CONFIG_BOARD_SIZE_LIMIT			262144
 
 /* Use common CFI driver */
 #define CONFIG_SYS_FLASH_CFI
@@ -149,6 +148,11 @@
 #define	CONFIG_PHY_ADDR			0x00
 /* MII PHY management */
 #define CONFIG_MII			1
+/* fixed-speed switch without standard PHY registers on MII */
+#define CONFIG_MII_NPE0_FIXEDLINK       1
+#define CONFIG_MII_NPE0_SPEED           100
+#define CONFIG_MII_NPE0_FULLDUPLEX      1
+
 /* Number of ethernet rx buffers & descriptors */
 #define CONFIG_SYS_RX_ETH_BUFFER		16
 #define CONFIG_RESET_PHY_R		1
@@ -183,13 +187,15 @@
 	"npe_ucode=50040000\0"						\
 	"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
 	"kerneladdr=50050000\0"						\
+	"kernelfile=actux2/uImage\0"					\
+	"rootfile=actux2/rootfs\0"					\
 	"rootaddr=50170000\0"						\
 	"loadaddr=10000\0"						\
 	"updateboot_ser=mw.b 10000 ff 40000;"				\
 	" loady ${loadaddr};"						\
 	" run eraseboot writeboot\0"					\
 	"updateboot_net=mw.b 10000 ff 40000;"				\
-	" tftp ${loadaddr} u-boot.bin;"					\
+	" tftp ${loadaddr} actux2/u-boot.bin;"				\
 	" run eraseboot writeboot\0"					\
 	"eraseboot=protect off 50000000 50003fff;"			\
 	" protect off 50006000 5003ffff;"				\
@@ -197,8 +203,9 @@
 	" erase 50006000 5003ffff\0"					\
 	"writeboot=cp.b 10000 50000000 4000;"				\
 	" cp.b 16000 50006000 3a000\0"					\
-	"eraseenv=protect off 50004000 50005fff;"			\
-	" erase 50004000 50005fff\0"					\
+	"updateucode=loady;"						\
+	" era ${npe_ucode} +${filesize};"				\
+	" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0"			\
 	"updateroot=tftp ${loadaddr} ${rootfile};"			\
 	" era ${rootaddr} +${filesize};"				\
 	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
@@ -217,4 +224,8 @@
 	" tftpboot ${loadaddr} ${kernelfile};"				\
 	" bootm\0"
 
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_INIT_SP_ADDR						\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/actux3.h b/include/configs/actux3.h
index 91987cbce5..c103312402 100644
--- a/include/configs/actux3.h
+++ b/include/configs/actux3.h
@@ -37,12 +37,12 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_BOARD_EARLY_INIT_F	1
+#define CONFIG_SYS_LDSCRIPT	"board/actux3/u-boot.lds"
 
 /***************************************************************
  * U-boot generic defines start here.
  ***************************************************************/
-#undef CONFIG_USE_IRQ
-
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
 
@@ -82,8 +82,9 @@
 #define CONFIG_SYS_MEMTEST_START		0x00400000
 #define CONFIG_SYS_MEMTEST_END			0x00800000
 
-/* spec says 66.666 MHz, but it appears to be 33 */
-#define CONFIG_SYS_HZ				3333333
+/* timer clock - 2* OSC_IN system clock */
+#define CONFIG_IXP425_TIMER_CLK                 66666666
+#define CONFIG_SYS_HZ				1000
 
 /* default load address */
 #define CONFIG_SYS_LOAD_ADDR			0x00010000
@@ -99,10 +100,6 @@
  * The stack sizes are set up in start.S using the settings below
  */
 #define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-# define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
-# define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
-#endif
 
 /* Expansion bus settings */
 #define CONFIG_SYS_EXP_CS0			0xbd113442
@@ -110,7 +107,7 @@
 /* SDRAM settings */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM_1			0x00000000
-#define CONFIG_SYS_DRAM_BASE			0x00000000
+#define CONFIG_SYS_SDRAM_BASE			0x00000000
 
 /* 16MB SDRAM */
 #define CONFIG_SYS_SDR_CONFIG			0x3A
@@ -120,6 +117,7 @@
 #define CONFIG_SYS_DRAM_SIZE			0x01000000
 
 /* FLASH organization */
+#define CONFIG_SYS_TEXT_BASE		0x50000000
 #define CONFIG_SYS_MAX_FLASH_BANKS		1
 /* max number of sectors on one chip */
 #define CONFIG_SYS_MAX_FLASH_SECT		140
@@ -129,6 +127,7 @@
 #define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_LEN			(256 << 10)
+#define CONFIG_BOARD_SIZE_LIMIT			262144
 
 /* Use common CFI driver */
 #define CONFIG_SYS_FLASH_CFI
@@ -149,6 +148,11 @@
 #define	CONFIG_PHY_ADDR			0x10
 /* MII PHY management */
 #define CONFIG_MII			1
+/* fixed-speed switch without standard PHY registers on MII */
+#define CONFIG_MII_NPE0_FIXEDLINK       1
+#define CONFIG_MII_NPE0_SPEED           100
+#define CONFIG_MII_NPE0_FULLDUPLEX      1
+
 /* Number of ethernet rx buffers & descriptors */
 #define CONFIG_SYS_RX_ETH_BUFFER		16
 #define CONFIG_RESET_PHY_R		1
@@ -183,13 +187,15 @@
 	"npe_ucode=50040000\0"						\
 	"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
 	"kerneladdr=50050000\0"						\
+	"kernelfile=actux3/uImage\0"					\
+	"rootfile=actux3/rootfs\0"					\
 	"rootaddr=50170000\0"						\
 	"loadaddr=10000\0"						\
 	"updateboot_ser=mw.b 10000 ff 40000;"				\
 	" loady ${loadaddr};"						\
 	" run eraseboot writeboot\0"					\
 	"updateboot_net=mw.b 10000 ff 40000;"				\
-	" tftp ${loadaddr} u-boot.bin;"					\
+	" tftp ${loadaddr} actux3/u-boot.bin;"				\
 	" run eraseboot writeboot\0"					\
 	"eraseboot=protect off 50000000 50003fff;"			\
 	" protect off 50006000 5003ffff;"				\
@@ -197,8 +203,9 @@
 	" erase 50006000 5003ffff\0"					\
 	"writeboot=cp.b 10000 50000000 4000;"				\
 	" cp.b 16000 50006000 3a000\0"					\
-	"eraseenv=protect off 50004000 50005fff;"			\
-	" erase 50004000 50005fff\0"					\
+	"updateucode=loady;"						\
+	" era ${npe_ucode} +${filesize};"				\
+	" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0"			\
 	"updateroot=tftp ${loadaddr} ${rootfile};"			\
 	" era ${rootaddr} +${filesize};"				\
 	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
@@ -209,7 +216,7 @@
 	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
 	"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3"	\
 	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \
 	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
 	"boot_flash=run flashargs addtty addeth;"			\
 	" bootm ${kerneladdr}\0"					\
@@ -217,4 +224,8 @@
 	" tftpboot ${loadaddr} ${kernelfile};"				\
 	" bootm\0"
 
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_INIT_SP_ADDR						\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/actux4.h b/include/configs/actux4.h
index 67189216d5..190de5a390 100644
--- a/include/configs/actux4.h
+++ b/include/configs/actux4.h
@@ -37,12 +37,11 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_BOARD_EARLY_INIT_F	1
 
 /***************************************************************
  * U-boot generic defines start here.
  ***************************************************************/
-#undef CONFIG_USE_IRQ
-
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
 
@@ -54,6 +53,15 @@
 
 #define CONFIG_CMD_ELF
 
+#define CONFIG_PCI
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_IXP_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI_ENUM
+#endif
+
 #define CONFIG_BOOTCOMMAND		"run boot_flash"
 /* enable passing of ATAGs */
 #define CONFIG_CMDLINE_TAG		1
@@ -81,8 +89,9 @@
 #define CONFIG_SYS_MEMTEST_START		0x00400000
 #define CONFIG_SYS_MEMTEST_END			0x00800000
 
-/* spec says 66.666 MHz, but it appears to be 33 */
-#define CONFIG_SYS_HZ				3333333
+/* timer clock - 2* OSC_IN system clock */
+#define CONFIG_IXP425_TIMER_CLK                 66000000
+#define CONFIG_SYS_HZ				1000
 
 /* default load address */
 #define CONFIG_SYS_LOAD_ADDR			0x00010000
@@ -97,10 +106,6 @@
  * The stack sizes are set up in start.S using the settings below
  */
 #define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-# define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
-# define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
-#endif
 
 /* Expansion bus settings */
 #define CONFIG_SYS_EXP_CS0			0xbd113003
@@ -108,7 +113,7 @@
 /* SDRAM settings */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM_1			0x00000000
-#define CONFIG_SYS_DRAM_BASE			0x00000000
+#define CONFIG_SYS_SDRAM_BASE			0x00000000
 
 /* 32MB SDRAM */
 #define CONFIG_SYS_SDR_CONFIG			0x18
@@ -118,6 +123,7 @@
 #define CONFIG_SYS_DRAM_SIZE			0x02000000
 
 /* FLASH organization */
+#define CONFIG_SYS_TEXT_BASE		0x50000000
 #define CONFIG_SYS_MAX_FLASH_BANKS		2
 /* max # of sectors per chip */
 #define CONFIG_SYS_MAX_FLASH_SECT		70
@@ -128,6 +134,7 @@
 #define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_LEN			(252 << 10)
+#define CONFIG_BOARD_SIZE_LIMIT			258048
 
 /* Use common CFI driver */
 #define CONFIG_SYS_FLASH_CFI
@@ -152,6 +159,7 @@
 #define	CONFIG_PHY_ADDR			0x1C
 /* MII PHY management */
 #define CONFIG_MII			1
+
 /* Number of ethernet rx buffers & descriptors */
 #define CONFIG_SYS_RX_ETH_BUFFER		16
 
@@ -180,19 +188,22 @@
 	"mtd=IXP4XX-Flash.0:252k(uboot),4k(uboot_env);"			\
 	"IXP4XX-Flash.1:128k(ucode),1280k(linux),-(root)\0"		\
 	"kerneladdr=51020000\0"						\
+	"kernelfile=actux4/uImage\0"					\
+	"rootfile=actux4/rootfs\0"					\
 	"rootaddr=51160000\0"						\
 	"loadaddr=10000\0"						\
 	"updateboot_ser=mw.b 10000 ff 40000;"				\
 	" loady ${loadaddr};"						\
 	" run eraseboot writeboot\0"					\
 	"updateboot_net=mw.b 10000 ff 40000;"				\
-	" tftp ${loadaddr} u-boot.bin;"					\
+	" tftp ${loadaddr} actux4/u-boot.bin;"					\
 	" run eraseboot writeboot\0"					\
 	"eraseboot=protect off 50000000 5003efff;"			\
 	" erase 50000000 +${filesize}\0"				\
 	"writeboot=cp.b 10000 50000000 ${filesize}\0"			\
-	"eraseenv=protect off 5003f000 5003ffff;"			\
-	" erase 5003f000 5003ffff\0"					\
+	"updateucode=loady;"						\
+	" era ${npe_ucode} +${filesize};"				\
+	" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0"			\
 	"updateroot=tftp ${loadaddr} ${rootfile};"			\
 	" era ${rootaddr} +${filesize};"				\
 	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
@@ -211,4 +222,8 @@
 	" tftpboot ${loadaddr} ${kernelfile};"				\
 	" bootm\0"
 
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_INIT_SP_ADDR						\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/dvlhost.h b/include/configs/dvlhost.h
new file mode 100644
index 0000000000..bccd416fcc
--- /dev/null
+++ b/include/configs/dvlhost.h
@@ -0,0 +1,248 @@
+/*
+ * (C) Copyright 2009
+ * Michael Schwingen, michael@schwingen.org
+ *
+ * Configuration settings for the
+ * dLAN200 AV Wireless G ("dvlhost") board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_IXP425			1
+#define CONFIG_DVLHOST			1
+
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+#define CONFIG_IXP_SERIAL
+#define CONFIG_SYS_IXP425_CONSOLE	IXP425_UART2
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_BOARD_EARLY_INIT_F	1
+#define CONFIG_SYS_LDSCRIPT	"board/dvlhost/u-boot.lds"
+
+/***************************************************************
+ * U-boot generic defines start here.
+ ***************************************************************/
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command line configuration. */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_PCI
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_IXP_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI_ENUM
+#endif
+
+#define CONFIG_BOOTCOMMAND		"run boot_flash"
+/* enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+#if defined(CONFIG_CMD_KGDB)
+# define CONFIG_KGDB_BAUDRATE		230400
+/* which serial port to use */
+# define CONFIG_KGDB_SER_INDEX		1
+#endif
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"=> "
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS		16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END		0x01D80000
+
+/* timer clock - 2* OSC_IN system clock */
+#define CONFIG_IXP425_TIMER_CLK         66666666
+#define CONFIG_SYS_HZ			1000
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x00010000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, \
+					  115200, 230400 }
+#define CONFIG_SERIAL_RTS_ACTIVE	1
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
+
+/* Expansion bus settings */
+#define CONFIG_SYS_EXP_CS0		0xbd113442
+
+/* SDRAM settings */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x00000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+
+/* 32MB SDRAM: 2* 8Mx16, CL3 */
+#define CONFIG_SYS_SDR_CONFIG		0x18
+#define PHYS_SDRAM_1_SIZE		0x02000000
+#define CONFIG_SYS_SDRAM_REFRESH_CNT	0x800
+#define CONFIG_SYS_SDR_MODE_CONFIG	0x1
+#define CONFIG_SYS_DRAM_SIZE		PHYS_SDRAM_1_SIZE
+
+/* FLASH organization: one Spansion S29AL032D-04 Flash */
+#define CONFIG_SYS_TEXT_BASE		0x50000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	140
+#define PHYS_FLASH_1			0x50000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1 }
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+#define CONFIG_BOARD_SIZE_LIMIT         262144
+
+/* Use common CFI driver */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+/* no byte writes on IXP4xx */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* Ethernet */
+
+/* include IXP4xx NPE support */
+#define CONFIG_IXP4XX_NPE		1
+
+#define CONFIG_NET_MULTI		1
+/* NPE0 PHY: MII dLAN200 AVmodule, 100BaseT-FDX fixed */
+#define	CONFIG_PHY_ADDR			0x18
+/* NPE1 PHY: MII IP175 switch, port 5 is host port */
+#define	CONFIG_PHY1_ADDR		0x05
+/* MII PHY management */
+#define CONFIG_MII			1
+/* fixed-speed powerline modem without standard PHY registers on MII */
+#define CONFIG_MII_NPE0_FIXEDLINK       1
+#define CONFIG_MII_NPE0_SPEED           100
+#define CONFIG_MII_NPE0_FULLDUPLEX      1
+/* fixed-speed switch without standard PHY registers on MII */
+#define CONFIG_MII_NPE1_FIXEDLINK       1
+#define CONFIG_MII_NPE1_SPEED           100
+#define CONFIG_MII_NPE1_FULLDUPLEX      1
+
+/* Number of ethernet rx buffers & descriptors */
+#define CONFIG_SYS_RX_ETH_BUFFER	16
+#define CONFIG_RESET_PHY_R		1
+/* ethernet switch connected to MII port */
+#define CONFIG_MII_ETHSWITCH		1
+#define CONFIG_HAS_ETH1			1
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#undef  CONFIG_CMD_NFS
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+/*
+ * environment organization:
+ * one flash sector, embedded in uboot area (bottom bootblock flash)
+ */
+#define	CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x4000)
+#define CONFIG_SYS_USE_PPCENV		1
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"npe_ucode=50040000\0"						\
+	"ethprime=NPE1\0"						\
+	"ethrotate=no\0"						\
+	"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root),\0" \
+	"kerneladdr=50050000\0"						\
+	"kernelfile=dvlhost/uImage\0"					\
+	"rootfile=dvlhost/rootfs\0"					\
+	"rootaddr=50170000\0"						\
+	"loadaddr=10000\0"						\
+	"updateboot_ser=mw.b 10000 ff 40000;"				\
+	" loady ${loadaddr};"						\
+	" run eraseboot writeboot\0"					\
+	"updateboot_net=mw.b 10000 ff 40000;"				\
+	" tftp ${loadaddr} dvlhost/u-boot.bin;"				\
+	" run eraseboot writeboot\0"					\
+	"eraseboot=protect off 50000000 50003fff;"			\
+	" protect off 50006000 5003ffff;"				\
+	" erase 50000000 50003fff;"					\
+	" erase 50006000 5003ffff\0"					\
+	"writeboot=cp.b 10000 50000000 4000;"				\
+	" cp.b 16000 50006000 3a000\0"					\
+	"updateucode=loady;"						\
+	" era ${npe_ucode} +${filesize};"				\
+	" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0"			\
+	"updateroot=tftp ${loadaddr} ${rootfile};"			\
+	" era ${rootaddr} +${filesize};"				\
+	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
+	"updatekern=tftp ${loadaddr} ${kernelfile};"			\
+	" era ${kerneladdr} +${filesize};"				\
+	" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0"			\
+	"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3"	\
+	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
+	"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3"	\
+	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
+	"boot_flash=run flashargs addtty addeth;"			\
+	" bootm ${kerneladdr}\0"					\
+	"boot_net=run netargs addtty addeth;"				\
+	" tftpboot ${loadaddr} ${kernelfile};"				\
+	" bootm\0"
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_INIT_SP_ADDR						\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h
index 28d41e2925..4bad31dfed 100644
--- a/include/configs/ixdp425.h
+++ b/include/configs/ixdp425.h
@@ -36,12 +36,19 @@
 #define CONFIG_DISPLAY_CPUINFO	1	/* display cpu info (and speed)	*/
 #define CONFIG_DISPLAY_BOARDINFO 1	/* display board info		*/
 
+/*
+ * select serial console configuration
+ */
+#define CONFIG_IXP_SERIAL
+#define CONFIG_SYS_IXP425_CONSOLE	IXP425_UART1
+#define CONFIG_BAUDRATE         115200
+
+#define CONFIG_BOARD_EARLY_INIT_F	1
+
 /***************************************************************
  * U-boot generic defines start here.
  ***************************************************************/
 
-#undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
-
 /*
  * Size of malloc() pool
  */
@@ -50,9 +57,6 @@
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
-#define CONFIG_BAUDRATE         115200
-
-
 /*
  * BOOTP options
  */
@@ -61,38 +65,33 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
-/*
- * Command line configuration.
- */
+/* Command line configuration. */
 #include <config_cmd_default.h>
 
 #define CONFIG_CMD_ELF
-#define CONFIG_CMD_PCI
-
 
 #define CONFIG_PCI
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_PCI_PNP
 #define CONFIG_IXP_PCI
-#define CONFIG_NET_MULTI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI_ENUM
 #define CONFIG_EEPRO100
+#endif
 
-#define CONFIG_BOOTDELAY        3
-/*#define CONFIG_ETHADDR          08:00:3e:26:0a:5b*/
-#define CONFIG_NETMASK          255.255.255.0
-#define CONFIG_IPADDR           192.168.0.21
-#define CONFIG_SERVERIP         192.168.0.148
-#define CONFIG_BOOTCOMMAND      "bootm 50040000"
-#define CONFIG_BOOTARGS         "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
-#define CONFIG_CMDLINE_TAG
+#define CONFIG_BOOTCOMMAND		"run boot_flash"
+/* enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
 #endif
 
-/*
- * Miscellaneous configurable options
- */
+/* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP                            /* undef to save memory         */
 #define CONFIG_SYS_PROMPT              "=> "   /* Monitor Command Prompt       */
 #define CONFIG_SYS_CBSIZE              256             /* Console I/O Buffer Size      */
@@ -103,10 +102,13 @@
 #define CONFIG_SYS_MEMTEST_START       0x00400000      /* memtest works on     */
 #define CONFIG_SYS_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
 
-#define CONFIG_SYS_LOAD_ADDR           0x00010000      /* default load address */
+/* timer clock - 2* OSC_IN system clock */
+#define CONFIG_IXP425_TIMER_CLK                 66666666
+#define CONFIG_SYS_HZ				1000
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR			0x00010000
 
-#define CONFIG_SYS_HZ                  3333333         /* spec says 66.666 MHz, but it appears to be 33 */
-						/* valid baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
 /*
@@ -115,10 +117,6 @@
  * The stack sizes are set up in start.S using the settings below
  */
 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
-#endif
 
 /***************************************************************
  * Platform/Board specific defines start here.
@@ -129,71 +127,145 @@
  */
 
 
-/*
- * select serial console configuration
- */
-#define CONFIG_IXP_SERIAL
-#define CONFIG_SYS_IXP425_CONSOLE	IXP425_UART1   /* we use UART1 for console */
 
 /*
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS    1          /* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1            0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE       0x01000000 /* 16 MB */
+#define CONFIG_SYS_TEXT_BASE	0x50000000
 
 #define PHYS_FLASH_1            0x50000000 /* Flash Bank #1 */
 #define PHYS_FLASH_SIZE         0x00800000 /* 8 MB */
 #define PHYS_FLASH_BANK_SIZE    0x00800000 /* 8 MB Banks */
 #define PHYS_FLASH_SECT_SIZE    0x00020000 /* 128 KB sectors (x1) */
 
-#define CONFIG_SYS_DRAM_BASE           0x00000000
-#define CONFIG_SYS_DRAM_SIZE           0x01000000
-
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_BOARD_SIZE_LIMIT		262144
 
-/*
- * Expansion bus settings
- */
-#define CONFIG_SYS_EXP_CS0				0xbcd23c42
+/* Expansion bus settings */
+#define CONFIG_SYS_EXP_CS0	0xbcd23c42
+
+/* SDRAM settings */
+#define CONFIG_NR_DRAM_BANKS    1          /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1            0x00000000 /* SDRAM Bank #1 */
+#define CONFIG_SYS_SDRAM_BASE	0x00000000
 
-/*
- * SDRAM settings
- */
 #define CONFIG_SYS_SDR_CONFIG		0xd
 #define CONFIG_SYS_SDR_MODE_CONFIG	0x1
 #define CONFIG_SYS_SDRAM_REFRESH_CNT	0x81a
 
 /*
- * GPIO settings
- */
-
-/*
- * FLASH and environment organization
- */
-/*
  * FLASH and environment organization
  */
 #define CONFIG_SYS_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 #define CONFIG_SYS_MAX_FLASH_SECT      128	/* max number of sectors on one chip    */
 
-#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
 #define	CONFIG_ENV_IS_IN_FLASH	1
 
 #define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1 }
 
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/
-
 #define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x20000)
+#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x40000)
 #define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
+/* Use common CFI driver */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+/* no byte writes on IXP4xx */
+#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
+/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* Ethernet */
+
+/* include IXP4xx NPE support */
+#define CONFIG_IXP4XX_NPE		1
+#define CONFIG_NET_MULTI		1
+/* NPE0 PHY address */
+#define	CONFIG_PHY_ADDR			0
+/* NPE1 PHY address (HW Release E only) */
+#define	CONFIG_PHY1_ADDR		1
+/* MII PHY management */
+#define CONFIG_MII			1
+/* Number of ethernet rx buffers & descriptors */
+#define CONFIG_SYS_RX_ETH_BUFFER		16
+
+#define CONFIG_HAS_ETH1			1
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#undef  CONFIG_CMD_NFS
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE		32
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"npe_ucode=50060000\0"						\
+	"mtd=IXP4XX-Flash.0:256k(uboot),128k(env),128k(ucode),2048k(linux),-(root)\0" \
+	"kerneladdr=50080000\0"						\
+	"kernelfile=ixdp425/uImage\0"					\
+	"rootfile=ixdp425/rootfs\0"					\
+	"rootaddr=50280000\0"						\
+	"loadaddr=10000\0"						\
+	"updateboot_ser=mw.b 10000 ff 40000;"				\
+	" loady ${loadaddr};"						\
+	" run eraseboot writeboot\0"					\
+	"updateboot_net=mw.b 10000 ff 40000;"				\
+	" tftp ${loadaddr} ixdp425/u-boot.bin;"				\
+	" run eraseboot writeboot\0"					\
+	"eraseboot=protect off 50000000 5003ffff;"			\
+	" erase 50000000 5003ffff\0"					\
+	"writeboot=cp.b 10000 50000000 ${filesize}\0"			\
+	"updateucode=loady;"						\
+	" era ${npe_ucode} +${filesize};"				\
+	" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0"			\
+	"updateroot=tftp ${loadaddr} ${rootfile};"			\
+	" era ${rootaddr} +${filesize};"				\
+	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
+	"updatekern=tftp ${loadaddr} ${kernelfile};"			\
+	" era ${kerneladdr} +${filesize};"				\
+	" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0"			\
+	"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4"	\
+	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
+	"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4"	\
+	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
+	"boot_flash=run flashargs addtty addeth;"			\
+	" bootm ${kerneladdr}\0"					\
+	"boot_net=run netargs addtty addeth;"				\
+	" tftpboot ${loadaddr} ${kernelfile};"				\
+	" bootm\0"
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_INIT_SP_ADDR						\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GPIO_UTOPIA_GPIO1    0
+#define CONFIG_SYS_GPIO_UTOPIA_IRQ_N    1
+#define CONFIG_SYS_GPIO_HSS1_IRQ_N      2
+#define CONFIG_SYS_GPIO_HSS0_IRQ_N      3
+#define CONFIG_SYS_GPIO_ETH0_IRQ_N      4
+#define CONFIG_SYS_GPIO_ETH1_IRQ_N      5
+#define CONFIG_SYS_GPIO_I2C_SCL	        6
+#define CONFIG_SYS_GPIO_I2C_SDA	        7
+#define CONFIG_SYS_GPIO_PCI_INTD_N	8
+#define CONFIG_SYS_GPIO_PCI_INTC_N	9
+#define CONFIG_SYS_GPIO_PCI_INTB_N	10
+#define CONFIG_SYS_GPIO_PCI_INTA_N	11
+#define CONFIG_SYS_GPIO_UTOPIA_GPIO0	12
+#define CONFIG_SYS_GPIO_PCI_RESET_N	13
+#define CONFIG_SYS_GPIO_PCI_CLK	        14
+#define CONFIG_SYS_GPIO_EXTBUS_CLK	15
+
 #endif  /* __CONFIG_H */
diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h
index 637fd7d4f8..3de001371f 100644
--- a/include/configs/ixdpg425.h
+++ b/include/configs/ixdpg425.h
@@ -53,9 +53,6 @@
 /*
  * Misc configuration options
  */
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
-#define CONFIG_USE_IRQ          1	/* we need IRQ stuff for timer	*/
-#define CONFIG_TIMER_IRQ
 
 #define CONFIG_BOOTCOUNT_LIMIT		/* support for bootcount limit	*/
 #define CONFIG_SYS_BOOTCOUNT_ADDR	0x60003000 /* inside qmrg sram		*/
@@ -115,6 +112,7 @@
 #define CONFIG_SYS_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
 #define CONFIG_SYS_LOAD_ADDR           0x00010000      /* default load address */
 
+#define CONFIG_IXP425_TIMER_CLK		66666666
 #define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 						/* valid baudrates */
@@ -179,6 +177,8 @@
 #define PHYS_SDRAM_1            0x00000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE       0x02000000 /* 32 MB */
 
+#define CONFIG_SYS_TEXT_BASE	0x50000000
+
 #define PHYS_FLASH_1            0x50000000 /* Flash Bank #1 */
 #define PHYS_FLASH_SIZE         0x01000000 /* 16 MB */
 #define PHYS_FLASH_BANK_SIZE    0x01000000 /* 16 MB Banks */
@@ -248,4 +248,9 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	32
 
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE 0
+#define CONFIG_SYS_INIT_SP_ADDR						\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
 #endif  /* __CONFIG_H */
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
index 33fa6ee8bd..7fe9e5b268 100644
--- a/include/configs/pdnb3.h
+++ b/include/configs/pdnb3.h
@@ -50,9 +50,6 @@
 /*
  * Misc configuration options
  */
-#define CONFIG_USE_IRQ          1	/* we need IRQ stuff for timer	*/
-#define CONFIG_TIMER_IRQ
-
 #define CONFIG_BOOTCOUNT_LIMIT		/* support for bootcount limit	*/
 #define CONFIG_SYS_BOOTCOUNT_ADDR	0x60003000 /* inside qmrg sram		*/
 
@@ -117,6 +114,7 @@
 #define CONFIG_SYS_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
 #define CONFIG_SYS_LOAD_ADDR           0x00010000      /* default load address */
 
+#define CONFIG_IXP425_TIMER_CLK		66666666
 #define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 						/* valid baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
@@ -188,6 +186,7 @@
 #define PHYS_SDRAM_1            0x00000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE       0x02000000 /* 32 MB */
 
+#define CONFIG_SYS_TEXT_BASE	       0x50000000
 #define CONFIG_SYS_FLASH_BASE          0x50000000
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
 #if defined(CONFIG_SCPU)
@@ -345,4 +344,9 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	32
 
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_INIT_SP_ADDR        \
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
 #endif  /* __CONFIG_H */