ppc/arm: zap EMK boards

The following bard configurations have been without active maintenance
for a long time, and the board maintainer agrees to have them removed:

MPC5200:	TOP5200, MINI5200, EVAL5200
MPC860:		TOP860
at91sam9xeXXX:	top9000eval_xe, top9000su_xe

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
[trini: Add missing Kconfig removals]
Signed-off-by: Tom Rini <trini@ti.com>

3 files changed, 0 insertions, 1101 deletions

diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h
deleted file mode 100644
index 92128b9588..0000000000
--- a/include/configs/TOP5200.h
+++ /dev/null
@@ -1,402 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
- *
- * TOP5200 differences from IceCube:
- * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
- *   bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
- * 1 SDRAM/DDRAM Bank up to 256 MB
- * local VPD I2C Bus is software driven and uses
- *   GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
- * FLASH is re-located at 0xff000000
- * Internal regs are at 0xf0000000
- * Reset jumps to 0x00000100
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
-#define CONFIG_TOP5200		1	/* ... on TOP5200 board - we need this for FEC.C */
-
-/*
- * allowed and functional CONFIG_SYS_TEXT_BASE values:
- * 0xff000000	low boot at 0x00000100 (default board setting)
- * 0xfff00000	high boot at 0xfff00100 (board needs modification)
- * 0x00100000	RAM load and test
- */
-#define	CONFIG_SYS_TEXT_BASE	0xff000000
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-
-#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#  define CONFIG_PCI		1
-#  define CONFIG_PCI_PNP		1
-#  define CONFIG_PCI_SCAN_SHOW	1
-#  define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
-
-#  define CONFIG_PCI_MEM_BUS	0x40000000
-#  define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#  define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#  define CONFIG_PCI_IO_BUS	0x50000000
-#  define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#  define CONFIG_PCI_IO_SIZE	0x01000000
-
-#endif
-
-/* USB */
-#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
-
-#  define CONFIG_USB_OHCI
-#  define CONFIG_USB_CLOCK	0x0001bbbb
-#  if defined (CONFIG_EVAL5200)
-#    define CONFIG_USB_CONFIG	0x00005100
-#  else
-#    define CONFIG_USB_CONFIG	0x00001000
-#  endif
-#  define CONFIG_DOS_PARTITION
-#  define CONFIG_USB_STORAGE
-
-#endif
-
-/* IDE */
-#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
-#  define CONFIG_DOS_PARTITION
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_REGINFO
-
-#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_PCI
-#endif
-
-
-/*
- * MUST be low boot - HIGHBOOT is not supported anymore
- */
-#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
-#   define CONFIG_SYS_LOWBOOT		1
-#   define CONFIG_SYS_LOWBOOT16	1
-#else
-#   error "CONFIG_SYS_TEXT_BASE must be 0xff000000"
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"flash_nfs=run nfsargs addip;"					\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip;"					\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
-	"rootpath=/opt/eldk/ppc_82xx\0"					\
-	"bootfile=/tftpboot/MPC5200/uImage\0"				\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-
-/*
- * I2C configuration
- */
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_SIZE 0x2000
-
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-
-#if defined(CONFIG_SYS_I2C_SOFT)
-#  define CONFIG_SYS_I2C
-#  define CONFIG_SYS_I2C_SOFT_SPEED	100000
-#  define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
-/**/
-#  define SDA0			0x40
-#  define SCL0			0x80
-#  define GPIOE0		*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c00))
-#  define DDR0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c08))
-#  define DVO0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c0c))
-#  define DVI0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c20))
-#  define ODE0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c04))
-#  define I2C_INIT		{GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
-#  define I2C_READ		((DVI0&SDA0)?1:0)
-#  define I2C_SDA(x)	{if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
-#  define I2C_SCL(x)	{if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
-#  define I2C_DELAY		{udelay(5);}
-#  define I2C_ACTIVE	{DDR0|=SDA0;}
-#  define I2C_TRISTATE	{DDR0&=~SDA0;}
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_FACT_ADDR	0x57
-#endif
-
-#if defined (CONFIG_HARD_I2C)
-#  define CONFIG_SYS_I2C_MODULE	2		/* Select I2C module #1 or #2 */
-#  define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
-#  define CONFIG_SYS_I2C_SLAVE		0x7F
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
-#define CONFIG_SYS_I2C_FACT_ADDR	0x54
-#endif
-
-/*
- * Flash configuration, expect one 16 Megabyte Bank at most
- */
-#define CONFIG_SYS_FLASH_BASE		0xff000000
-#define CONFIG_SYS_FLASH_SIZE		0x01000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0)
-
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-#undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */
-
-/*
- * DRAM configuration - will be read from VPD later... TODO!
- */
-#if 0
-/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
-#define	CONFIG_SYS_DRAM_DDR		0
-#define CONFIG_SYS_DRAM_EMODE		0
-#define CONFIG_SYS_DRAM_MODE		0x008D
-#define CONFIG_SYS_DRAM_CONTROL	0x514F0000
-#define CONFIG_SYS_DRAM_CONFIG1	0xC2233A00
-#define CONFIG_SYS_DRAM_CONFIG2	0x88B70004
-#define	CONFIG_SYS_DRAM_TAP_DEL	0x08
-#define CONFIG_SYS_DRAM_RAM_SIZE	0x19
-#endif
-#if 1
-/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
-#define	CONFIG_SYS_DRAM_DDR		0
-#define CONFIG_SYS_DRAM_EMODE		0
-#define CONFIG_SYS_DRAM_MODE		0x00CD
-#define CONFIG_SYS_DRAM_CONTROL	0x514F0000
-#define CONFIG_SYS_DRAM_CONFIG1	0xD2333A00
-#define CONFIG_SYS_DRAM_CONFIG2	0x8AD70004
-#define	CONFIG_SYS_DRAM_TAP_DEL	0x08
-#define CONFIG_SYS_DRAM_RAM_SIZE	0x19
-#endif
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_EEPROM	1	/* turn on EEPROM env feature */
-#define CONFIG_ENV_OFFSET		0x1000
-#define CONFIG_ENV_SIZE		0x0700
-
-/*
- * VPD settings
- */
-#define CONFIG_SYS_FACT_OFFSET		0x1800
-#define CONFIG_SYS_FACT_SIZE		0x0800
-
-/*
- * Memory map
- *
- * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
- */
-#define CONFIG_SYS_MBAR			0xf0000000	/* DO NOT CHANGE this */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
-
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII10	/* Workaround for FEC 100Mbit problem */
-#define	CONFIG_PHY_ADDR		0x1f
-#define	CONFIG_PHY_TYPE		0x79c874
-/*
- * GPIO configuration:
- * PSC1,2,3 predefined as UART
- * PCI disabled
- * Ethernet 100 with MD
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x00058044
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
-#else
-#  define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-
-#ifdef CONFIG_EVAL5200		/* M48T08 is available with the Evaluation board only */
-  #define CONFIG_RTC_MK48T59	1	/* use M48T08 on EVAL5200 */
-  #define RTC(reg)		(0xf0010000+reg)
-  /* setup CS2 for M48T08. Must MAP 64kB */
-  #define CONFIG_SYS_CS2_START	RTC(0)
-  #define CONFIG_SYS_CS2_SIZE	0x10000
-  /* setup CS2 configuration register: */
-  /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
-  /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
-  #define CONFIG_SYS_CS2_CFG	0x00047800
-#else
-  #define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00047801
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS	0x7f000000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-
-#define CONFIG_IDE_RESET	1
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-
-/* Offset for data I/O			*/
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
-
-/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005c)
-
-/* Interval between registers                                                */
-#define CONFIG_SYS_ATA_STRIDE          4
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h
deleted file mode 100644
index da68503a69..0000000000
--- a/include/configs/TOP860.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/*
- * (C) Copyright 2003
- * EMK Elektronik GmbH <www.emk-elektronik.de>
- * Reinhard Meyer <r.meyer@emk-elektronik.de>
- *
- * Configuation settings for the TOP860 board.
- *
- * -----------------------------------------------------------------
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/*
- * TOP860 is a simple module:
- * 16-bit wide FLASH on CS0	(2MB or more)
- * 32-bit wide DRAM on CS2 (either 4MB or 16MB)
- * FEC with Am79C874 100-Base-T and Fiber Optic
- * Ports available, but we choose SMC1 for Console
- * 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set
- * 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock
- *
- * This config has been copied from MBX.h / MBX860T.h
- */
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-/*-----------------------------------------------------------------------
- * CPU and BOARD type
- */
-#define CONFIG_MPC860	1	/* This is a MPC860 CPU		*/
-#define CONFIG_MPC860T	1	/* even better... an FEC!	*/
-#define CONFIG_TOP860	1	/* ...on a TOP860 module	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0x80000000
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#define	CONFIG_IDENT_STRING " EMK TOP860"
-
-/*-----------------------------------------------------------------------
- * CLOCK settings
- */
-#define	CONFIG_SYSCLK	49152000
-#define	CONFIG_SYS_XTAL		32768
-#define	CONFIG_EBDF		1
-#define	CONFIG_COM		3
-#define	CONFIG_RTC_MPC8xx
-
-/*-----------------------------------------------------------------------
- * Physical memory map as defined by EMK
- */
-#define CONFIG_SYS_IMMR		0xFFF00000	/* Internal Memory Mapped Register */
-#define	CONFIG_SYS_FLASH_BASE	0x80000000	/* FLASH in final mapping */
-#define	CONFIG_SYS_DRAM_BASE	0x00000000	/* DRAM in final mapping */
-#define	CONFIG_SYS_FLASH_MAX	0x00400000	/* max FLASH to expect */
-#define	CONFIG_SYS_DRAM_MAX	0x01000000	/* max DRAM to expect */
-
-/*-----------------------------------------------------------------------
- * derived values
- */
-#define	CONFIG_SYS_MF			(CONFIG_SYSCLK/CONFIG_SYS_XTAL)
-#define	CONFIG_SYS_CPUCLOCK	CONFIG_SYSCLK
-#define	CONFIG_SYS_BRGCLOCK	CONFIG_SYSCLK
-#define	CONFIG_SYS_BUSCLOCK	(CONFIG_SYSCLK >> CONFIG_EBDF)
-#define	CONFIG_8xx_GCLK_FREQ	CONFIG_SYSCLK
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CONFIG_SYS_FLASH_CFI
-
-/*-----------------------------------------------------------------------
- * Command interpreter
- */
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#define CONFIG_BAUDRATE		9600
-
-/*
- * Allow partial commands to be matched to uniqueness.
- */
-#define CONFIG_SYS_MATCH_PARTIAL_CMD
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_BEDBUG
-
-
-#define	CONFIG_SOURCE			1
-#define	CONFIG_SYS_LOADS_BAUD_CHANGE	1
-#undef	CONFIG_LOADS_ECHO			/* NO echo on for serial download	*/
-
-
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-
-#undef	CONFIG_SYS_HUSH_PARSER			/* Hush parse for U-Boot	*/
-
-
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
- #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-/*-----------------------------------------------------------------------
- * Memory Test Command
- */
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-/*-----------------------------------------------------------------------
- * Environment handler
- * only the first 6k in EEPROM are available for user. Of that we use 256b
- */
-#define CONFIG_ENV_IS_IN_EEPROM	1	/* turn on EEPROM env feature */
-#define CONFIG_ENV_OFFSET		0x1000
-#define CONFIG_ENV_SIZE		0x0700
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_FACT_OFFSET		0x1800
-#define CONFIG_SYS_FACT_SIZE		0x0800
-#define CONFIG_SYS_I2C_FACT_ADDR	0x57
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_SIZE 0x2000
-#define	CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED	100000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
-/**/
-#define	SDA	0x00010
-#define	SCL	0x00020
-#define __I2C_DIR	immr->im_cpm.cp_pbdir
-#define __I2C_DAT	immr->im_cpm.cp_pbdat
-#define __I2C_PAR	immr->im_cpm.cp_pbpar
-#define	__I2C_ODR	immr->im_cpm.cp_pbodr
-#define	I2C_INIT	{ __I2C_PAR &= ~(SDA|SCL);	\
-			  __I2C_ODR &= ~(SDA|SCL);	\
-			  __I2C_DAT |= (SDA|SCL);	\
-			  __I2C_DIR|=(SDA|SCL);	}
-#define	I2C_READ	((__I2C_DAT & SDA) ? 1 : 0)
-#define	I2C_SDA(x)	{ if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
-#define	I2C_SCL(x)	{ if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
-#define	I2C_DELAY	{ udelay(5); }
-#define	I2C_ACTIVE	{ __I2C_DIR |= SDA; }
-#define	I2C_TRISTATE	{ __I2C_DIR &= ~SDA; }
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*-----------------------------------------------------------------------
- * defines we need to get FEC running
- */
-#define CONFIG_FEC_ENET		1	/* Ethernet only via FEC	*/
-#define	FEC_ENET		1	/* eth.c needs it that way... */
-#define CONFIG_SYS_DISCOVER_PHY	1
-#define CONFIG_MII		1
-#define CONFIG_MII_INIT		1
-#define CONFIG_PHY_ADDR		31
-
-/*-----------------------------------------------------------------------
- * adresses
- */
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0x80000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE	0x2f00	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_VPD_SIZE	256 /* size in bytes reserved for vpd buffer */
-#define CONFIG_SYS_INIT_VPD_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_VPD_OFFSET-8)
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/* Interrupt level assignments.
-*/
-#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
-
-/*-----------------------------------------------------------------------
- * Debug Enable Register
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0					/* used in start.S */
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * set up PLPRCR (PLL, Low-Power, and Reset Control Register)
- *	12	MF		calculated	Multiplication factor
- *	4	0		0000
- *	1	SPLSS	0			System PLL lock status sticky
- *	1	TEXPS	1			Timer expired status
- *	1	0		0
- *	1	TMIST	0			Timers interrupt status
- *	1	0		0
- *	1	CSRC	0			Clock source (0=DFNH, 1=DFNL)
- *	2	LPM		00			Low-power modes
- *	1	CSR		0			Checkstop reset enable
- *	1	LOLRE	0			Loss-of-lock reset enable
- *	1	FIOPD	0			Force I/O pull down
- *	5	0		00000
- */
-#define CONFIG_SYS_PLPRCR	(PLPRCR_TEXPS | ((CONFIG_SYS_MF-1)<<20))
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * set up SYPCR:
- *	16	SWTC	0xffff		Software watchdog timer count
- *	8	BMT		0xff		Bus monitor timing
- *	1	BME		1			Bus monitor enable
- *	3	0		000
- *	1	SWF		1			Software watchdog freeze
- *	1	SWE		0/1			Software watchdog enable
- *	1	SWRI	0/1			Software watchdog reset/interrupt select (1=HRESET)
- *	1	SWP		0/1			Software watchdog prescale (1=/2048)
- */
-#if defined (CONFIG_WATCHDOG)
- #define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-					 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
- #define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * set up SIUMCR
- *	1	EARB	0			External arbitration
- *	3	EARP	000			External arbitration request priority
- *	4	0		0000
- *	1	DSHW	0			Data show cycles
- *	2	DBGC	00			Debug pin configuration
- *	2	DBPC	00			Debug port pins configuration
- *	1	0		0
- *	1	FRC		0			FRZ pin configuration
- *	1	DLK		0			Debug register lock
- *	1	OPAR	0			Odd parity
- *	1	PNCS	0			Parity enable for non memory controller regions
- *	1	DPC		0			Data parity pins configuration
- *	1	MPRE	0			Multiprocessor reservation enable
- *	2	MLRC	11			Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)
- *	1	AEME	0			Async external master enable
- *	1	SEME	0			Sync external master enable
- *	1	BSC		0			Byte strobe configuration
- *	1	GB5E	0			GPL_B5 enable
- *	1	B2DD	0			Bank 2 double drive
- *	1	B3DD	0			Bank 3 double drive
- *	4	0		0000
- */
-#define CONFIG_SYS_SIUMCR	(SIUMCR_MLRC11)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * set up SCCR (System Clock and Reset Control Register)
- *	1	0		0
- *	2	COM		11			Clock output module (00=full, 01=half, 11=off)
- *	3	0		000
- *	1	TBS		1			Timebase source (0=OSCCLK, 1=GCLK2)
- *	1	RTDIV	0			Real-time clock divide (0=/4, 1=/512)
- *	1	RTSEL	0			Real-time clock select (0=OSCM, 1=EXTCLK)
- *	1	CRQEN	0			CPM request enable
- *	1	PRQEN	0			Power management request enable
- *	2	0		00
- *	2	EBDF	xx			External bus division factor
- *	2	0		00
- *	2	DFSYNC	00			Division factor for SYNCLK
- *	2	DFBRG	00			Division factor for BRGCLK
- *	3	DFNL	000			Division factor low frequency
- *	3	DFNH	000			Division factor high frequency
- *	5	0		00000
- */
-#define SCCR_MASK	0
-#ifdef CONFIG_EBDF
- #define CONFIG_SYS_SCCR	(SCCR_COM11 | SCCR_TBS | SCCR_EBDF01)
-#else
- #define CONFIG_SYS_SCCR	(SCCR_COM11 | SCCR_TBS)
-#endif
-
-/*-----------------------------------------------------------------------
- * Chip Select 0 - FLASH
- *-----------------------------------------------------------------------
- * Preliminary Values
- */
-/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1	*/
-#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR)
-#define CONFIG_SYS_OR0_PRELIM	(-CONFIG_SYS_FLASH_MAX | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V )
-
-/*-----------------------------------------------------------------------
- * misc
- *-----------------------------------------------------------------------
- *
- */
-/*
- * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
- */
-#define CONFIG_BOOTDELAY				5
-
-/*
- * Pass the clock frequency to the Linux kernel in units of MHz
- */
-#define	CONFIG_CLOCKS_IN_MHZ
-
-#define CONFIG_PREBOOT		\
-	"echo;echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND	\
-	"bootp;" \
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
-	"bootm"
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Set default IP stuff just to get bootstrap entries into the
- * environment so that we can source the full default environment.
- */
-#define CONFIG_ETHADDR					9a:52:63:15:85:25
-#define CONFIG_SERVERIP					10.0.4.200
-#define CONFIG_IPADDR					10.0.4.111
-
-#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/top9000.h b/include/configs/top9000.h
deleted file mode 100644
index a96a9cb416..0000000000
--- a/include/configs/top9000.h
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * (C) Copyright 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- *
- * Configuation settings for the TOP9000 CPU module with AT91SAM9XE.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/*
- * top9000 with at91sam9xe256 or at91sam9xe512
- *
- * Initial Bootloader is in embedded flash.
- * Vital Product Data, U-Boot Environment are in I2C-EEPROM.
- * U-Boot is in embedded flash, a backup U-Boot can be in NAND flash.
- * kernel and file system are either in NAND flash or on a micro SD card.
- * NAND flash is optional.
- * I2C EEPROM is never optional.
- * SPI FRAM is optional.
- * SPI ENC28J60 is optional.
- * 16 or 32 bit wide SDRAM.
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* SoC must be defined first, before hardware.h is included */
-#define CONFIG_AT91SAM9XE
-#include <asm/hardware.h>
-
-/*
- * Warning: changing CONFIG_SYS_TEXT_BASE requires
- * adapting the initial boot program.
- */
-#define CONFIG_SYS_TEXT_BASE		0x20000000	/* start of SDRAM */
-
-/* Command line configuration */
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_XIMG
-#define CONFIG_CMD_ASKENV
-#define CONFIG_SYS_CBSIZE		256
-#define CONFIG_SYS_MAXARGS		16
-#define CONFIG_SYS_PBSIZE \
-	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_PROMPT		"TOP9000> "
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_CACHE
-
-/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* main clock xtal */
-
-/* Misc CPU related */
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_AT91RESET_EXTRST		/* assert external reset */
-
-/* general purpose I/O */
-#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
-#define CONFIG_AT91_GPIO
-#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
-
-/* serial console */
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
-#define	CONFIG_USART_ID			ATMEL_ID_SYS
-#define CONFIG_BAUDRATE			115200
-
-/* SD/MMC card */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_GENERIC_ATMEL_MCI
-#define CONFIG_SYS_MMC_CD_PIN		AT91_PIN_PC9
-#define CONFIG_CMD_MMC
-
-/* Ethernet */
-#define CONFIG_MACB
-#define CONFIG_SYS_PHY_ID	1
-#define CONFIG_RMII
-#define CONFIG_NET_RETRY_COUNT	20
-
-/* real time clock */
-#define CONFIG_RTC_AT91SAM9_RTT
-#define CONFIG_CMD_DATE
-
-#if defined(CONFIG_AT91SAM9XE)
-/*
- * NOR flash - use embedded flash of SAM9XE256/512
- * U-Boot will not fit into 128K !
- * 2010.09 will not fit into 256K with all options enabled !
- *
- * Layout:
- * 16kB	1st Bootloader
- * Rest U-Boot
- * the first sector (16kB) of EFLASH cannot be unprotected
- * with u-boot commands
- */
-# define CONFIG_AT91_EFLASH
-# define CONFIG_SYS_FLASH_BASE		ATMEL_BASE_FLASH
-# define CONFIG_SYS_MAX_FLASH_SECT	32
-# define CONFIG_SYS_MAX_FLASH_BANKS	1
-# define CONFIG_SYS_FLASH_PROTECTION
-# define CONFIG_EFLASH_PROTSECTORS	1	/* protect first sector */
-#endif
-
-/* SPI */
-#define CONFIG_ATMEL_SPI
-#define CONFIG_CMD_SPI
-
-/* RAMTRON FRAM */
-#define CONFIG_CMD_SF
-#define CONFIG_ATMEL_SPI0		/* SPI used for FRAM is SPI0 */
-#define FRAM_SPI_BUS		0
-#define FRAM_CS_NUM		0
-#define CONFIG_SPI_FRAM_RAMTRON
-#define CONFIG_SF_DEFAULT_SPEED	1000000	/* be conservative here... */
-#define CONFIG_SF_DEFAULT_MODE	SPI_MODE_0
-#define CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC	"FM25H20"
-
-/* Microchip ENC28J60 (second LAN) */
-#if defined(CONFIG_EVAL9000)
-# define CONFIG_ENC28J60
-# define CONFIG_ATMEL_SPI1		/* SPI used for ENC28J60 is SPI1 */
-# define ENC_SPI_BUS		1
-# define ENC_CS_NUM		0
-# define ENC_SPI_CLOCK	1000000
-#endif /* CONFIG_EVAL9000 */
-
-/*
- * SDRAM: 1 bank, min 32, max 128 MB
- * Initialized before u-boot gets started.
- */
-#define CONFIG_NR_DRAM_BANKS		1
-#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE		0x08000000
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01e00000)
-#define CONFIG_SYS_LOAD_ADDR \
-	(CONFIG_SYS_SDRAM_BASE + 0x01000000)
-/*
- * Initial stack pointer: 16k - GENERATED_GBL_DATA_SIZE in internal SRAM,
- * leaving the correct space for initial global data structure above
- * that address while providing maximum stack area below.
- */
-#define CONFIG_SYS_INIT_SP_ADDR \
-	(ATMEL_BASE_SRAM + 0x4000 - GENERATED_GBL_DATA_SIZE)
-
-/*
- * NAND flash: 256 MB (optional)
- *
- * Layout:
- * 640kB: u-boot (includes space for spare sectors, handled by
- * initial loader)
- * 2MB: kernel
- * rest: file system
- */
-#define CONFIG_NAND_ATMEL
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
-#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
-#define CONFIG_CMD_NAND
-
-/* USB */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE	ATMEL_UHP_BASE
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"top9000"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
-#define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
-
-/* I2C support must always be enabled */
-#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED	400000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
-
-#define I2C0_PORT			AT91_PIO_PORTA
-#define SDA0_PIN			23
-#define SCL0_PIN			24
-#define I2C1_PORT			AT91_PIO_PORTB
-#define SDA1_PIN			12
-#define SCL1_PIN			13
-#define I2C_SOFT_DECLARATIONS		void iic_init(void);\
-					int iic_read(void);\
-					void iic_sda(int);\
-					void iic_scl(int);
-#define I2C_ACTIVE
-#define I2C_TRISTATE
-#define I2C_INIT			iic_init()
-#define I2C_READ			iic_read()
-#define I2C_SDA(bit)			iic_sda(bit)
-#define I2C_SCL(bit)			iic_scl(bit)
-#define I2C_DELAY			udelay(3)
-/* EEPROM configuration */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
-#define CONFIG_SYS_EEPROM_SIZE		0x2000
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
-/* later: #define CONFIG_I2C_ENV_EEPROM_BUS	0 */
-/* ENV is always in I2C-EEPROM */
-#define CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_ENV_OFFSET		0x1000
-#define CONFIG_ENV_SIZE			0x0f00
-/* VPD settings */
-#define CONFIG_SYS_I2C_FACT_ADDR	0x57
-#define CONFIG_SYS_FACT_OFFSET		0x1F00
-#define CONFIG_SYS_FACT_SIZE		0x0100
-/* later: #define CONFIG_MISC_INIT_R */
-/* define the next only if you want to allow users to enter VPD data */
-#define CONFIG_SYS_FACT_ENTRY
-#ifndef __ASSEMBLY__
-extern void read_factory_r(void);
-#endif
-
-/*
- * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
- * data on the serial line may interrupt the boot sequence.
- */
-#define CONFIG_BOOTDELAY		1
-#define CONFIG_AUTOBOOT
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT \
-	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
-#define CONFIG_AUTOBOOT_DELAY_STR	"d"
-#define CONFIG_AUTOBOOT_STOP_STR	" "
-
-/*
- * add filesystem commands if we have at least 1 storage
- * media with filesystem
- */
-#if defined(CONFIG_NAND_ATMEL) \
-	|| defined(CONFIG_USB_ATMEL) \
-	|| defined(CONFIG_MMC)
-# define CONFIG_DOS_PARTITION
-# define CONFIG_CMD_FAT
-# define CONFIG_CMD_EXT2
-/* later: #define CONFIG_CMD_JFFS2 */
-#endif
-
-/* add NET commands if we have at least 1 LAN */
-#if defined(CONFIG_MACB) || defined(CONFIG_ENC28J60)
-# define CONFIG_CMD_PING
-# define CONFIG_CMD_DHCP
-# define CONFIG_CMD_MII
-/* is this really needed ? */
-# define CONFIG_RESET_PHY_R
-/* BOOTP options */
-# define CONFIG_BOOTP_BOOTFILESIZE
-# define CONFIG_BOOTP_BOOTPATH
-# define CONFIG_BOOTP_GATEWAY
-# define CONFIG_BOOTP_HOSTNAME
-#endif
-
-/* linux in NAND flash */
-#define CONFIG_BOOTCOUNT_LIMIT	1
-#define CONFIG_BOOTCOMMAND \
-	"nand read 0x21000000 0xA0000 0x200000; bootm"
-#define CONFIG_BOOTARGS \
-	"console=ttyS0,115200 " \
-	"root=/dev/mtdblock2 " \
-	"mtdparts=atmel_nand:" \
-		"640k(uboot)ro," \
-		"2M(linux)," \
-		"16M(root)," \
-		"-(rest) " \
-	"rw "\
-	"rootfstype=jffs2"
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN \
-	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-
-#endif