diff options
| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | 2018-01-16 20:44:25 +0300 |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2018-01-19 17:59:35 +0300 |
| commit | 075cbae1639189a9d9c76e74e954721f354f397a (patch) | |
| tree | 7d10db927078e61b2b4b718ee18cdbc521b73e66 /include/dt-bindings/power | |
| parent | 5aec2569a67f33c4ee58f7eb3a8a3d75751e3d49 (diff) | |
ARC: HSDK: CGU: Update AXI, TUN, ARC clock options
Update default AXI, TUN, ARC clock set options:
instead of changing only IDIV divider settings adjust also domain PLL
settings.
Add support of TUN_ROM and TUN_PWM clocks (subclocks of TUNN_PLL)
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'include/dt-bindings/power')
0 files changed, 0 insertions, 0 deletions