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authorLokesh Vutla <lokeshvutla@ti.com>2018-11-15 11:04:50 +0530
committerTom Rini <trini@konsulko.com>2018-11-26 22:52:11 -0500
commitccdb7c2255bde555bd0d4e104f8d228e25b76572 (patch)
tree0729f8f35361062cc31ec767dc5f7852c63a6396 /include
parentf7bb20a53e829ce0b4d3c22c704e80b490d24016 (diff)
armv7r: K3: Allow SPL to run only on core 0
Based on the MCU R5 efuse settings, R5F cores in MCU domain either work in split mode or in lock step mode. If efuse settings are in lockstep mode: ROM release R5 cores and SPL continues to run on the R5 core is lockstep mode. If efuse settings are in split mode: ROM releases both the R5 cores simultaneously and allow SPL to run on both the cores. In this case it is bootloader's responsibility to detect core 1 and park it. Else both the core will be running bootloader independently which might result in an unexpected behaviour. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/am65x_evm.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
index 484c5ef2fe..31749c6d06 100644
--- a/include/configs/am65x_evm.h
+++ b/include/configs/am65x_evm.h
@@ -29,7 +29,9 @@
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin"
#endif
+#ifndef CONFIG_CPU_V7R
#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \