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authorJerry Huang <Chang-Ming.Huang@freescale.com>2011-11-03 15:18:06 +0800
committerKumar Gala <galak@kernel.crashing.org>2011-11-11 07:48:54 -0600
commit71775d3b54780f1901ff6eac7c5ae05676938107 (patch)
treeea6e79554893a014d014f9fd49d9de62e23c10ff /nand_spl
parent8d22ddca3db2577b7f2bf1040972231279288847 (diff)
powerpc/mpc85xx: Set SYSCLK to the required frequency
For ICS307-02, there is one general expression to generate SYSCLK: CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) If we want the required frequency for SYSCLK, we must find one solution to generate this frequency, this solution includes VDW, RDW and OD. For OD, there are only eight option value: 10, 2, 8, 4, 5, 7, 3, 6. For RDW, the range is 1 to 127. For VDW, the range is 4 to 511. First, we use one OD, RDW and required SYSCLK to calculate the VDW, if VDW is in it's range, we will calculate the CLK1Frequency with the OD, RDW and VDW calculated, and we will check this percent (CLK1Frequency / required SYSCLK), and the precision is 1/1000. if the percent is less than 1/1000, we think the CLK1Frequency is we want. Otherwise, We will continue to calculate it with the next OD and RDW. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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