diff options
| -rw-r--r-- | arch/arm/cpu/arm720t/tegra-common/cpu.c | 48 | ||||
| -rw-r--r-- | arch/arm/cpu/arm720t/tegra-common/cpu.h | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/tegra-common/ap.c | 43 | ||||
| -rw-r--r-- | arch/arm/cpu/tegra20-common/pmu.c | 4 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/ap.h | 20 | ||||
| -rw-r--r-- | board/nvidia/common/emc.c | 2 |
6 files changed, 84 insertions, 37 deletions
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index 119342e957..9294611be8 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -143,26 +143,34 @@ void init_pllx(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX]; - int chip_type; + int soc_type, sku_info, chip_sku; enum clock_osc_freq osc; struct clk_pll_table *sel; debug("init_pllx entry\n"); - /* get chip type */ - chip_type = tegra_get_chip_type(); - debug(" init_pllx: chip_type = %d\n", chip_type); + /* get SOC (chip) type */ + soc_type = tegra_get_chip(); + debug(" init_pllx: SoC = 0x%02X\n", soc_type); + + /* get SKU info */ + sku_info = tegra_get_sku_info(); + debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info); + + /* get chip SKU, combo of the above info */ + chip_sku = tegra_get_chip_sku(); + debug(" init_pllx: Chip SKU = %d\n", chip_sku); /* get osc freq */ osc = clock_get_osc_freq(); - debug(" init_pllx: osc = %d\n", osc); + debug(" init_pllx: osc = %d\n", osc); /* set pllx */ - sel = &tegra_pll_x_table[chip_type][osc]; + sel = &tegra_pll_x_table[chip_sku][osc]; pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon); - /* adjust PLLP_out1-4 on T30/T114 */ - if (chip_type == TEGRA_SOC_T30 || chip_type == TEGRA_SOC_T114) { + /* adjust PLLP_out1-4 on T3x/T114 */ + if (soc_type >= CHIPID_TEGRA30) { debug(" init_pllx: adjusting PLLP out freqs\n"); adjust_pllp_out_freqs(); } @@ -287,7 +295,7 @@ void reset_A9_cpu(int reset) void clock_enable_coresight(int enable) { u32 rst, src = 2; - int chip; + int soc_type; debug("clock_enable_coresight entry\n"); clock_set_enable(PERIPH_ID_CORESIGHT, enable); @@ -295,21 +303,21 @@ void clock_enable_coresight(int enable) if (enable) { /* - * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by - * 1.5, giving an effective frequency of 144MHz. - * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor - * (bits 7:0), so 00000001b == 1.5 (n+1 + .5) - * - * Clock divider request for 204MHz would setup CSITE clock as - * 144MHz for PLLP base 216MHz and 204MHz for PLLP base 408MHz + * Put CoreSight on PLLP_OUT0 and divide it down as per + * PLLP base frequency based on SoC type (T20/T30/T114). + * Clock divider request would setup CSITE clock as 144MHz + * for PLLP base 216MHz and 204MHz for PLLP base 408MHz */ - chip = tegra_get_chip_type(); - if (chip == TEGRA_SOC_T30 || chip == TEGRA_SOC_T114) + + soc_type = tegra_get_chip(); + if (soc_type == CHIPID_TEGRA30 || soc_type == CHIPID_TEGRA114) src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000); - else if (chip == TEGRA_SOC_T20 || chip == TEGRA_SOC_T25) + else if (soc_type == CHIPID_TEGRA20) src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000); else - printf("%s: Unknown chip type %X!\n", __func__, chip); + printf("%s: Unknown SoC type %X!\n", + __func__, soc_type); + clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src); /* Unlock the CPU CoreSight interfaces */ diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h b/arch/arm/cpu/arm720t/tegra-common/cpu.h index e8e05d77aa..f9bfb32445 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.h +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.h @@ -80,5 +80,7 @@ void init_pllx(void); void powerup_cpu(void); void reset_A9_cpu(int reset); void start_cpu(u32 reset_vector); -int tegra_get_chip_type(void); +int tegra_get_chip(void); +int tegra_get_sku_info(void); +int tegra_get_chip_sku(void); void adjust_pllp_out_freqs(void); diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index a739fe2b5e..9b77b2b82e 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -34,25 +34,44 @@ #include <asm/arch-tegra/tegra.h> #include <asm/arch-tegra/warmboot.h> -int tegra_get_chip_type(void) +int tegra_get_chip(void) { - struct apb_misc_gp_ctlr *gp; - struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; - uint tegra_sku_id, rev; + int rev; + struct apb_misc_gp_ctlr *gp = + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; /* * This is undocumented, Chip ID is bits 15:8 of the register * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for * Tegra30, and 0x35 for T114. */ - gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; + debug("%s: CHIPID is 0x%02X\n", __func__, rev); + + return rev; +} + +int tegra_get_sku_info(void) +{ + int sku_id; + struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; + + sku_id = readl(&fuse->sku_info) & 0xff; + debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id); + + return sku_id; +} + +int tegra_get_chip_sku(void) +{ + uint sku_id, chip_id; - tegra_sku_id = readl(&fuse->sku_info) & 0xff; + chip_id = tegra_get_chip(); + sku_id = tegra_get_sku_info(); - switch (rev) { + switch (chip_id) { case CHIPID_TEGRA20: - switch (tegra_sku_id) { + switch (sku_id) { case SKU_ID_T20: return TEGRA_SOC_T20; case SKU_ID_T25SE: @@ -64,20 +83,22 @@ int tegra_get_chip_type(void) } break; case CHIPID_TEGRA30: - switch (tegra_sku_id) { + switch (sku_id) { case SKU_ID_T33: case SKU_ID_T30: return TEGRA_SOC_T30; } break; case CHIPID_TEGRA114: - switch (tegra_sku_id) { + switch (sku_id) { case SKU_ID_T114_ENG: return TEGRA_SOC_T114; } break; } - /* unknown sku id */ + /* unknown chip/sku id */ + printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n", + __func__, chip_id, sku_id); return TEGRA_SOC_UNKNOWN; } diff --git a/arch/arm/cpu/tegra20-common/pmu.c b/arch/arm/cpu/tegra20-common/pmu.c index 228295303c..4c5a5333d7 100644 --- a/arch/arm/cpu/tegra20-common/pmu.c +++ b/arch/arm/cpu/tegra20-common/pmu.c @@ -44,7 +44,7 @@ int pmu_set_nominal(void) int core, cpu, bus; /* by default, the table has been filled with T25 settings */ - switch (tegra_get_chip_type()) { + switch (tegra_get_chip_sku()) { case TEGRA_SOC_T20: core = VDD_CORE_NOMINAL_T20; cpu = VDD_CPU_NOMINAL_T20; @@ -54,7 +54,7 @@ int pmu_set_nominal(void) cpu = VDD_CPU_NOMINAL_T25; break; default: - debug("%s: Unknown chip type\n", __func__); + debug("%s: Unknown SKU id\n", __func__); return -1; } diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h index 5999f55460..f6d08c6598 100644 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ b/arch/arm/include/asm/arch-tegra/ap.h @@ -59,9 +59,25 @@ extern void _start(void); /** - * Works out the SOC type used for clocks settings + * Works out the SOC/SKU type used for clocks settings * * @return SOC type - see TEGRA_SOC... */ -int tegra_get_chip_type(void); +int tegra_get_chip_sku(void); + +/** + * Returns the pure SOC (chip ID) from the HIDREV register + * + * @return SOC ID - see CHIPID_TEGRAxx... + */ +int tegra_get_chip(void); + +/** + * Returns the SKU ID from the sku_info register + * + * @return SKU ID - see SKU_ID_Txx... + */ +int tegra_get_sku_info(void); + +/* Do any chip-specific cache config */ void config_cache(void); diff --git a/board/nvidia/common/emc.c b/board/nvidia/common/emc.c index 26b6ec7c3b..87d7aa25b7 100644 --- a/board/nvidia/common/emc.c +++ b/board/nvidia/common/emc.c @@ -40,7 +40,7 @@ int board_emc_init(void) { unsigned rate; - switch (tegra_get_chip_type()) { + switch (tegra_get_chip_sku()) { default: case TEGRA_SOC_T20: rate = EMC_SDRAM_RATE_T20; |