diff options
Diffstat (limited to 'arch/arm/cpu/arm720t/tegra-common/cpu.c')
| -rw-r--r-- | arch/arm/cpu/arm720t/tegra-common/cpu.c | 48 |
1 files changed, 28 insertions, 20 deletions
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index 119342e957..9294611be8 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -143,26 +143,34 @@ void init_pllx(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX]; - int chip_type; + int soc_type, sku_info, chip_sku; enum clock_osc_freq osc; struct clk_pll_table *sel; debug("init_pllx entry\n"); - /* get chip type */ - chip_type = tegra_get_chip_type(); - debug(" init_pllx: chip_type = %d\n", chip_type); + /* get SOC (chip) type */ + soc_type = tegra_get_chip(); + debug(" init_pllx: SoC = 0x%02X\n", soc_type); + + /* get SKU info */ + sku_info = tegra_get_sku_info(); + debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info); + + /* get chip SKU, combo of the above info */ + chip_sku = tegra_get_chip_sku(); + debug(" init_pllx: Chip SKU = %d\n", chip_sku); /* get osc freq */ osc = clock_get_osc_freq(); - debug(" init_pllx: osc = %d\n", osc); + debug(" init_pllx: osc = %d\n", osc); /* set pllx */ - sel = &tegra_pll_x_table[chip_type][osc]; + sel = &tegra_pll_x_table[chip_sku][osc]; pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon); - /* adjust PLLP_out1-4 on T30/T114 */ - if (chip_type == TEGRA_SOC_T30 || chip_type == TEGRA_SOC_T114) { + /* adjust PLLP_out1-4 on T3x/T114 */ + if (soc_type >= CHIPID_TEGRA30) { debug(" init_pllx: adjusting PLLP out freqs\n"); adjust_pllp_out_freqs(); } @@ -287,7 +295,7 @@ void reset_A9_cpu(int reset) void clock_enable_coresight(int enable) { u32 rst, src = 2; - int chip; + int soc_type; debug("clock_enable_coresight entry\n"); clock_set_enable(PERIPH_ID_CORESIGHT, enable); @@ -295,21 +303,21 @@ void clock_enable_coresight(int enable) if (enable) { /* - * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by - * 1.5, giving an effective frequency of 144MHz. - * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor - * (bits 7:0), so 00000001b == 1.5 (n+1 + .5) - * - * Clock divider request for 204MHz would setup CSITE clock as - * 144MHz for PLLP base 216MHz and 204MHz for PLLP base 408MHz + * Put CoreSight on PLLP_OUT0 and divide it down as per + * PLLP base frequency based on SoC type (T20/T30/T114). + * Clock divider request would setup CSITE clock as 144MHz + * for PLLP base 216MHz and 204MHz for PLLP base 408MHz */ - chip = tegra_get_chip_type(); - if (chip == TEGRA_SOC_T30 || chip == TEGRA_SOC_T114) + + soc_type = tegra_get_chip(); + if (soc_type == CHIPID_TEGRA30 || soc_type == CHIPID_TEGRA114) src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000); - else if (chip == TEGRA_SOC_T20 || chip == TEGRA_SOC_T25) + else if (soc_type == CHIPID_TEGRA20) src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000); else - printf("%s: Unknown chip type %X!\n", __func__, chip); + printf("%s: Unknown SoC type %X!\n", + __func__, soc_type); + clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src); /* Unlock the CPU CoreSight interfaces */ |