diff options
101 files changed, 926 insertions, 908 deletions
@@ -1696,11 +1696,6 @@ The following options need to be configured: - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4 - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4 - - drivers/i2c/zynq_i2c.c - - activate this driver with CONFIG_SYS_I2C_ZYNQ - - set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting - - set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr - - drivers/i2c/s3c24x0_i2c.c: - activate this driver with CONFIG_SYS_I2C_S3C24X0 - This driver adds i2c buses (11 for Exynos5250, Exynos5420 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ca50623480..2bbe47d8a2 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -186,6 +186,10 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zc1751-xm017-dc3.dtb \ zynqmp-zc1751-xm018-dc4.dtb \ zynqmp-zc1751-xm019-dc5.dtb +dtb-$(CONFIG_ARCH_VERSAL) += \ + versal-mini.dtb \ + versal-mini-emmc0.dtb \ + versal-mini-emmc1.dtb dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \ zynqmp-r5.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \ diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts new file mode 100644 index 0000000000..7f57d232b7 --- /dev/null +++ b/arch/arm/dts/versal-mini-emmc0.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal Mini eMMC0 Configuration + * + * (C) Copyright 2018-2019, Xilinx, Inc. + * + * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> + * Michal Simek <michal.simek@xilinx.com> + */ + +/dts-v1/; + +/ { + compatible = "xlnx,versal"; + #address-cells = <2>; + #size-cells = <2>; + model = "Xilinx Versal MINI eMMC0"; + + clk25: clk25 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <25000000>; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "okay"; + u-boot,dm-pre-reloc; + }; + + amba: amba { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + sdhci0: sdhci@f1040000 { + compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; + status = "okay"; + reg = <0x0 0xf1040000 0x0 0x10000>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clk25 &clk25>; + xlnx,device_id = <0>; + no-1-8-v; + xlnx,mio_bank = <0>; + #stream-id-cells = <1>; + }; + }; + + aliases { + serial0 = &dcc; + mmc0 = &sdhci0; + }; + + chosen { + stdout-path = "serial0:115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; +}; diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts new file mode 100644 index 0000000000..9ecb1ce5dc --- /dev/null +++ b/arch/arm/dts/versal-mini-emmc1.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal Mini eMMC1 Configuration + * + * (C) Copyright 2018-2019, Xilinx, Inc. + * + * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> + * Michal Simek <michal.simek@xilinx.com> + */ + +/dts-v1/; + +/ { + compatible = "xlnx,versal"; + #address-cells = <2>; + #size-cells = <2>; + model = "Xilinx Versal MINI eMMC1"; + + clk25: clk25 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <25000000>; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "okay"; + u-boot,dm-pre-reloc; + }; + + amba: amba { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + sdhci1: sdhci@f105000 { + compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; + status = "okay"; + reg = <0x0 0xf1050000 0x0 0x10000>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clk25 &clk25>; + xlnx,device_id = <1>; + no-1-8-v; + xlnx,mio_bank = <0>; + #stream-id-cells = <1>; + }; + }; + + aliases { + serial0 = &dcc; + mmc0 = &sdhci1; + }; + + chosen { + stdout-path = "serial0:115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; +}; diff --git a/arch/arm/dts/versal-mini.dts b/arch/arm/dts/versal-mini.dts new file mode 100644 index 0000000000..6a83981cc2 --- /dev/null +++ b/arch/arm/dts/versal-mini.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal Mini Configuration + * + * (C) Copyright 2019, Xilinx, Inc. + * + * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> + */ + +/dts-v1/; + +/ { + model = "Versal MINI"; + compatible = "xlnx,versal"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &dcc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0xfffc0000 0x0 0x40000>, <0x0 0x0 0x0 0x80000000>; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "okay"; + u-boot,dm-pre-reloc; + }; +}; diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 286059d56e..e1b0816a34 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -235,7 +235,7 @@ #size-cells = <0>; }; - sdhci0: sdhci@e0100000 { + sdhci0: mmc@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; @@ -245,7 +245,7 @@ reg = <0xe0100000 0x1000>; }; - sdhci1: sdhci@e0101000 { + sdhci1: mmc@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; diff --git a/arch/arm/dts/zynq-cc108.dts b/arch/arm/dts/zynq-cc108.dts index 5f8a0d2555..64d73ecbc5 100644 --- a/arch/arm/dts/zynq-cc108.dts +++ b/arch/arm/dts/zynq-cc108.dts @@ -12,8 +12,8 @@ /include/ "zynq-7000.dtsi" / { + model = "Xilinx CC108 board"; compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000"; - model = "Xilinx Zynq"; aliases { ethernet0 = &gem0; diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts index 79f878eab2..0766398605 100644 --- a/arch/arm/dts/zynq-microzed.dts +++ b/arch/arm/dts/zynq-microzed.dts @@ -9,7 +9,7 @@ / { model = "Zynq MicroZED Board"; - compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000"; + compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000"; aliases { serial0 = &uart1; diff --git a/arch/arm/dts/zynq-syzygy-hub.dts b/arch/arm/dts/zynq-syzygy-hub.dts index a30d667146..55f8e8a2da 100644 --- a/arch/arm/dts/zynq-syzygy-hub.dts +++ b/arch/arm/dts/zynq-syzygy-hub.dts @@ -16,6 +16,7 @@ ethernet0 = &gem0; serial0 = &uart0; mmc0 = &sdhci0; + i2c0 = &i2c1; }; memory@0 { @@ -26,6 +27,7 @@ chosen { bootargs = ""; stdout-path = "serial0:115200n8"; + xlnx,eeprom = &eeprom; }; usb_phy0: phy0 { @@ -52,6 +54,10 @@ &i2c1 { status = "okay"; + eeprom: eeprom@57 { + compatible = "atmel,24c08"; /* not sure if this is correct */ + reg = <0x57>; + }; }; &sdhci0 { diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 12e35618f8..54231cd580 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -7,7 +7,7 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZC702 Development Board"; + model = "Xilinx ZC702 board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; aliases { diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index f24364b385..84729e9feb 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -7,7 +7,7 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZC706 Development Board"; + model = "Xilinx ZC706 board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; aliases { diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index a779672f3a..e1f34653ec 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -8,8 +8,8 @@ #include "zynq-7000.dtsi" / { + model = "Xilinx ZC770 XM010 board"; compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; - model = "Xilinx Zynq"; aliases { ethernet0 = &gem0; @@ -58,7 +58,6 @@ compatible = "atmel,24c02"; reg = <0x52>; }; - }; &qspi { diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index 3fe6eb559e..1123bfc743 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -8,8 +8,8 @@ #include "zynq-7000.dtsi" / { + model = "Xilinx ZC770 XM011 board"; compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000"; - model = "Xilinx Zynq"; aliases { i2c0 = &i2c1; diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index 19d5b275ae..0d001c9161 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -8,8 +8,8 @@ #include "zynq-7000.dtsi" / { + model = "Xilinx ZC770 XM012 board"; compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; - model = "Xilinx Zynq"; aliases { i2c0 = &i2c0; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index efd0833eab..05a49982cc 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -8,8 +8,8 @@ #include "zynq-7000.dtsi" / { + model = "Xilinx ZC770 XM013 board"; compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; - model = "Xilinx Zynq"; aliases { ethernet0 = &gem1; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 9c505fb7b8..d2b7fc2c99 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -7,8 +7,8 @@ #include "zynq-7000.dtsi" / { - model = "Zynq Zed Development Board"; - compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; + model = "Avnet ZedBoard board"; + compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts index 3844822305..0ac54ebbdc 100644 --- a/arch/arm/dts/zynq-zybo.dts +++ b/arch/arm/dts/zynq-zybo.dts @@ -7,7 +7,7 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZYBO Development Board"; + model = "Digilent Zybo board"; compatible = "digilent,zynq-zybo", "xlnx,zynq-7000"; aliases { diff --git a/arch/arm/dts/zynqmp-zc1275-revB.dts b/arch/arm/dts/zynqmp-zc1275-revB.dts index e84b2da164..1a7975b551 100644 --- a/arch/arm/dts/zynqmp-zc1275-revB.dts +++ b/arch/arm/dts/zynqmp-zc1275-revB.dts @@ -47,7 +47,7 @@ #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; + spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 05491e9bbc..5285f62d1a 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -296,7 +296,6 @@ compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; - }; &uart1 { @@ -332,7 +331,6 @@ &watchdog0 { status = "okay"; - reset-on-timeout; }; &xilinx_ams { diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 05be919f6f..0e96a36188 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -36,6 +36,7 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; + xlnx,eeprom = &eeprom; }; memory@0 { @@ -360,7 +361,6 @@ status = "disabled"; /* unreachable */ reg = <0x20>; }; - max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; @@ -485,21 +485,6 @@ #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ - dev@19 { - reg = <0x19>; - }; - dev@30 { - reg = <0x30>; - }; - dev@35 { - reg = <0x35>; - }; - dev@36 { - reg = <0x36>; - }; - dev@51 { - reg = <0x51>; - }; }; i2c@4 { #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index becc6a0fe1..623d2c96cd 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -34,6 +34,7 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; + xlnx,eeprom = &eeprom; }; memory@0 { diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 7735e9d2c8..00f6e30ef3 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -36,6 +36,7 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; + xlnx,eeprom = &eeprom; }; memory@0 { @@ -462,26 +463,6 @@ #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ - dev@19 { /* u-boot detection */ - compatible = "xxx"; - reg = <0x19>; - }; - dev@30 { /* u-boot detection */ - compatible = "xxx"; - reg = <0x30>; - }; - dev@35 { /* u-boot detection */ - compatible = "xxx"; - reg = <0x35>; - }; - dev@36 { /* u-boot detection */ - compatible = "xxx"; - reg = <0x36>; - }; - dev@51 { /* u-boot detection - maybe SPD */ - compatible = "xxx"; - reg = <0x51>; - }; }; i2c@4 { #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 172e6cc2ca..58021be9bf 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -35,6 +35,7 @@ chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; + xlnx,eeprom = &eeprom; }; memory@0 { @@ -399,26 +400,6 @@ #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ - dev@19 { /* u-boot detection FIXME */ - compatible = "xxx"; - reg = <0x19>; - }; - dev@30 { /* u-boot detection */ - compatible = "xxx"; - reg = <0x30>; - }; - dev@35 { /* u-boot detection */ - compatible = "xxx"; - reg = <0x35>; - }; - dev@36 { /* u-boot detection */ - compatible = "xxx"; - reg = <0x36>; - }; - dev@51 { /* u-boot detection - maybe SPD */ - compatible = "xxx"; - reg = <0x51>; - }; }; i2c@4 { #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 831d6e1ecc..dfb6ebc64c 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -58,7 +58,7 @@ }; idle-states { - entry-method = "arm,psci"; + entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; @@ -884,7 +884,8 @@ interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; - timeout-sec = <10>; + timeout-sec = <60>; + reset-on-timeout; }; xilinx_ams: ams@ffa50000 { diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig index 9cee97b748..26d1756371 100644 --- a/arch/arm/mach-versal/Kconfig +++ b/arch/arm/mach-versal/Kconfig @@ -41,4 +41,17 @@ config VERSAL_OF_BOARD_DTB_ADDR default 0x1000 depends on OF_BOARD +config IOU_SWITCH_DIVISOR0 + hex "IOU switch divisor0" + default 0x20 + help + Setup time clock divisor for input clock. + +config SYS_MEM_RSVD_FOR_MMU + bool "Reserve memory for MMU Table" + help + If defined this option is used to setup different space for + MMU table than the one which will be allocated during + relocation. + endif diff --git a/arch/arm/mach-versal/Makefile b/arch/arm/mach-versal/Makefile index c230239320..ca12e29170 100644 --- a/arch/arm/mach-versal/Makefile +++ b/arch/arm/mach-versal/Makefile @@ -6,3 +6,4 @@ obj-y += clk.o obj-y += cpu.o +obj-$(CONFIG_SYS_MEM_RSVD_FOR_MMU) += mp.o diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 1fd3c246c1..70c1908ec4 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -7,6 +7,10 @@ #include <common.h> #include <asm/armv8/mmu.h> #include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; static struct mm_region versal_mem_map[] = { { @@ -68,6 +72,17 @@ u64 get_page_table_size(void) return 0x14000; } +#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) +int reserve_mmu(void) +{ + tcm_init(TCM_LOCK); + gd->arch.tlb_size = PGTABLE_SIZE; + gd->arch.tlb_addr = VERSAL_TCM_BASE_ADDR; + + return 0; +} +#endif + #if defined(CONFIG_OF_BOARD) void *board_fdt_blob_setup(void) { diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h index aad742625b..23fbc3d8f5 100644 --- a/arch/arm/mach-versal/include/mach/hardware.h +++ b/arch/arm/mach-versal/include/mach/hardware.h @@ -11,11 +11,15 @@ #define IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 struct crlapb_regs { - u32 reserved0[69]; + u32 reserved0[67]; + u32 cpu_r5_ctrl; + u32 reserved; u32 iou_switch_ctrl; /* 0x114 */ u32 reserved1[13]; u32 timestamp_ref_ctrl; /* 0x14c */ - u32 reserved2[126]; + u32 reserved3[108]; + u32 rst_cpu_r5; + u32 reserved2[17]; u32 rst_timestamp; /* 0x348 */ }; @@ -32,3 +36,18 @@ struct iou_scntrs_regs { }; #define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_IOU_SCNTR_SECURE) + +#define VERSAL_TCM_BASE_ADDR 0xFFE00000 +#define VERSAL_TCM_SIZE 0x40000 + +#define VERSAL_RPU_BASEADDR 0xFF9A0000 + +struct rpu_regs { + u32 rpu_glbl_ctrl; + u32 reserved0[63]; + u32 rpu0_cfg; /* 0x100 */ + u32 reserved1[63]; + u32 rpu1_cfg; /* 0x200 */ +}; + +#define rpu_base ((struct rpu_regs *)VERSAL_RPU_BASEADDR) diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h index 677facba5e..1dc7bf6656 100644 --- a/arch/arm/mach-versal/include/mach/sys_proto.h +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -3,4 +3,9 @@ * Copyright 2016 - 2018 Xilinx, Inc. */ -/* Empty file - for compilation */ +enum { + TCM_LOCK, + TCM_SPLIT, +}; + +void tcm_init(u8 mode); diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c new file mode 100644 index 0000000000..4b434b0ac3 --- /dev/null +++ b/arch/arm/mach-versal/mp.c @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2019 Xilinx, Inc. + * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define HALT 0 +#define RELEASE 1 + +#define VERSAL_RPU_CFG_CPU_HALT_MASK 0x01 +#define VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK 0x08 +#define VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK 0x40 +#define VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK 0x10 + +#define VERSAL_CRLAPB_RST_LPD_AMBA_RST_MASK 0x04 +#define VERSAL_CRLAPB_RST_LPD_R50_RST_MASK 0x01 +#define VERSAL_CRLAPB_RST_LPD_R51_RST_MASK 0x02 +#define VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK 0x10 +#define VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000 + +void set_r5_halt_mode(u8 halt, u8 mode) +{ + u32 tmp; + + tmp = readl(&rpu_base->rpu0_cfg); + if (halt == HALT) + tmp &= ~VERSAL_RPU_CFG_CPU_HALT_MASK; + else + tmp |= VERSAL_RPU_CFG_CPU_HALT_MASK; + writel(tmp, &rpu_base->rpu0_cfg); + + if (mode == TCM_LOCK) { + tmp = readl(&rpu_base->rpu1_cfg); + if (halt == HALT) + tmp &= ~VERSAL_RPU_CFG_CPU_HALT_MASK; + else + tmp |= VERSAL_RPU_CFG_CPU_HALT_MASK; + writel(tmp, &rpu_base->rpu1_cfg); + } +} + +void set_r5_tcm_mode(u8 mode) +{ + u32 tmp; + + tmp = readl(&rpu_base->rpu_glbl_ctrl); + if (mode == TCM_LOCK) { + tmp &= ~VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK; + tmp |= VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK | + VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK; + } else { + tmp |= VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK; + tmp &= ~(VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK | + VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK); + } + + writel(tmp, &rpu_base->rpu_glbl_ctrl); +} + +void release_r5_reset(u8 mode) +{ + u32 tmp; + + tmp = readl(&crlapb_base->rst_cpu_r5); + tmp &= ~(VERSAL_CRLAPB_RST_LPD_AMBA_RST_MASK | + VERSAL_CRLAPB_RST_LPD_R50_RST_MASK | + VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK); + + if (mode == TCM_LOCK) + tmp &= ~VERSAL_CRLAPB_RST_LPD_R51_RST_MASK; + + writel(tmp, &crlapb_base->rst_cpu_r5); +} + +void enable_clock_r5(void) +{ + u32 tmp; + + tmp = readl(&crlapb_base->cpu_r5_ctrl); + tmp |= VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK; + writel(tmp, &crlapb_base->cpu_r5_ctrl); +} + +void initialize_tcm(bool mode) +{ + if (!mode) { + set_r5_tcm_mode(TCM_LOCK); + set_r5_halt_mode(HALT, TCM_LOCK); + enable_clock_r5(); + release_r5_reset(TCM_LOCK); + } else { + set_r5_tcm_mode(TCM_SPLIT); + set_r5_halt_mode(HALT, TCM_SPLIT); + enable_clock_r5(); + release_r5_reset(TCM_SPLIT); + } +} + +void tcm_init(u8 mode) +{ + puts("WARNING: Initializing TCM overwrites TCM content\n"); + initialize_tcm(mode); + memset((void *)VERSAL_TCM_BASE_ADDR, 0, VERSAL_TCM_SIZE); +} diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h index 58b6f95395..5412ed6827 100644 --- a/arch/arm/mach-zynq/include/mach/hardware.h +++ b/arch/arm/mach-zynq/include/mach/hardware.h @@ -9,8 +9,6 @@ #define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000 #define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000 #define ZYNQ_SCU_BASEADDR 0xF8F00000 -#define ZYNQ_I2C_BASEADDR0 0xE0004000 -#define ZYNQ_I2C_BASEADDR1 0xE0005000 #define ZYNQ_QSPI_BASEADDR 0xE000D000 #define ZYNQ_SMC_BASEADDR 0xE000E000 #define ZYNQ_NAND_BASEADDR 0xE1000000 diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index e9f7e7e489..9bb5a5c202 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -99,6 +99,17 @@ config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED config ZYNQ_SDHCI_MAX_FREQ default 200000000 +config SPL_ZYNQMP_TWO_SDHCI + bool "Enable booting from both SDHCIs" + depends on SPL + help + This option reflects that board has two SDHCI controllers which + platform can use as boot device. This option ensures that SPL will + setup BOOT_DEVICE_MMC2 for SDHCI1 controller and BOOT_DEVICE_MMC1 for + SDHCI0 controller. Platforms which have only one SDHCI controller + shouldn't enable this option because it for software SDHCI0 or SDHCI1 + are both covered by BOOT_DEVICE_MMC1. + config SPL_ZYNQMP_ALT_BOOTMODE hex default 0x0 if JTAG_MODE diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index efb4bba4b8..a0d776166d 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -7,9 +7,6 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H -#define ZYNQ_I2C_BASEADDR0 0xFF020000 -#define ZYNQ_I2C_BASEADDR1 0xFF030000 - #define ARASAN_NAND_BASEADDR 0xFF100000 #define ZYNQMP_TCM_BASE_ADDR 0xFFE00000 diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index fb3955c93f..f6f5414201 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -85,7 +85,7 @@ u32 spl_boot_device(void) case SD_MODE1: case SD1_LSHFT_MODE: /* not working on silicon v1 */ /* if both controllers enabled, then these two are the second controller */ -#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1) +#if defined(SPL_ZYNQMP_TWO_SDHCI) return BOOT_DEVICE_MMC2; /* else, fall through, the one SDHCI controller that is enabled is number 1 */ #endif diff --git a/board/opalkelly/zynq/board.c b/board/opalkelly/zynq/board.c index a95c9d1eff..ee666185ec 100644 --- a/board/opalkelly/zynq/board.c +++ b/board/opalkelly/zynq/board.c @@ -1 +1,3 @@ +#include "../../xilinx/common/board.c" + #include "../../xilinx/zynq/board.c" diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c new file mode 100644 index 0000000000..7e6340bad6 --- /dev/null +++ b/board/xilinx/common/board.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2014 - 2019 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + */ + +#include <common.h> +#include <dm/uclass.h> +#include <i2c.h> + +int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) +{ + int ret = -EINVAL; + +#if defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) + struct udevice *dev; + ofnode eeprom; + + eeprom = ofnode_get_chosen_node("xlnx,eeprom"); + if (!ofnode_valid(eeprom)) + return -ENODEV; + + debug("%s: Path to EEPROM %s\n", __func__, + ofnode_get_chosen_prop("xlnx,eeprom")); + + ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev); + if (ret) + return ret; + + ret = dm_i2c_read(dev, CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, ethaddr, 6); + if (ret) + debug("%s: I2C EEPROM MAC address read failed\n", __func__); + else + debug("%s: I2C EEPROM MAC %pM\n", __func__, ethaddr); +#endif + + return ret; +} diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 2b3a40b73a..90751477b5 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -21,42 +21,46 @@ int board_init(void) int board_early_init_r(void) { - if (current_el() == 3) { - u32 val; - - writel(IOU_SWITCH_CTRL_CLKACT_BIT | - (0x20 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), - &crlapb_base->iou_switch_ctrl); - - /* Global timer init - Program time stamp reference clk */ - val = readl(&crlapb_base->timestamp_ref_ctrl); - val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; - writel(val, &crlapb_base->timestamp_ref_ctrl); - - debug("ref ctrl 0x%x\n", - readl(&crlapb_base->timestamp_ref_ctrl)); - - /* Clear reset of timestamp reg */ - writel(0, &crlapb_base->rst_timestamp); - - /* - * Program freq register in System counter and - * enable system counter. - */ - writel(COUNTER_FREQUENCY, - &iou_scntr_secure->base_frequency_id_register); - - debug("counter val 0x%x\n", - readl(&iou_scntr_secure->base_frequency_id_register)); - - writel(IOU_SCNTRS_CONTROL_EN, - &iou_scntr_secure->counter_control_register); - - debug("scntrs control 0x%x\n", - readl(&iou_scntr_secure->counter_control_register)); - debug("timer 0x%llx\n", get_ticks()); - debug("timer 0x%llx\n", get_ticks()); - } + u32 val; + + if (current_el() != 3) + return 0; + + debug("iou_switch ctrl div0 %x\n", + readl(&crlapb_base->iou_switch_ctrl)); + + writel(IOU_SWITCH_CTRL_CLKACT_BIT | + (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), + &crlapb_base->iou_switch_ctrl); + + /* Global timer init - Program time stamp reference clk */ + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + debug("ref ctrl 0x%x\n", + readl(&crlapb_base->timestamp_ref_ctrl)); + + /* Clear reset of timestamp reg */ + writel(0, &crlapb_base->rst_timestamp); + + /* + * Program freq register in System counter and + * enable system counter. + */ + writel(COUNTER_FREQUENCY, + &iou_scntr_secure->base_frequency_id_register); + + debug("counter val 0x%x\n", + readl(&iou_scntr_secure->base_frequency_id_register)); + + writel(IOU_SCNTRS_CONTROL_EN, + &iou_scntr_secure->counter_control_register); + + debug("scntrs control 0x%x\n", + readl(&iou_scntr_secure->counter_control_register)); + debug("timer 0x%llx\n", get_ticks()); + debug("timer 0x%llx\n", get_ticks()); return 0; } diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index e7645be189..8d33015439 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -4,6 +4,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-y := board.o +obj-y += ../common/board.o ifneq ($(CONFIG_XILINX_PS_INIT_FILE),"") PS_INIT_FILE := $(shell cd $(srctree); readlink -f $(CONFIG_XILINX_PS_INIT_FILE)) diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 614d93c082..b4b84df576 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -8,6 +8,7 @@ #include <dm/uclass.h> #include <fdtdec.h> #include <fpga.h> +#include <malloc.h> #include <mmc.h> #include <watchdog.h> #include <wdt.h> @@ -53,39 +54,54 @@ int board_init(void) int board_late_init(void) { + int env_targets_len = 0; + const char *mode; + char *new_targets; + char *env_targets; + switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { case ZYNQ_BM_QSPI: + mode = "qspi"; env_set("modeboot", "qspiboot"); break; case ZYNQ_BM_NAND: + mode = "nand"; env_set("modeboot", "nandboot"); break; case ZYNQ_BM_NOR: + mode = "nor"; env_set("modeboot", "norboot"); break; case ZYNQ_BM_SD: + mode = "mmc"; env_set("modeboot", "sdboot"); break; case ZYNQ_BM_JTAG: + mode = "pxe dhcp"; env_set("modeboot", "jtagboot"); break; default: + mode = ""; env_set("modeboot", ""); break; } - return 0; -} + /* + * One terminating char + one byte for space between mode + * and default boot_targets + */ + env_targets = env_get("boot_targets"); + if (env_targets) + env_targets_len = strlen(env_targets); -int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) -{ -#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ - defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) - if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, - CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, - ethaddr, 6)) - printf("I2C EEPROM MAC address read failed\n"); -#endif + new_targets = calloc(1, strlen(mode) + env_targets_len + 2); + if (!new_targets) + return -ENOMEM; + + sprintf(new_targets, "%s %s", mode, + env_targets ? env_targets : ""); + + env_set("boot_targets", new_targets); return 0; } diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile index 960b81fc58..80f8ca7e1e 100644 --- a/board/xilinx/zynqmp/Makefile +++ b/board/xilinx/zynqmp/Makefile @@ -4,6 +4,7 @@ # Michal Simek <michal.simek@xilinx.com> obj-y := zynqmp.o +obj-y += ../common/board.o ifneq ($(CONFIG_XILINX_PS_INIT_FILE),"") PS_INIT_FILE := $(shell cd $(srctree); readlink -f $(CONFIG_XILINX_PS_INIT_FILE)) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 41e88b03f9..5e1d2116bc 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -20,7 +20,6 @@ #include <usb.h> #include <dwc3-uboot.h> #include <zynqmppl.h> -#include <i2c.h> #include <g_dnl.h> DECLARE_GLOBAL_DATA_PTR; @@ -409,22 +408,6 @@ int board_early_init_r(void) return 0; } -int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) -{ -#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ - defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \ - defined(CONFIG_ZYNQ_EEPROM_BUS) - i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS); - - if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, - CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, - ethaddr, 6)) - printf("I2C EEPROM MAC address read failed\n"); -#endif - - return 0; -} - unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, char * const argv[]) { @@ -531,6 +514,36 @@ static u32 reset_reason(void) return ret; } +static int set_fdtfile(void) +{ + char *compatible, *fdtfile; + const char *suffix = ".dtb"; + const char *vendor = "xilinx/"; + + if (env_get("fdtfile")) + return 0; + + compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL); + if (compatible) { + debug("Compatible: %s\n", compatible); + + /* Discard vendor prefix */ + strsep(&compatible, ","); + + fdtfile = calloc(1, strlen(vendor) + strlen(compatible) + + strlen(suffix) + 1); + if (!fdtfile) + return -ENOMEM; + + sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix); + + env_set("fdtfile", fdtfile); + free(fdtfile); + } + + return 0; +} + int board_late_init(void) { u32 reg = 0; @@ -553,6 +566,10 @@ int board_late_init(void) return 0; } + ret = set_fdtfile(); + if (ret) + return ret; + ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®); if (ret) return -EINVAL; diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig index 3c0f2a54af..15a6827893 100644 --- a/configs/avnet_ultra96_rev1_defconfig +++ b/configs/avnet_ultra96_rev1_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu100" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -49,8 +48,10 @@ CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_DM_GPIO=y CONFIG_XILINX_GPIO=y -CONFIG_SYS_I2C_ZYNQ=y -CONFIG_ZYNQ_I2C1=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig index 545042f4bd..82354a5156 100644 --- a/configs/bitmain_antminer_s9_defconfig +++ b/configs/bitmain_antminer_s9_defconfig @@ -42,7 +42,6 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="bitmain-antminer-s9" CONFIG_ENV_IS_IN_NAND=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index 75139d93b3..131f8f1660 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -13,11 +13,9 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_IMAGE_FORMAT_LEGACY=y -CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_PROMPT="Zynq> " -CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y @@ -36,8 +34,8 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQPL=y CONFIG_DM_GPIO=y -CONFIG_SYS_I2C_ZYNQ=y -CONFIG_ZYNQ_I2C1=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index 73dc9531cd..352976b7d3 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -11,7 +11,6 @@ CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt" CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=0 -CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="zynq-uboot> " diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index e379a8e3d4..9b004acb23 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -11,7 +11,6 @@ CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt" CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=0 -CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="zynq-uboot> " diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index a7bc257c97..e45055756f 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -11,7 +11,6 @@ CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt" CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=0 -CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="zynq-uboot> " diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig new file mode 100644 index 0000000000..a79f096a57 --- /dev/null +++ b/configs/xilinx_versal_mini_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini_qspi" +CONFIG_ARCH_VERSAL=y +CONFIG_SYS_TEXT_BASE=0xFFFC0000 +CONFIG_ENV_SIZE=0x80 +CONFIG_SYS_MALLOC_LEN=0x2000 +CONFIG_SYS_MEM_RSVD_FOR_MMU=y +CONFIG_COUNTER_FREQUENCY=2720000 +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_IMAGE_FORMAT_LEGACY is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_PROMPT="Versal> " +# CONFIG_AUTOBOOT is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +# CONFIG_PARTITIONS is not set +CONFIG_DEFAULT_DEVICE_TREE="versal-mini" +# CONFIG_NET is not set +# CONFIG_DM_WARN is not set +# CONFIG_DM_DEVICE_REMOVE is not set +# CONFIG_MMC is not set +# CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig new file mode 100644 index 0000000000..d647d6839b --- /dev/null +++ b/configs/xilinx_versal_mini_emmc0_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini" +CONFIG_ARCH_VERSAL=y +CONFIG_SYS_TEXT_BASE=0x10000 +CONFIG_ENV_SIZE=0x80 +CONFIG_SYS_MALLOC_LEN=0x80000 +CONFIG_COUNTER_FREQUENCY=2720000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_PROMPT="Versal> " +# CONFIG_AUTOBOOT is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc0" +# CONFIG_NET is not set +# CONFIG_DM_WARN is not set +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig new file mode 100644 index 0000000000..4a83311235 --- /dev/null +++ b/configs/xilinx_versal_mini_emmc1_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini" +CONFIG_ARCH_VERSAL=y +CONFIG_SYS_TEXT_BASE=0x10000 +CONFIG_ENV_SIZE=0x80 +CONFIG_SYS_MALLOC_LEN=0x80000 +CONFIG_COUNTER_FREQUENCY=2720000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_PROMPT="Versal> " +# CONFIG_AUTOBOOT is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc1" +# CONFIG_NET is not set +# CONFIG_DM_WARN is not set +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 2b226c4004..b0b36a084f 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -56,6 +56,11 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI=y +CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y CONFIG_PHY_GIGE=y CONFIG_MII=y diff --git a/configs/xilinx_zynqmp_zc1275_revB_defconfig b/configs/xilinx_zynqmp_zc1275_revB_defconfig index 7e0f618ed0..aa44f04243 100644 --- a/configs/xilinx_zynqmp_zc1275_revB_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revB_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1275_revB" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index 59db2131c0..bf141c5e16 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -7,6 +6,7 @@ CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_ZYNQMP_USB=y +CONFIG_SPL_ZYNQMP_TWO_SDHCI=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig index d91d511a3a..439f89e50f 100644 --- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm017_dc3" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig index d14d6c4972..f1970aadf4 100644 --- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig index a3c81eb7e9..6e0767164c 100644 --- a/configs/xilinx_zynqmp_zcu100_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu100" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -49,8 +48,10 @@ CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_DM_GPIO=y CONFIG_XILINX_GPIO=y -CONFIG_SYS_I2C_ZYNQ=y -CONFIG_ZYNQ_I2C1=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index ac1710195a..371e6363db 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -23,7 +22,6 @@ CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_CLK=y @@ -60,15 +58,18 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_DM_GPIO=y -CONFIG_CMD_PCA953X=y CONFIG_XILINX_GPIO=y -CONFIG_SYS_I2C_ZYNQ=y -CONFIG_ZYNQ_I2C0=y -CONFIG_ZYNQ_I2C1=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y +CONFIG_I2C_EEPROM=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_SDHCI=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index 604e8c9f71..a0fb6c3586 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -23,7 +22,6 @@ CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_CLK=y @@ -60,15 +58,19 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_DM_GPIO=y -CONFIG_CMD_PCA953X=y CONFIG_XILINX_GPIO=y -CONFIG_SYS_I2C_ZYNQ=y -CONFIG_ZYNQ_I2C0=y -CONFIG_ZYNQ_I2C1=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y +CONFIG_I2C_EEPROM=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index d0155b1d4f..db7c093d5e 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -23,7 +22,6 @@ CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_CLK=y @@ -60,15 +58,19 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_DM_GPIO=y -CONFIG_CMD_PCA953X=y CONFIG_XILINX_GPIO=y -CONFIG_SYS_I2C_ZYNQ=y -CONFIG_ZYNQ_I2C0=y -CONFIG_ZYNQ_I2C1=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y +CONFIG_I2C_EEPROM=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig index 06c3ca3db6..eacf75d9f8 100644 --- a/configs/xilinx_zynqmp_zcu104_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu104" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -19,7 +18,6 @@ CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y CONFIG_SYS_PROMPT="ZynqMP> " -CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y @@ -50,10 +48,14 @@ CONFIG_DFU_RAM=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_DM_GPIO=y -CONFIG_CMD_PCA953X=y -CONFIG_SYS_I2C_ZYNQ=y -CONFIG_ZYNQ_I2C1=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig index d615cb04f4..1c9a6d6f1e 100644 --- a/configs/xilinx_zynqmp_zcu104_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu104_revC" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -19,7 +18,6 @@ CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y CONFIG_SYS_PROMPT="ZynqMP> " -CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y @@ -50,11 +48,15 @@ CONFIG_DFU_RAM=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_DM_GPIO=y -CONFIG_CMD_PCA953X=y -CONFIG_SYS_I2C_ZYNQ=y -CONFIG_ZYNQ_I2C1=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_MISC=y +CONFIG_I2C_EEPROM=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y diff --git a/configs/xilinx_zynqmp_zcu106_revA_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig index 9f5f975008..1b685ca049 100644 --- a/configs/xilinx_zynqmp_zcu106_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu106_revA_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu106" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -22,7 +21,6 @@ CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y @@ -57,14 +55,17 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_DM_GPIO=y -CONFIG_CMD_PCA953X=y -CONFIG_SYS_I2C_ZYNQ=y -CONFIG_ZYNQ_I2C0=y -CONFIG_ZYNQ_I2C1=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y +CONFIG_I2C_EEPROM=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y diff --git a/configs/xilinx_zynqmp_zcu111_revA_defconfig b/configs/xilinx_zynqmp_zcu111_revA_defconfig index 40586771a0..74106d7ea8 100644 --- a/configs/xilinx_zynqmp_zcu111_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu111_revA_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu111" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -19,7 +18,6 @@ CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y CONFIG_SYS_PROMPT="ZynqMP> " -CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y @@ -49,14 +47,17 @@ CONFIG_DFU_RAM=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_DM_GPIO=y -CONFIG_CMD_PCA953X=y -CONFIG_SYS_I2C_ZYNQ=y -CONFIG_ZYNQ_I2C0=y -CONFIG_ZYNQ_I2C1=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y +CONFIG_I2C_EEPROM=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig index 1fd18ac364..5f15d42933 100644 --- a/configs/zynq_cc108_defconfig +++ b/configs/zynq_cc108_defconfig @@ -11,7 +11,6 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_IMAGE_FORMAT_LEGACY=y -CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_dlc20_rev1_0_defconfig b/configs/zynq_dlc20_rev1_0_defconfig index 42b565ce46..c61010f289 100644 --- a/configs/zynq_dlc20_rev1_0_defconfig +++ b/configs/zynq_dlc20_rev1_0_defconfig @@ -12,14 +12,12 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_IMAGE_FORMAT_LEGACY=y -CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_EEPROM=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y @@ -44,8 +42,12 @@ CONFIG_DFU_RAM=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQPL=y CONFIG_DM_GPIO=y -CONFIG_SYS_I2C_ZYNQ=y -CONFIG_ZYNQ_I2C0=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 83996bb773..bbf9fc0ced 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -8,7 +8,6 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_IMAGE_FORMAT_LEGACY=y -CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/zynq_minized_defconfig b/configs/zynq_minized_defconfig index 21f807a2d0..b64f91fb3a 100644 --- a/configs/zynq_minized_defconfig +++ b/configs/zynq_minized_defconfig @@ -10,7 +10,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index 226f0f7f3a..98db04559f 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_SPL=y CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig index f5cbaae0b1..9704b81a3d 100644 --- a/configs/zynq_z_turn_defconfig +++ b/configs/zynq_z_turn_defconfig @@ -11,7 +11,6 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_IMAGE_FORMAT_LEGACY=y -CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 101568de8e..c9eb4d3eeb 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="zynq_zc70x" CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_SPL=y @@ -13,13 +12,11 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_IMAGE_FORMAT_LEGACY=y -CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set @@ -45,10 +42,14 @@ CONFIG_DFU_RAM=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQPL=y CONFIG_DM_GPIO=y -CONFIG_SYS_I2C_ZYNQ=y -CONFIG_ZYNQ_I2C0=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index 313a02a091..9da1d54d98 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="zynq_zc70x" CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_SPL=y @@ -15,14 +14,12 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_PRINT=y CONFIG_SPL_LOAD_FIT=y CONFIG_IMAGE_FORMAT_LEGACY=y -CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_SPL_STACK_R=y CONFIG_SPL_FPGA_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_EEPROM=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y @@ -47,8 +44,12 @@ CONFIG_DFU_RAM=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQPL=y CONFIG_DM_GPIO=y -CONFIG_SYS_I2C_ZYNQ=y -CONFIG_ZYNQ_I2C0=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index 22d5b84766..bfff8afab8 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -12,7 +12,6 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_IMAGE_FORMAT_LEGACY=y -CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig index 70a76e6020..871237f39b 100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@ -13,7 +13,6 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_IMAGE_FORMAT_LEGACY=y -CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_zc770_xm011_x16_defconfig b/configs/zynq_zc770_xm011_x16_defconfig index 2a6ffa595d..0ab7aba2cc 100644 --- a/configs/zynq_zc770_xm011_x16_defconfig +++ b/configs/zynq_zc770_xm011_x16_defconfig @@ -13,7 +13,6 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_IMAGE_FORMAT_LEGACY=y -CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index 8c92505024..3770e267e5 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -10,7 +10,6 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_IMAGE_FORMAT_LEGACY=y -CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index 4f11ddedf8..996f46b223 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -10,7 +10,6 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_IMAGE_FORMAT_LEGACY=y -CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 166c034696..fdaa5bb6c6 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -11,7 +11,6 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_IMAGE_FORMAT_LEGACY=y -CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 6754ff529a..9a4ac2dcc9 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -11,7 +11,6 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_IMAGE_FORMAT_LEGACY=y -CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y @@ -40,7 +39,6 @@ CONFIG_DFU_RAM=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQPL=y CONFIG_DM_GPIO=y -CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig index 6323645aeb..8cabaf131d 100644 --- a/configs/zynq_zybo_z7_defconfig +++ b/configs/zynq_zybo_z7_defconfig @@ -11,7 +11,6 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_IMAGE_FORMAT_LEGACY=y -CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index d83afe4dc6..b6bc678091 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -456,39 +456,6 @@ config SYS_I2C_XILINX_XIIC help Support for Xilinx AXI I2C controller. -config SYS_I2C_ZYNQ - bool "Xilinx I2C driver" - depends on ARCH_ZYNQMP || ARCH_ZYNQ - depends on !DM_I2C - help - Support for Xilinx I2C controller. - -config SYS_I2C_ZYNQ_SLAVE - hex "Set slave addr" - depends on SYS_I2C_ZYNQ - default 0 - help - Set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr. - -config SYS_I2C_ZYNQ_SPEED - int "Set I2C speed" - depends on SYS_I2C_ZYNQ - default 100000 - help - Set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting. - -config ZYNQ_I2C0 - bool "Xilinx I2C0 controller" - depends on SYS_I2C_ZYNQ - help - Enable Xilinx I2C0 controller. - -config ZYNQ_I2C1 - bool "Xilinx I2C1 controller" - depends on SYS_I2C_ZYNQ - help - Enable Xilinx I2C1 controller. - config SYS_I2C_IHS bool "gdsys IHS I2C driver" depends on DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index ec2d1964c3..dc40055efb 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -38,7 +38,6 @@ obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o obj-$(CONFIG_SYS_I2C_VERSATILE) += i2c-versatile.o obj-$(CONFIG_SYS_I2C_XILINX_XIIC) += xilinx_xiic.o -obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o obj-$(CONFIG_I2C_MUX) += muxes/ diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c deleted file mode 100644 index da25067c21..0000000000 --- a/drivers/i2c/zynq_i2c.c +++ /dev/null @@ -1,313 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Driver for the Zynq-7000 PS I2C controller - * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2) - * - * Author: Joe Hershberger <joe.hershberger@ni.com> - * Copyright (c) 2012 Joe Hershberger. - * - * Copyright (c) 2012-2013 Xilinx, Michal Simek - * - * NOTE: This driver should be converted to driver model before June 2017. - * Please see doc/driver-model/i2c-howto.txt for instructions. - */ - -#include <common.h> -#include <asm/io.h> -#include <i2c.h> -#include <linux/errno.h> -#include <asm/arch/hardware.h> - -/* i2c register set */ -struct zynq_i2c_registers { - u32 control; - u32 status; - u32 address; - u32 data; - u32 interrupt_status; - u32 transfer_size; - u32 slave_mon_pause; - u32 time_out; - u32 interrupt_mask; - u32 interrupt_enable; - u32 interrupt_disable; -}; - -/* Control register fields */ -#define ZYNQ_I2C_CONTROL_RW 0x00000001 -#define ZYNQ_I2C_CONTROL_MS 0x00000002 -#define ZYNQ_I2C_CONTROL_NEA 0x00000004 -#define ZYNQ_I2C_CONTROL_ACKEN 0x00000008 -#define ZYNQ_I2C_CONTROL_HOLD 0x00000010 -#define ZYNQ_I2C_CONTROL_SLVMON 0x00000020 -#define ZYNQ_I2C_CONTROL_CLR_FIFO 0x00000040 -#define ZYNQ_I2C_CONTROL_DIV_B_SHIFT 8 -#define ZYNQ_I2C_CONTROL_DIV_B_MASK 0x00003F00 -#define ZYNQ_I2C_CONTROL_DIV_A_SHIFT 14 -#define ZYNQ_I2C_CONTROL_DIV_A_MASK 0x0000C000 - -/* Status register values */ -#define ZYNQ_I2C_STATUS_RXDV 0x00000020 -#define ZYNQ_I2C_STATUS_TXDV 0x00000040 -#define ZYNQ_I2C_STATUS_RXOVF 0x00000080 -#define ZYNQ_I2C_STATUS_BA 0x00000100 - -/* Interrupt register fields */ -#define ZYNQ_I2C_INTERRUPT_COMP 0x00000001 -#define ZYNQ_I2C_INTERRUPT_DATA 0x00000002 -#define ZYNQ_I2C_INTERRUPT_NACK 0x00000004 -#define ZYNQ_I2C_INTERRUPT_TO 0x00000008 -#define ZYNQ_I2C_INTERRUPT_SLVRDY 0x00000010 -#define ZYNQ_I2C_INTERRUPT_RXOVF 0x00000020 -#define ZYNQ_I2C_INTERRUPT_TXOVF 0x00000040 -#define ZYNQ_I2C_INTERRUPT_RXUNF 0x00000080 -#define ZYNQ_I2C_INTERRUPT_ARBLOST 0x00000200 - -#define ZYNQ_I2C_FIFO_DEPTH 16 -#define ZYNQ_I2C_TRANSFERT_SIZE_MAX 255 /* Controller transfer limit */ - -static struct zynq_i2c_registers *i2c_select(struct i2c_adapter *adap) -{ - return adap->hwadapnr ? - /* Zynq PS I2C1 */ - (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR1 : - /* Zynq PS I2C0 */ - (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR0; -} - -/* I2C init called by cmd_i2c when doing 'i2c reset'. */ -static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed, - int slaveadd) -{ - struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); - - /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */ - writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) | - (2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control); - - /* Enable master mode, ack, and 7-bit addressing */ - setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_MS | - ZYNQ_I2C_CONTROL_ACKEN | ZYNQ_I2C_CONTROL_NEA); -} - -#ifdef DEBUG -static void zynq_i2c_debug_status(struct zynq_i2c_registers *zynq_i2c) -{ - int int_status; - int status; - int_status = readl(&zynq_i2c->interrupt_status); - - status = readl(&zynq_i2c->status); - if (int_status || status) { - debug("Status: "); - if (int_status & ZYNQ_I2C_INTERRUPT_COMP) - debug("COMP "); - if (int_status & ZYNQ_I2C_INTERRUPT_DATA) - debug("DATA "); - if (int_status & ZYNQ_I2C_INTERRUPT_NACK) - debug("NACK "); - if (int_status & ZYNQ_I2C_INTERRUPT_TO) - debug("TO "); - if (int_status & ZYNQ_I2C_INTERRUPT_SLVRDY) - debug("SLVRDY "); - if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF) - debug("RXOVF "); - if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF) - debug("TXOVF "); - if (int_status & ZYNQ_I2C_INTERRUPT_RXUNF) - debug("RXUNF "); - if (int_status & ZYNQ_I2C_INTERRUPT_ARBLOST) - debug("ARBLOST "); - if (status & ZYNQ_I2C_STATUS_RXDV) - debug("RXDV "); - if (status & ZYNQ_I2C_STATUS_TXDV) - debug("TXDV "); - if (status & ZYNQ_I2C_STATUS_RXOVF) - debug("RXOVF "); - if (status & ZYNQ_I2C_STATUS_BA) - debug("BA "); - debug("TS%d ", readl(&zynq_i2c->transfer_size)); - debug("\n"); - } -} -#endif - -/* Wait for an interrupt */ -static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask) -{ - int timeout, int_status; - - for (timeout = 0; timeout < 100; timeout++) { - udelay(100); - int_status = readl(&zynq_i2c->interrupt_status); - if (int_status & mask) - break; - } -#ifdef DEBUG - zynq_i2c_debug_status(zynq_i2c); -#endif - /* Clear interrupt status flags */ - writel(int_status & mask, &zynq_i2c->interrupt_status); - - return int_status & mask; -} - -/* - * I2C probe called by cmd_i2c when doing 'i2c probe'. - * Begin read, nak data byte, end. - */ -static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev) -{ - struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); - - /* Attempt to read a byte */ - setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | - ZYNQ_I2C_CONTROL_RW); - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); - writel(0xFF, &zynq_i2c->interrupt_status); - writel(dev, &zynq_i2c->address); - writel(1, &zynq_i2c->transfer_size); - - return (zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP | - ZYNQ_I2C_INTERRUPT_NACK) & - ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT; -} - -/* - * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c - * Begin write, send address byte(s), begin read, receive data bytes, end. - */ -static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, - int alen, u8 *data, int length) -{ - u32 status; - u32 i = 0; - u8 *cur_data = data; - struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); - - /* Check the hardware can handle the requested bytes */ - if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX)) - return -EINVAL; - - /* Write the register address */ - setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | - ZYNQ_I2C_CONTROL_HOLD); - /* - * Temporarily disable restart (by clearing hold) - * It doesn't seem to work. - */ - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); - writel(0xFF, &zynq_i2c->interrupt_status); - if (alen) { - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW); - writel(dev, &zynq_i2c->address); - while (alen--) - writel(addr >> (8 * alen), &zynq_i2c->data); - - /* Wait for the address to be sent */ - if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) { - /* Release the bus */ - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); - return -ETIMEDOUT; - } - debug("Device acked address\n"); - } - - setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | - ZYNQ_I2C_CONTROL_RW); - /* Start reading data */ - writel(dev, &zynq_i2c->address); - writel(length, &zynq_i2c->transfer_size); - - /* Wait for data */ - do { - status = zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP | - ZYNQ_I2C_INTERRUPT_DATA); - if (!status) { - /* Release the bus */ - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); - return -ETIMEDOUT; - } - debug("Read %d bytes\n", - length - readl(&zynq_i2c->transfer_size)); - for (; i < length - readl(&zynq_i2c->transfer_size); i++) - *(cur_data++) = readl(&zynq_i2c->data); - } while (readl(&zynq_i2c->transfer_size) != 0); - /* All done... release the bus */ - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); - -#ifdef DEBUG - zynq_i2c_debug_status(zynq_i2c); -#endif - return 0; -} - -/* - * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c - * Begin write, send address byte(s), send data bytes, end. - */ -static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, - int alen, u8 *data, int length) -{ - u8 *cur_data = data; - struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); - - /* Write the register address */ - setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | - ZYNQ_I2C_CONTROL_HOLD); - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW); - writel(0xFF, &zynq_i2c->interrupt_status); - writel(dev, &zynq_i2c->address); - if (alen) { - while (alen--) - writel(addr >> (8 * alen), &zynq_i2c->data); - /* Start the tranfer */ - if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) { - /* Release the bus */ - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); - return -ETIMEDOUT; - } - debug("Device acked address\n"); - } - - while (length--) { - writel(*(cur_data++), &zynq_i2c->data); - if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) { - if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) { - /* Release the bus */ - clrbits_le32(&zynq_i2c->control, - ZYNQ_I2C_CONTROL_HOLD); - return -ETIMEDOUT; - } - } - } - - /* All done... release the bus */ - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); - /* Wait for the address and data to be sent */ - if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) - return -ETIMEDOUT; - return 0; -} - -static unsigned int zynq_i2c_set_bus_speed(struct i2c_adapter *adap, - unsigned int speed) -{ - if (speed != 1000000) - return -EINVAL; - - return 0; -} - -#ifdef CONFIG_ZYNQ_I2C0 -U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read, - zynq_i2c_write, zynq_i2c_set_bus_speed, - CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE, - 0) -#endif -#ifdef CONFIG_ZYNQ_I2C1 -U_BOOT_I2C_ADAP_COMPLETE(zynq_1, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read, - zynq_i2c_write, zynq_i2c_set_bus_speed, - CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE, - 1) -#endif diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 704c8dd195..d6e677fba8 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -245,6 +245,7 @@ config SPL_I2C_EEPROM config ZYNQ_GEM_I2C_MAC_OFFSET hex "Set the I2C MAC offset" default 0x0 + depends on DM_I2C help Set the MAC offset for i2C. diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 75459d156e..da9413c066 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -714,6 +714,7 @@ static const struct dm_spi_ops zynqmp_qspi_ops = { static const struct udevice_id zynqmp_qspi_ids[] = { { .compatible = "xlnx,zynqmp-qspi-1.0" }, + { .compatible = "xlnx,versal-qspi-1.0" }, { } }; diff --git a/include/configs/syzygy_hub.h b/include/configs/syzygy_hub.h index 88ee772848..e31b77c0c0 100644 --- a/include/configs/syzygy_hub.h +++ b/include/configs/syzygy_hub.h @@ -10,9 +10,6 @@ #ifndef __CONFIG_SYZYGY_HUB_H #define __CONFIG_SYZYGY_HUB_H -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x57 - #define CONFIG_EXTRA_ENV_SETTINGS \ "fit_image=fit.itb\0" \ "bitstream_image=download.bit\0" \ diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index bfe4c43449..2cc36e793b 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -73,9 +73,33 @@ "pxefile_addr_r=0x10000000\0" \ "kernel_addr_r=0x18000000\0" \ "scriptaddr=0x02000000\0" \ - "ramdisk_addr_r=0x02100000\0" + "ramdisk_addr_r=0x02100000\0" \ + "script_offset_f=0x3f80000\0" \ + "script_size_f=0x80000\0" + +#if defined(CONFIG_MMC_SDHCI_ZYNQ) +# define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) +#else +# define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#if defined(CONFIG_ZYNQMP_GQSPI) || defined(CONFIG_CADENCE_OSPI_VERSAL) +# define BOOT_TARGET_DEVICES_XSPI(func) func(XSPI, xspi, 0) +#else +# define BOOT_TARGET_DEVICES_XSPI(func) +#endif + +#define BOOTENV_DEV_XSPI(devtypeu, devtypel, instance) \ + "bootcmd_xspi0=sf probe 0 0 0 && " \ + "sf read $scriptaddr $script_offset_f $script_size_f && " \ + "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \ + "xspi " #define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_XSPI(func) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h new file mode 100644 index 0000000000..c15fb5fc3b --- /dev/null +++ b/include/configs/xilinx_versal_mini.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for Xilinx Versal MINI configuration + * + * (C) Copyright 2018-2019 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> + */ + +#ifndef __CONFIG_VERSAL_MINI_H +#define __CONFIG_VERSAL_MINI_H + +/* #define CONFIG_SYS_DCACHE_OFF */ +#define CONFIG_SYS_ICACHE_OFF + +#define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000 + +#define CONFIG_EXTRA_ENV_SETTINGS + +#include <configs/xilinx_versal.h> + +/* Undef unneeded configs */ +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_ZLIB +#undef CONFIG_GZIP +#undef CONFIG_CMD_ENV +#undef CONFIG_BOOTM_NETBSD +#undef CONFIG_BOOTM_VXWORKS +#undef CONFIG_BOOTM_LINUX + +/* BOOTP options */ +#undef CONFIG_BOOTP_BOOTFILESIZE +#undef CONFIG_BOOTP_MAY_FAIL + +#endif /* __CONFIG_VERSAL_MINI_H */ diff --git a/include/configs/xilinx_versal_mini_qspi.h b/include/configs/xilinx_versal_mini_qspi.h new file mode 100644 index 0000000000..8572b8b3d2 --- /dev/null +++ b/include/configs/xilinx_versal_mini_qspi.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for Xilinx Versal QSPI Flash utility + * + * (C) Copyright 2018-2019 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * Siva Durga Prasad Paladugu <sivadur@xilinx.com> + */ + +#ifndef __CONFIG_VERSAL_MINI_QSPI_H +#define __CONFIG_VERSAL_MINI_QSPI_H + +#include <configs/xilinx_versal_mini.h> + +#undef CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000) + +#endif /* __CONFIG_VERSAL_MINI_QSPI_H */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 7a9b06ec4c..27a8e4d490 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -108,11 +108,6 @@ # define PHY_ANEG_TIMEOUT 20000 #endif -/* I2C */ -#if defined(CONFIG_SYS_I2C_ZYNQ) -# define CONFIG_SYS_I2C -#endif - /* EEPROM */ #ifdef CONFIG_ZYNQMP_EEPROM # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 @@ -134,6 +129,8 @@ "kernel_addr_r=0x18000000\0" \ "scriptaddr=0x02000000\0" \ "ramdisk_addr_r=0x02100000\0" \ + "script_offset_f=0x3e80000\0" \ + "script_size_f=0x80000\0" \ #if defined(CONFIG_MMC_SDHCI_ZYNQ) # define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) @@ -165,8 +162,38 @@ # define BOOT_TARGET_DEVICES_DHCP(func) #endif +#if defined(CONFIG_ZYNQMP_GQSPI) +# define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, 0) +#else +# define BOOT_TARGET_DEVICES_QSPI(func) +#endif + +#if defined(CONFIG_NAND_ARASAN) +# define BOOT_TARGET_DEVICES_NAND(func) func(NAND, nand, 0) +#else +# define BOOT_TARGET_DEVICES_NAND(func) +#endif + +#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=sf probe " #instance " 0 0 && " \ + "sf read $scriptaddr $script_offset_f $script_size_f && " \ + "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "= nand info && " \ + "nand read $scriptaddr $script_offset_f $script_size_f && " \ + "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ + #devtypel #instance " " + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_QSPI(func) \ + BOOT_TARGET_DEVICES_NAND(func) \ BOOT_TARGET_DEVICES_USB(func) \ BOOT_TARGET_DEVICES_SCSI(func) \ BOOT_TARGET_DEVICES_PXE(func) \ diff --git a/include/configs/xilinx_zynqmp_zc1275_revB.h b/include/configs/xilinx_zynqmp_zc1275_revB.h deleted file mode 100644 index f0880db0b0..0000000000 --- a/include/configs/xilinx_zynqmp_zc1275_revB.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Xilinx ZynqMP zc1275 RevB - * - * (C) Copyright 2018 Xilinx, Inc. - */ - -#ifndef __CONFIG_ZYNQMP_ZC1275_REVB_H -#define __CONFIG_ZYNQMP_ZC1275_REVB_H - -#define CONFIG_ZYNQ_SDHCI1 - -#include <configs/xilinx_zynqmp.h> - -#endif /* __CONFIG_ZYNQMP_ZC1275_REVB_H */ diff --git a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h deleted file mode 100644 index f0ab3f1592..0000000000 --- a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Xilinx ZynqMP zc1751 XM015 DC1 - * - * (C) Copyright 2015 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> - */ - -#ifndef __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H -#define __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H - -#define CONFIG_ZYNQ_SDHCI0 -#define CONFIG_ZYNQ_SDHCI1 - -#include <configs/xilinx_zynqmp.h> - -#endif /* __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H */ diff --git a/include/configs/xilinx_zynqmp_zc1751_xm017_dc3.h b/include/configs/xilinx_zynqmp_zc1751_xm017_dc3.h deleted file mode 100644 index bd4a0c3178..0000000000 --- a/include/configs/xilinx_zynqmp_zc1751_xm017_dc3.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Xilinx ZynqMP zc1751 XM017 DC3 - * - * (C) Copyright 2015 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> - */ - -#ifndef __CONFIG_ZYNQMP_ZC1751_XM017_DC3_H -#define __CONFIG_ZYNQMP_ZC1751_XM017_DC3_H - -#define CONFIG_ZYNQ_SDHCI1 - -#include <configs/xilinx_zynqmp.h> - -#endif /* __CONFIG_ZYNQMP_ZC1751_XM017_DC3_H */ diff --git a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h deleted file mode 100644 index f39eeb9bfc..0000000000 --- a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Xilinx ZynqMP zc1751 XM019 DC5 - * - * (C) Copyright 2015 Xilinx, Inc. - * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> - * Michal Simek <michal.simek@xilinx.com> - */ - -#ifndef __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H -#define __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H - -#define CONFIG_ZYNQ_SDHCI0 - -#include <configs/xilinx_zynqmp.h> - -#endif /* __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H */ diff --git a/include/configs/xilinx_zynqmp_zcu100.h b/include/configs/xilinx_zynqmp_zcu100.h deleted file mode 100644 index 5ad9e1be5a..0000000000 --- a/include/configs/xilinx_zynqmp_zcu100.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Xilinx ZynqMP zcu100 - * - * (C) Copyright 2015 - 2016 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> - */ - -#ifndef __CONFIG_ZYNQMP_ZCU100_H -#define __CONFIG_ZYNQMP_ZCU100_H - -/* FIXME Will go away soon */ -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_NUM_I2C_BUSES 9 -#define CONFIG_SYS_I2C_BUSES { \ - {0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9548, 0x75, 0} } }, \ - {0, {{I2C_MUX_PCA9548, 0x75, 1} } }, \ - {0, {{I2C_MUX_PCA9548, 0x75, 2} } }, \ - {0, {{I2C_MUX_PCA9548, 0x75, 3} } }, \ - {0, {{I2C_MUX_PCA9548, 0x75, 4} } }, \ - {0, {{I2C_MUX_PCA9548, 0x75, 5} } }, \ - {0, {{I2C_MUX_PCA9548, 0x75, 6} } }, \ - {0, {{I2C_MUX_PCA9548, 0x75, 7} } }, \ - } - -#include <configs/xilinx_zynqmp.h> - -#endif /* __CONFIG_ZYNQMP_ZCU100_H */ diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h deleted file mode 100644 index ad6bc3d1bf..0000000000 --- a/include/configs/xilinx_zynqmp_zcu102.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Xilinx ZynqMP zcu102 - * - * (C) Copyright 2015 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> - */ - -#ifndef __CONFIG_ZYNQMP_ZCU102_H -#define __CONFIG_ZYNQMP_ZCU102_H - -#define CONFIG_ZYNQ_SDHCI1 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_NUM_I2C_BUSES 18 -#define CONFIG_SYS_I2C_BUSES { \ - {0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \ - {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \ - {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \ - {1, {I2C_NULL_HOP} }, \ - {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \ - {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \ - {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \ - {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \ - {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \ - } - -#define CONFIG_PCA953X - -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_ZYNQ_EEPROM_BUS 5 -#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54 - -#define CONFIG_SPD_EEPROM -#define CONFIG_DDR_SPD - -#include <configs/xilinx_zynqmp.h> - -#endif /* __CONFIG_ZYNQMP_ZCU102_H */ diff --git a/include/configs/xilinx_zynqmp_zcu104.h b/include/configs/xilinx_zynqmp_zcu104.h deleted file mode 100644 index 7e3b9ad705..0000000000 --- a/include/configs/xilinx_zynqmp_zcu104.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Xilinx ZynqMP zcu104 - * - * (C) Copyright 2017 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> - */ - -#ifndef __CONFIG_ZYNQMP_ZCU104_H -#define __CONFIG_ZYNQMP_ZCU104_H - -#define CONFIG_ZYNQ_SDHCI1 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_NUM_I2C_BUSES 9 -#define CONFIG_SYS_I2C_BUSES { \ - {0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9548, 0x74, 0} } }, \ - {0, {{I2C_MUX_PCA9548, 0x74, 1} } }, \ - {0, {{I2C_MUX_PCA9548, 0x74, 2} } }, \ - {0, {{I2C_MUX_PCA9548, 0x74, 3} } }, \ - {0, {{I2C_MUX_PCA9548, 0x74, 4} } }, \ - {0, {{I2C_MUX_PCA9548, 0x74, 5} } }, \ - {0, {{I2C_MUX_PCA9548, 0x74, 6} } }, \ - {0, {{I2C_MUX_PCA9548, 0x74, 7} } }, \ - } - -#define CONFIG_PCA953X - -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -#include <configs/xilinx_zynqmp.h> - -#endif /* __CONFIG_ZYNQMP_ZCU104_H */ diff --git a/include/configs/xilinx_zynqmp_zcu104_revC.h b/include/configs/xilinx_zynqmp_zcu104_revC.h deleted file mode 100644 index 8b3ae36d0f..0000000000 --- a/include/configs/xilinx_zynqmp_zcu104_revC.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Xilinx ZynqMP zcu104 - * - * (C) Copyright 2018 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> - */ - -#ifndef __CONFIG_ZYNQMP_ZCU104_REVC_H -#define __CONFIG_ZYNQMP_ZCU104_REVC_H - -#include <configs/xilinx_zynqmp_zcu104.h> - -#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54 -#define CONFIG_ZYNQ_EEPROM_BUS 1 - -#endif /* __CONFIG_ZYNQMP_ZCU104_REVC_H */ diff --git a/include/configs/xilinx_zynqmp_zcu106.h b/include/configs/xilinx_zynqmp_zcu106.h deleted file mode 100644 index cc2d145ddd..0000000000 --- a/include/configs/xilinx_zynqmp_zcu106.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Xilinx ZynqMP zcu106 - * - * (C) Copyright 2016 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> - */ - -#ifndef __CONFIG_ZYNQMP_ZCU106_H -#define __CONFIG_ZYNQMP_ZCU106_H - -#define CONFIG_ZYNQ_SDHCI1 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_NUM_I2C_BUSES 18 -#define CONFIG_SYS_I2C_BUSES { \ - {0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \ - {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \ - {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \ - {1, {I2C_NULL_HOP} }, \ - {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \ - {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \ - {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \ - {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \ - {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \ - } - -#define CONFIG_PCA953X - -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_ZYNQ_EEPROM_BUS 5 -#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54 - -#include <configs/xilinx_zynqmp.h> - -#endif /* __CONFIG_ZYNQMP_ZCU106_H */ diff --git a/include/configs/xilinx_zynqmp_zcu111.h b/include/configs/xilinx_zynqmp_zcu111.h deleted file mode 100644 index 8f8cb4f087..0000000000 --- a/include/configs/xilinx_zynqmp_zcu111.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Xilinx ZynqMP zcu111 - * - * (C) Copyright 2017 Xilinx, Inc. - * Michal Simek <michal.simek@xilinx.com> - */ - -#ifndef __CONFIG_ZYNQMP_ZCU111_H -#define __CONFIG_ZYNQMP_ZCU111_H - -#define CONFIG_ZYNQ_SDHCI1 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_NUM_I2C_BUSES 21 -#define CONFIG_SYS_I2C_BUSES { \ - {0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \ - {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \ - {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \ - {0, {{I2C_MUX_PCA9544, 0x75, 3} } }, \ - {1, {I2C_NULL_HOP} }, \ - {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \ - {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \ - {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \ - {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \ - {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \ - {1, {{I2C_MUX_PCA9548, 0x74, 5} } }, \ - {1, {{I2C_MUX_PCA9548, 0x74, 6} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \ - {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \ - } - -#define CONFIG_PCA953X - -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_ZYNQ_EEPROM_BUS 5 -#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54 - -#include <configs/xilinx_zynqmp.h> - -#endif /* __CONFIG_ZYNQMP_ZCU111_H */ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 1710feda91..a285fcdece 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -102,20 +102,6 @@ # define DFU_ALT_INFO #endif -/* I2C */ -#if defined(CONFIG_SYS_I2C_ZYNQ) -# define CONFIG_SYS_I2C -#endif - -/* EEPROM */ -#ifdef CONFIG_ZYNQ_EEPROM -# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -# define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 -# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -# define CONFIG_SYS_EEPROM_SIZE 1024 /* Bytes */ -#endif - /* Allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -153,11 +139,62 @@ #define BOOT_TARGET_DEVICES_DHCP(func) #endif +#if defined(CONFIG_ZYNQ_QSPI) +# define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na) +#else +# define BOOT_TARGET_DEVICES_QSPI(func) +#endif + +#if defined(CONFIG_NAND_ZYNQ) +# define BOOT_TARGET_DEVICES_NAND(func) func(NAND, nand, na) +#else +# define BOOT_TARGET_DEVICES_NAND(func) +#endif + +#if defined(CONFIG_MTD_NOR_FLASH) +# define BOOT_TARGET_DEVICES_NOR(func) func(NOR, nor, na) +#else +# define BOOT_TARGET_DEVICES_NOR(func) +#endif + +#define BOOTENV_DEV_XILINX(devtypeu, devtypel, instance) \ + "bootcmd_xilinx=run $modeboot\0" + +#define BOOTENV_DEV_NAME_XILINX(devtypeu, devtypel, instance) \ + "xilinx " + +#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ + "bootcmd_qspi=sf probe 0 0 0 && " \ + "sf read $scriptaddr $script_offset_f $script_size_f && " \ + "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ + "qspi " + +#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ + "bootcmd_nand=nand info && " \ + "nand read $scriptaddr $script_offset_f $script_size_f && " \ + "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ + "nand " + +#define BOOTENV_DEV_NOR(devtypeu, devtypel, instance) \ + "bootcmd_nor=cp.b $scropt_offset_nor $scriptaddr $script_size_f && " \ + "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_NOR(devtypeu, devtypel, instance) \ + "nor " + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_QSPI(func) \ + BOOT_TARGET_DEVICES_NAND(func) \ + BOOT_TARGET_DEVICES_NOR(func) \ BOOT_TARGET_DEVICES_USB(func) \ BOOT_TARGET_DEVICES_PXE(func) \ - BOOT_TARGET_DEVICES_DHCP(func) + BOOT_TARGET_DEVICES_DHCP(func) \ + func(XILINX, xilinx, na) #include <config_distro_bootcmd.h> #endif /* CONFIG_SPL_BUILD */ @@ -172,6 +209,10 @@ "nor_flash_off=0xE2100000\0" \ "fdt_high=0x20000000\0" \ "initrd_high=0x20000000\0" \ + "scriptaddr=0x20000\0" \ + "script_offser_nor=0xE2FC0000\0" \ + "script_offset_f=0xFC0000\0" \ + "script_size_f=0x40000\0" \ "loadbootenv_addr=0x2000000\0" \ "fdt_addr_r=0x1f00000\0" \ "pxefile_addr_r=0x2000000\0" \ diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h deleted file mode 100644 index b5a28dab87..0000000000 --- a/include/configs/zynq_zc70x.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Xilinx, Inc. - * - * Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards - * See zynq-common.h for Zynq common configs - */ - -#ifndef __CONFIG_ZYNQ_ZC70X_H -#define __CONFIG_ZYNQ_ZC70X_H - -#define CONFIG_ZYNQ_EEPROM - -#include <configs/zynq-common.h> - -#endif /* __CONFIG_ZYNQ_ZC70X_H */ |