1 files changed, 1 insertions, 37 deletions

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 71c0cc8f2e..c8e9bc86e5 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -242,46 +242,10 @@ static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
 	       __udelay(130);
 }
 
-static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
-{
-	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
-	u32 fifo_reg;
-
-	fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_1);
-	writel(fifo_reg | 0x00000100,
-	       &emif->emif_ddr_fifo_misaligned_clear_1);
-
-	fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_2);
-	writel(fifo_reg | 0x00000100,
-	       &emif->emif_ddr_fifo_misaligned_clear_2);
-
-	/* Launch Full leveling */
-	writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
-
-	/* Wait till full leveling is complete */
-	readl(&emif->emif_rd_wr_lvl_ctl);
-	      __udelay(130);
-
-	/* Read data eye leveling no of samples */
-	config_data_eye_leveling_samples(base);
-
-	/*
-	 * Disable leveling. This is because if leveling is kept
-	 * enabled, then PHY triggers a false leveling during
-	 * EMIF-idle scenario which results in wrong delay
-	 * values getting updated. After this the EMIF becomes
-	 * unaccessible. So disable it after the first time
-	 */
-	writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
-}
-
 static void ddr3_leveling(u32 base, const struct emif_regs *regs)
 {
 	if (is_omap54xx())
 		omap5_ddr3_leveling(base, regs);
-	else
-		dra7_ddr3_leveling(base, regs);
 }
 
 static void ddr3_init(u32 base, const struct emif_regs *regs)
@@ -1383,7 +1347,7 @@ void sdram_init(void)
 	}
 
 	if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
-	    (!in_sdram && !warm_reset())) {
+	    (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
 		if (emif1_enabled)
 			do_bug0039_workaround(EMIF1_BASE);
 		if (emif2_enabled)