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-rw-r--r--arch/arm/cpu/armv7/keystone/clock-k2e.c16
-rw-r--r--arch/arm/cpu/armv7/keystone/clock-k2hk.c32
-rw-r--r--arch/arm/cpu/armv7/keystone/clock.c43
-rw-r--r--arch/arm/cpu/armv7/omap-common/emif-common.c38
-rw-r--r--arch/arm/cpu/armv7/omap-common/hwinit-common.c3
-rw-r--r--arch/arm/cpu/armv7/omap5/hw_data.c2
-rw-r--r--arch/arm/cpu/armv7/omap5/sdram.c60
-rw-r--r--arch/arm/include/asm/arch-keystone/clock-k2e.h16
-rw-r--r--arch/arm/include/asm/arch-keystone/clock-k2hk.h14
-rw-r--r--arch/arm/include/asm/arch-keystone/clock.h4
-rw-r--r--arch/arm/include/asm/arch-keystone/hardware.h4
-rw-r--r--arch/arm/include/asm/arch-omap5/mem.h12
12 files changed, 170 insertions, 74 deletions
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c b/arch/arm/cpu/armv7/keystone/clock-k2e.c
index 42092e1060..31f66613ef 100644
--- a/arch/arm/cpu/armv7/keystone/clock-k2e.c
+++ b/arch/arm/cpu/armv7/keystone/clock-k2e.c
@@ -17,6 +17,22 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
};
+int dev_speeds[] = {
+ SPD800,
+ SPD850,
+ SPD1000,
+ SPD1250,
+ SPD1350,
+ SPD1400,
+ SPD1500,
+ SPD1400,
+ SPD1350,
+ SPD1250,
+ SPD1000,
+ SPD850,
+ SPD800
+};
+
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2hk.c b/arch/arm/cpu/armv7/keystone/clock-k2hk.c
index 96a9f72886..1591960795 100644
--- a/arch/arm/cpu/armv7/keystone/clock-k2hk.c
+++ b/arch/arm/cpu/armv7/keystone/clock-k2hk.c
@@ -19,6 +19,38 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
[DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
};
+int dev_speeds[] = {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD800,
+ SPD1200,
+ SPD1000,
+ SPD800,
+ SPD800,
+ SPD800,
+};
+
+int arm_speeds[] = {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD1350,
+ SPD1400,
+ SPD800,
+ SPD1400,
+ SPD1350,
+ SPD1200,
+ SPD1000,
+ SPD800,
+ SPD800,
+ SPD800,
+};
+
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD
diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c
index 03c1d9f660..30d76a6603 100644
--- a/arch/arm/cpu/armv7/keystone/clock.c
+++ b/arch/arm/cpu/armv7/keystone/clock.c
@@ -11,6 +11,8 @@
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
+#define MAX_SPEEDS 13
+
static void wait_for_completion(const struct pll_init_data *data)
{
int i;
@@ -218,3 +220,44 @@ void init_plls(int num_pll, struct pll_init_data *config)
for (i = 0; i < num_pll; i++)
init_pll(&config[i]);
}
+
+static int get_max_speed(u32 val, int *speeds)
+{
+ int j;
+
+ if (!val)
+ return speeds[0];
+
+ for (j = 1; j < MAX_SPEEDS; j++) {
+ if (val == 1)
+ return speeds[j];
+ val >>= 1;
+ }
+
+ return SPD800;
+}
+
+#ifdef CONFIG_SOC_K2HK
+static u32 read_efuse_bootrom(void)
+{
+ return (cpu_revision() > 1) ? __raw_readl(KS2_EFUSE_BOOTROM) :
+ __raw_readl(KS2_REV1_DEVSPEED);
+}
+#else
+static inline u32 read_efuse_bootrom(void)
+{
+ return __raw_readl(KS2_EFUSE_BOOTROM);
+}
+#endif
+
+inline int get_max_dev_speed(void)
+{
+ return get_max_speed(read_efuse_bootrom() & 0xffff, dev_speeds);
+}
+
+#ifndef CONFIG_SOC_K2E
+inline int get_max_arm_speed(void)
+{
+ return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
+}
+#endif
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 71c0cc8f2e..c8e9bc86e5 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -242,46 +242,10 @@ static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
__udelay(130);
}
-static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- u32 fifo_reg;
-
- fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_1);
- writel(fifo_reg | 0x00000100,
- &emif->emif_ddr_fifo_misaligned_clear_1);
-
- fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_2);
- writel(fifo_reg | 0x00000100,
- &emif->emif_ddr_fifo_misaligned_clear_2);
-
- /* Launch Full leveling */
- writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
-
- /* Wait till full leveling is complete */
- readl(&emif->emif_rd_wr_lvl_ctl);
- __udelay(130);
-
- /* Read data eye leveling no of samples */
- config_data_eye_leveling_samples(base);
-
- /*
- * Disable leveling. This is because if leveling is kept
- * enabled, then PHY triggers a false leveling during
- * EMIF-idle scenario which results in wrong delay
- * values getting updated. After this the EMIF becomes
- * unaccessible. So disable it after the first time
- */
- writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
-}
-
static void ddr3_leveling(u32 base, const struct emif_regs *regs)
{
if (is_omap54xx())
omap5_ddr3_leveling(base, regs);
- else
- dra7_ddr3_leveling(base, regs);
}
static void ddr3_init(u32 base, const struct emif_regs *regs)
@@ -1383,7 +1347,7 @@ void sdram_init(void)
}
if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
- (!in_sdram && !warm_reset())) {
+ (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
if (emif1_enabled)
do_bug0039_workaround(EMIF1_BASE);
if (emif2_enabled)
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 1b4477f469..dd52e938a9 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -140,6 +140,9 @@ void s_init(void)
#endif
prcm_init();
#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+ board_early_init_f();
+#endif
/* For regular u-boot sdram_init() is called from dram_init() */
sdram_init();
#endif
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 4baca11d7a..ed89f85458 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -556,7 +556,7 @@ const struct ctrl_ioregs ioregs_dra7xx_es1 = {
.ctrl_ddrio_1 = 0x84210840,
.ctrl_ddrio_2 = 0x84210000,
.ctrl_emif_sdram_config_ext = 0x0001C1A7,
- .ctrl_emif_sdram_config_ext_final = 0x000101A7,
+ .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
};
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index e2ebab8262..9105121ff6 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -145,18 +145,18 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
- .read_idle_ctrl = 0x00050000,
+ .read_idle_ctrl = 0x00050001,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400A,
- .emif_ddr_phy_ctlr_1 = 0x0024400A,
+ .emif_ddr_phy_ctlr_1_init = 0x0E24400A,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00B000B0,
- .emif_ddr_ext_phy_ctrl_3 = 0x00B000B0,
- .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
- .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
+ .emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
+ .emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
@@ -169,18 +169,18 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
- .read_idle_ctrl = 0x00050000,
+ .read_idle_ctrl = 0x00050001,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400A,
- .emif_ddr_phy_ctlr_1 = 0x0024400A,
+ .emif_ddr_phy_ctlr_1_init = 0x0E24400A,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00B000B0,
- .emif_ddr_ext_phy_ctrl_3 = 0x00B000B0,
- .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
- .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
+ .emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
+ .emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
@@ -394,24 +394,24 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
- 0x00B000B0,
- 0x00400040,
- 0x00400040,
- 0x00400040,
- 0x00400040,
- 0x00400040,
- 0x00800080,
- 0x00800080,
- 0x00800080,
- 0x00800080,
- 0x00800080,
+ 0x00BB00BB,
+ 0x00440044,
+ 0x00440044,
+ 0x00440044,
+ 0x00440044,
+ 0x00440044,
+ 0x007F007F,
+ 0x007F007F,
+ 0x007F007F,
+ 0x007F007F,
+ 0x007F007F,
0x00600060,
0x00600060,
0x00600060,
0x00600060,
0x00600060,
- 0x00800080,
- 0x00800080,
+ 0x00000000,
+ 0x00600020,
0x40010080,
0x08102040,
0x0,
@@ -439,7 +439,7 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
0x00600060,
0x00600060,
0x00600060,
- 0x0,
+ 0x00000000,
0x00600020,
0x40010080,
0x08102040,
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h b/arch/arm/include/asm/arch-keystone/clock-k2e.h
index 41478110e5..df33a78a10 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2e.h
+++ b/arch/arm/include/asm/arch-keystone/clock-k2e.h
@@ -56,10 +56,26 @@ enum pll_type_e {
DDR3_PLL,
};
+enum {
+ SPD800,
+ SPD850,
+ SPD1000,
+ SPD1250,
+ SPD1350,
+ SPD1400,
+ SPD1500,
+ SPD_RSV
+};
+
#define CORE_PLL_800 {CORE_PLL, 16, 1, 2}
+#define CORE_PLL_850 {CORE_PLL, 17, 1, 2}
#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2}
#define CORE_PLL_1200 {CORE_PLL, 24, 1, 2}
#define PASS_PLL_1000 {PASS_PLL, 20, 1, 2}
+#define CORE_PLL_1250 {CORE_PLL, 25, 1, 2}
+#define CORE_PLL_1350 {CORE_PLL, 27, 1, 2}
+#define CORE_PLL_1400 {CORE_PLL, 28, 1, 2}
+#define CORE_PLL_1500 {CORE_PLL, 30, 1, 2}
#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
index 784a0be567..bdb869bed4 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
@@ -63,21 +63,35 @@ enum pll_type_e {
DDR3B_PLL,
};
+enum {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD1350,
+ SPD1400,
+ SPD_RSV
+};
+
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
+#define CORE_PLL_999 {CORE_PLL, 122, 15, 1}
#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
+#define CORE_PLL_1200 {CORE_PLL, 625, 32, 2}
#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
#define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2}
#define TETRIS_PLL_500 {TETRIS_PLL, 8, 1, 2}
#define TETRIS_PLL_750 {TETRIS_PLL, 12, 1, 2}
+#define TETRIS_PLL_800 {TETRIS_PLL, 32, 5, 1}
#define TETRIS_PLL_687 {TETRIS_PLL, 11, 1, 2}
#define TETRIS_PLL_625 {TETRIS_PLL, 10, 1, 2}
#define TETRIS_PLL_812 {TETRIS_PLL, 13, 1, 2}
#define TETRIS_PLL_875 {TETRIS_PLL, 14, 1, 2}
+#define TETRIS_PLL_1000 {TETRIS_PLL, 40, 5, 1}
#define TETRIS_PLL_1188 {TETRIS_PLL, 19, 2, 1}
#define TETRIS_PLL_1200 {TETRIS_PLL, 48, 5, 1}
+#define TETRIS_PLL_1350 {TETRIS_PLL, 54, 5, 1}
#define TETRIS_PLL_1375 {TETRIS_PLL, 22, 2, 1}
#define TETRIS_PLL_1400 {TETRIS_PLL, 56, 5, 1}
#define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2}
diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h
index 1513c76b6a..dae000e43a 100644
--- a/arch/arm/include/asm/arch-keystone/clock.h
+++ b/arch/arm/include/asm/arch-keystone/clock.h
@@ -38,12 +38,16 @@ struct pll_init_data {
};
extern const struct keystone_pll_regs keystone_pll_regs[];
+extern int dev_speeds[];
+extern int arm_speeds[];
void init_plls(int num_pll, struct pll_init_data *config);
void init_pll(const struct pll_init_data *data);
unsigned long clk_get_rate(unsigned int clk);
unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
int clk_set_rate(unsigned int clk, unsigned long hz);
+int get_max_dev_speed(void);
+int get_max_arm_speed(void);
#endif
#endif
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index ddeb06e7bb..d6726a1eca 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -138,6 +138,10 @@ typedef volatile unsigned int *dv_reg_p;
/* Flag from ks2_debug options to check if DSPs need to stay ON */
#define DBG_LEAVE_DSPS_ON 0x1
+/* Device speed */
+#define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
+#define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
+
/* Queue manager */
#define KS2_QM_MANAGER_BASE 0x02a02000
#define KS2_QM_DESC_SETUP_BASE 0x02a03000
diff --git a/arch/arm/include/asm/arch-omap5/mem.h b/arch/arm/include/asm/arch-omap5/mem.h
index d2e708bba5..3e5d655de9 100644
--- a/arch/arm/include/asm/arch-omap5/mem.h
+++ b/arch/arm/include/asm/arch-omap5/mem.h
@@ -46,13 +46,13 @@
#define M_NAND_GPMC_CONFIG6 0x16000f80
#define M_NAND_GPMC_CONFIG7 0x00000008
-#define STNOR_GPMC_CONFIG1 0x00001200
-#define STNOR_GPMC_CONFIG2 0x00101000
-#define STNOR_GPMC_CONFIG3 0x00030301
-#define STNOR_GPMC_CONFIG4 0x10041004
-#define STNOR_GPMC_CONFIG5 0x000C1010
+#define STNOR_GPMC_CONFIG1 0x00001000
+#define STNOR_GPMC_CONFIG2 0x001f1f00
+#define STNOR_GPMC_CONFIG3 0x001f1f01
+#define STNOR_GPMC_CONFIG4 0x1f011f01
+#define STNOR_GPMC_CONFIG5 0x001d1f1f
#define STNOR_GPMC_CONFIG6 0x08070280
-#define STNOR_GPMC_CONFIG7 0x00000F48
+#define STNOR_GPMC_CONFIG7 0x00000048
/* max number of GPMC Chip Selects */
#define GPMC_MAX_CS 8
generated by cgit (git 2.34.1) at 2024-12-25 14:29:01 +0000