diff options
Diffstat (limited to 'arch/arm/cpu/at91-common')
| -rw-r--r-- | arch/arm/cpu/at91-common/Makefile | 17 | ||||
| -rw-r--r-- | arch/arm/cpu/at91-common/mpddrc.c | 133 | ||||
| -rw-r--r-- | arch/arm/cpu/at91-common/phy.c | 57 | ||||
| -rw-r--r-- | arch/arm/cpu/at91-common/sdram.c | 77 | ||||
| -rw-r--r-- | arch/arm/cpu/at91-common/spl.c | 46 | ||||
| -rw-r--r-- | arch/arm/cpu/at91-common/spl_at91.c | 124 | ||||
| -rw-r--r-- | arch/arm/cpu/at91-common/spl_atmel.c | 80 | ||||
| -rw-r--r-- | arch/arm/cpu/at91-common/u-boot-spl.lds | 55 |
8 files changed, 0 insertions, 589 deletions
diff --git a/arch/arm/cpu/at91-common/Makefile b/arch/arm/cpu/at91-common/Makefile deleted file mode 100644 index 89e15775fb..0000000000 --- a/arch/arm/cpu/at91-common/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# -# (C) Copyright 2000-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2013 Atmel Corporation -# Bo Shen <voice.shen@atmel.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o -ifneq ($(CONFIG_SPL_BUILD),) -obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o -obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o -obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o -obj-y += spl.o -endif diff --git a/arch/arm/cpu/at91-common/mpddrc.c b/arch/arm/cpu/at91-common/mpddrc.c deleted file mode 100644 index 44798e612c..0000000000 --- a/arch/arm/cpu/at91-common/mpddrc.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (C) 2013 Atmel Corporation - * Bo Shen <voice.shen@atmel.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/atmel_mpddrc.h> - -static inline void atmel_mpddr_op(int mode, u32 ram_address) -{ - struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; - - writel(mode, &mpddr->mr); - writel(0, ram_address); -} - -static int ddr2_decodtype_is_seq(u32 cr) -{ -#if defined(CONFIG_SAMA5D3) - if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED) - return 0; -#endif - return 1; -} - -int ddr2_init(const unsigned int ram_address, - const struct atmel_mpddr *mpddr_value) -{ - struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; - u32 ba_off, cr; - - /* Compute bank offset according to NC in configuration register */ - ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9; - if (ddr2_decodtype_is_seq(mpddr_value->cr)) - ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11; - - ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2; - - /* Program the memory device type into the memory device register */ - writel(mpddr_value->md, &mpddr->md); - - /* Program the configuration register */ - writel(mpddr_value->cr, &mpddr->cr); - - /* Program the timing register */ - writel(mpddr_value->tpr0, &mpddr->tpr0); - writel(mpddr_value->tpr1, &mpddr->tpr1); - writel(mpddr_value->tpr2, &mpddr->tpr2); - - /* Issue a NOP command */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); - - /* A 200 us is provided to precede any signal toggle */ - udelay(200); - - /* Issue a NOP command */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); - - /* Issue an all banks precharge command */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address); - - /* Issue an extended mode register set(EMRS2) to choose operation */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, - ram_address + (0x2 << ba_off)); - - /* Issue an extended mode register set(EMRS3) to set EMSR to 0 */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, - ram_address + (0x3 << ba_off)); - - /* - * Issue an extended mode register set(EMRS1) to enable DLL and - * program D.I.C (output driver impedance control) - */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, - ram_address + (0x1 << ba_off)); - - /* Enable DLL reset */ - cr = readl(&mpddr->cr); - writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr); - - /* A mode register set(MRS) cycle is issued to reset DLL */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address); - - /* Issue an all banks precharge command */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address); - - /* Two auto-refresh (CBR) cycles are provided */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address); - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address); - - /* Disable DLL reset */ - cr = readl(&mpddr->cr); - writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr); - - /* A mode register set (MRS) cycle is issued to disable DLL reset */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address); - - /* Set OCD calibration in default state */ - cr = readl(&mpddr->cr); - writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr); - - /* - * An extended mode register set (EMRS1) cycle is issued - * to OCD default value - */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, - ram_address + (0x1 << ba_off)); - - /* OCD calibration mode exit */ - cr = readl(&mpddr->cr); - writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr); - - /* - * An extended mode register set (EMRS1) cycle is issued - * to enable OCD exit - */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, - ram_address + (0x1 << ba_off)); - - /* A nornal mode command is provided */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address); - - /* Perform a write access to any DDR2-SDRAM address */ - writel(0, ram_address); - - /* Write the refresh rate */ - writel(mpddr_value->rtr, &mpddr->rtr); - - return 0; -} diff --git a/arch/arm/cpu/at91-common/phy.c b/arch/arm/cpu/at91-common/phy.c deleted file mode 100644 index 2cba7169e4..0000000000 --- a/arch/arm/cpu/at91-common/phy.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop <stelian@popies.net> - * Lead Tech Design <www.leadtechdesign.com> - * - * (C) Copyright 2012 - * Markus Hubig <mhubig@imko.de> - * IMKO GmbH <www.imko.de> - * - * Copyright (C) 2013 DENX Software Engineering, hs@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <linux/sizes.h> -#include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_rstc.h> -#include <watchdog.h> - -void at91_phy_reset(void) -{ - unsigned long erstl; - unsigned long start = get_timer(0); - unsigned long const timeout = 1000; /* 1000ms */ - at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC; - - erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - - /* - * Need to reset PHY -> 500ms reset - * Reset PHY by pulling the NRST line for 500ms to low. To do so - * disable user reset for low level on NRST pin and poll the NRST - * level in reset status register. - */ - writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | - AT91_RSTC_MR_URSTEN, &rstc->mr); - - writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); - - /* Wait for end of hardware reset */ - while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) { - /* avoid shutdown by watchdog */ - WATCHDOG_RESET(); - mdelay(10); - - /* timeout for not getting stuck in an endless loop */ - if (get_timer(start) >= timeout) { - puts("*** ERROR: Timeout waiting for PHY reset!\n"); - break; - } - }; - - /* Restore NRST value */ - writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); -} diff --git a/arch/arm/cpu/at91-common/sdram.c b/arch/arm/cpu/at91-common/sdram.c deleted file mode 100644 index 5758b066e4..0000000000 --- a/arch/arm/cpu/at91-common/sdram.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2014 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * (C) Copyright 2007-2008 - * Stelian Pop <stelian@popies.net> - * Lead Tech Design <www.leadtechdesign.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> -#include <asm/arch/at91sam9_sdramc.h> -#include <asm/arch/gpio.h> - -int sdramc_initialize(unsigned int sdram_address, const struct sdramc_reg *p) -{ - struct sdramc_reg *reg = (struct sdramc_reg *)ATMEL_BASE_SDRAMC; - unsigned int i; - - /* SDRAM feature must be in the configuration register */ - writel(p->cr, ®->cr); - - /* The SDRAM memory type must be set in the Memory Device Register */ - writel(p->mdr, ®->mdr); - - /* - * The minimum pause of 200 us is provided to precede any single - * toggle - */ - for (i = 0; i < 1000; i++) - ; - - /* A NOP command is issued to the SDRAM devices */ - writel(AT91_SDRAMC_MODE_NOP, ®->mr); - writel(0x00000000, sdram_address); - - /* An All Banks Precharge command is issued to the SDRAM devices */ - writel(AT91_SDRAMC_MODE_PRECHARGE, ®->mr); - writel(0x00000000, sdram_address); - - for (i = 0; i < 10000; i++) - ; - - /* Eight auto-refresh cycles are provided */ - for (i = 0; i < 8; i++) { - writel(AT91_SDRAMC_MODE_REFRESH, ®->mr); - writel(0x00000001 + i, sdram_address + 4 + 4 * i); - } - - /* - * A Mode Register set (MRS) cyscle is issued to program the - * SDRAM parameters(TCSR, PASR, DS) - */ - writel(AT91_SDRAMC_MODE_LMR, ®->mr); - writel(0xcafedede, sdram_address + 0x24); - - /* - * The application must go into Normal Mode, setting Mode - * to 0 in the Mode Register and perform a write access at - * any location in the SDRAM. - */ - writel(AT91_SDRAMC_MODE_NORMAL, ®->mr); - writel(0x00000000, sdram_address); /* Perform Normal mode */ - - /* - * Write the refresh rate into the count field in the SDRAMC - * Refresh Timer Rgister. - */ - writel(p->tr, ®->tr); - - return 0; -} diff --git a/arch/arm/cpu/at91-common/spl.c b/arch/arm/cpu/at91-common/spl.c deleted file mode 100644 index 6473320097..0000000000 --- a/arch/arm/cpu/at91-common/spl.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (C) 2013 Atmel Corporation - * Bo Shen <voice.shen@atmel.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/at91_wdt.h> -#include <asm/arch/clk.h> -#include <spl.h> - -void at91_disable_wdt(void) -{ - struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT; - - writel(AT91_WDT_MR_WDDIS, &wdt->mr); -} - -u32 spl_boot_device(void) -{ -#ifdef CONFIG_SYS_USE_MMC - return BOOT_DEVICE_MMC1; -#elif CONFIG_SYS_USE_NANDFLASH - return BOOT_DEVICE_NAND; -#elif CONFIG_SYS_USE_SERIALFLASH - return BOOT_DEVICE_SPI; -#endif - return BOOT_DEVICE_NONE; -} - -u32 spl_boot_mode(void) -{ - switch (spl_boot_device()) { -#ifdef CONFIG_SYS_USE_MMC - case BOOT_DEVICE_MMC1: - return MMCSD_MODE_FS; - break; -#endif - case BOOT_DEVICE_NONE: - default: - hang(); - } -} diff --git a/arch/arm/cpu/at91-common/spl_at91.c b/arch/arm/cpu/at91-common/spl_at91.c deleted file mode 100644 index 89f588be45..0000000000 --- a/arch/arm/cpu/at91-common/spl_at91.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * (C) Copyright 2014 DENX Software Engineering - * Heiko Schocher <hs@denx.de> - * - * Based on: - * Copyright (C) 2013 Atmel Corporation - * Bo Shen <voice.shen@atmel.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/at91sam9_matrix.h> -#include <asm/arch/at91_pit.h> -#include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_rstc.h> -#include <asm/arch/at91_wdt.h> -#include <asm/arch/clk.h> -#include <spl.h> - -DECLARE_GLOBAL_DATA_PTR; - -static void enable_ext_reset(void) -{ - struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; - - writel(AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN, &rstc->mr); -} - -void lowlevel_clock_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) { - /* Enable Main Oscillator */ - writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor); - - /* Wait until Main Oscillator is stable */ - while (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) - ; - } - - /* After stabilization, switch to Main Oscillator */ - if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) { - unsigned long tmp; - - tmp = readl(&pmc->mckr); - tmp &= ~AT91_PMC_CSS; - tmp |= AT91_PMC_CSS_MAIN; - writel(tmp, &pmc->mckr); - while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) - ; - - tmp &= ~AT91_PMC_PRES; - tmp |= AT91_PMC_PRES_1; - writel(tmp, &pmc->mckr); - while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) - ; - } - - return; -} - -void __weak matrix_init(void) -{ -} - -void __weak at91_spl_board_init(void) -{ -} - -void spl_board_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - lowlevel_clock_init(); - at91_disable_wdt(); - - /* - * At this stage the main oscillator is supposed to be enabled - * PCK = MCK = MOSC - */ - writel(0x00, &pmc->pllicpr); - - /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ - at91_plla_init(CONFIG_SYS_AT91_PLLA); - - /* PCK = PLLA = 2 * MCK */ - at91_mck_init(CONFIG_SYS_MCKR); - - /* Switch MCK on PLLA output */ - at91_mck_init(CONFIG_SYS_MCKR_CSS); - -#if defined(CONFIG_SYS_AT91_PLLB) - /* Configure PLLB */ - at91_pllb_init(CONFIG_SYS_AT91_PLLB); -#endif - - /* Enable External Reset */ - enable_ext_reset(); - - /* Initialize matrix */ - matrix_init(); - - gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK; - /* - * init timer long enough for using in spl. - */ - timer_init(); - - /* enable clocks for all PIOs */ - at91_periph_clk_enable(ATMEL_ID_PIOA); - at91_periph_clk_enable(ATMEL_ID_PIOB); - at91_periph_clk_enable(ATMEL_ID_PIOC); - /* init console */ - at91_seriald_hw_init(); - preloader_console_init(); - - mem_init(); - - at91_spl_board_init(); -} diff --git a/arch/arm/cpu/at91-common/spl_atmel.c b/arch/arm/cpu/at91-common/spl_atmel.c deleted file mode 100644 index 7297530e7d..0000000000 --- a/arch/arm/cpu/at91-common/spl_atmel.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (C) 2013 Atmel Corporation - * Bo Shen <voice.shen@atmel.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/at91_pit.h> -#include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_rstc.h> -#include <asm/arch/at91_wdt.h> -#include <asm/arch/clk.h> -#include <spl.h> - -DECLARE_GLOBAL_DATA_PTR; - -static void switch_to_main_crystal_osc(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - u32 tmp; - - tmp = readl(&pmc->mor); - tmp &= ~AT91_PMC_MOR_OSCOUNT(0xff); - tmp &= ~AT91_PMC_MOR_KEY(0xff); - tmp |= AT91_PMC_MOR_MOSCEN; - tmp |= AT91_PMC_MOR_OSCOUNT(8); - tmp |= AT91_PMC_MOR_KEY(0x37); - writel(tmp, &pmc->mor); - while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCS)) - ; - - tmp = readl(&pmc->mor); - tmp &= ~AT91_PMC_MOR_OSCBYPASS; - tmp &= ~AT91_PMC_MOR_KEY(0xff); - tmp |= AT91_PMC_MOR_KEY(0x37); - writel(tmp, &pmc->mor); - - tmp = readl(&pmc->mor); - tmp |= AT91_PMC_MOR_MOSCSEL; - tmp &= ~AT91_PMC_MOR_KEY(0xff); - tmp |= AT91_PMC_MOR_KEY(0x37); - writel(tmp, &pmc->mor); - - while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCSELS)) - ; - - /* Wait until MAINRDY field is set to make sure main clock is stable */ - while (!(readl(&pmc->mcfr) & AT91_PMC_MAINRDY)) - ; - - tmp = readl(&pmc->mor); - tmp &= ~AT91_PMC_MOR_MOSCRCEN; - tmp &= ~AT91_PMC_MOR_KEY(0xff); - tmp |= AT91_PMC_MOR_KEY(0x37); - writel(tmp, &pmc->mor); -} - -void s_init(void) -{ - switch_to_main_crystal_osc(); - - /* disable watchdog */ - at91_disable_wdt(); - - /* PMC configuration */ - at91_pmc_init(); - - at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); - - timer_init(); - - board_early_init_f(); - - preloader_console_init(); - - mem_init(); -} diff --git a/arch/arm/cpu/at91-common/u-boot-spl.lds b/arch/arm/cpu/at91-common/u-boot-spl.lds deleted file mode 100644 index eccca43a42..0000000000 --- a/arch/arm/cpu/at91-common/u-boot-spl.lds +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Aneesh V <aneesh@ti.com> - * - * (C) 2013 Atmel Corporation - * Bo Shen <voice.shen@atmel.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \ - LENGTH = CONFIG_SPL_MAX_SIZE } -MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ - LENGTH = CONFIG_SPL_BSS_MAX_SIZE } - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - .text : - { - __start = .; - *(.vectors) - arch/arm/cpu/armv7/start.o (.text*) - *(.text*) - } >.sram - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram - - . = ALIGN(4); - .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram - - . = ALIGN(4); - __image_copy_end = .; - - .end : - { - *(.__end) - } >.sram - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end = .; - } >.sdram -} |