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-rw-r--r--arch/arm/include/asm/arch-rockchip/boot0.h38
-rw-r--r--arch/arm/include/asm/arch-rockchip/boot_mode.h6
-rw-r--r--arch/arm/include/asm/arch-rockchip/bootrom.h30
-rw-r--r--arch/arm/include/asm/arch-rockchip/clock.h5
4 files changed, 64 insertions, 15 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h
index 72d264bcbe..af3a733e98 100644
--- a/arch/arm/include/asm/arch-rockchip/boot0.h
+++ b/arch/arm/include/asm/arch-rockchip/boot0.h
@@ -1,4 +1,3 @@
-
/*
* Copyright 2017 Theobroma Systems Design und Consulting GmbH
*
@@ -7,26 +6,49 @@
/*
* Execution starts on the instruction following this 4-byte header
- * (containing the magic 'RK33').
+ * (containing the magic 'RK30', 'RK31', 'RK32' or 'RK33'). This
+ * magic constant will be written into the final image by the rkimage
+ * tool, but we need to reserve space for it here.
*
* To make life easier for everyone, we build the SPL binary with
* space for this 4-byte header already included in the binary.
*/
-
#ifdef CONFIG_SPL_BUILD
/*
* We need to add 4 bytes of space for the 'RK33' at the
* beginning of the executable. However, as we want to keep
* this generic and make it applicable to builds that are like
* the RK3368 (TPL needs this, SPL doesn't) or the RK3399 (no
- * TPL, but extra space needed in the SPL), we simply repeat
- * the 'b reset' with the expectation that the first one will
- * be overwritten, if this is the first stage contained in the
- * final image created with mkimage)...
+ * TPL, but extra space needed in the SPL), we simply insert
+ * a branch-to-next-instruction-word with the expectation that
+ * the first one may be overwritten, if this is the first stage
+ * contained in the final image created with mkimage)...
*/
- b reset /* may be overwritten --- should be 'nop' or a 'b reset' */
+ b 1f /* if overwritten, entry-address is at the next word */
+1:
+#endif
+#if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM)
+ adr r3, entry_counter
+ ldr r0, [r3]
+ cmp r0, #1 /* check if entry_counter == 1 */
+ beq reset /* regular bootup */
+ add r0, #1
+ str r0, [r3] /* increment the entry_counter in memory */
+ mov r0, #0 /* return 0 to the BROM to signal 'OK' */
+ bx lr /* return control to the BROM */
+entry_counter:
+ .word 0
#endif
b reset
+#if !defined(CONFIG_ARM64)
+ /*
+ * For armv7, the addr '_start' will used as vector start address
+ * and write to VBAR register, which needs to aligned to 0x20.
+ */
+ .align(5), 0x0
+_start:
+ ARM_VECTORS
+#endif
#if defined(CONFIG_ROCKCHIP_RK3399) && defined(CONFIG_SPL_BUILD)
.space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */
diff --git a/arch/arm/include/asm/arch-rockchip/boot_mode.h b/arch/arm/include/asm/arch-rockchip/boot_mode.h
index bd65f60bf2..6b2a610cf4 100644
--- a/arch/arm/include/asm/arch-rockchip/boot_mode.h
+++ b/arch/arm/include/asm/arch-rockchip/boot_mode.h
@@ -15,5 +15,11 @@
#define BOOT_CHARGING (REBOOT_FLAG + 11)
/* enter usb mass storage mode */
#define BOOT_UMS (REBOOT_FLAG + 12)
+/* enter bootrom download mode */
+#define BOOT_BROM_DOWNLOAD 0xEF08A53C
+
+#ifndef __ASSEMBLY__
+int setup_boot_mode(void);
+#endif
#endif
diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h
index 169cc5e50b..103b799593 100644
--- a/arch/arm/include/asm/arch-rockchip/bootrom.h
+++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
@@ -1,5 +1,6 @@
/*
* (C) Copyright 2017 Heiko Stuebner <heiko@sntech.de>
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*
* SPDX-License-Identifier: GPL-2.0
*/
@@ -14,15 +15,30 @@
extern u32 SAVE_SP_ADDR;
/**
- * Hand control back to the bootrom to load another
- * boot stage.
+ * back_to_bootrom() - return to bootrom (for TPL/SPL), passing a
+ * result code
+ *
+ * Transfer control back to the Rockchip BROM, restoring necessary
+ * register context and passing a command/result code to the BROM
+ * to instruct its next actions (e.g. continue boot sequence, enter
+ * download mode, ...).
+ *
+ * This function does not return.
+ *
+ * @brom_cmd: indicates how the bootrom should continue the boot
+ * sequence (e.g. load the next stage)
*/
-void back_to_bootrom(void);
+enum rockchip_bootrom_cmd {
+ /*
+ * These can not start at 0, as 0 has a special meaning
+ * for setjmp().
+ */
-/**
- * Assembler component for the above (do not call this directly)
- */
-void _back_to_bootrom_s(void);
+ BROM_BOOT_NEXTSTAGE = 1, /* continue boot-sequence */
+ BROM_BOOT_ENTER_DNL, /* have BROM enter download-mode */
+};
+
+void back_to_bootrom(enum rockchip_bootrom_cmd brom_cmd);
/**
* Boot-device identifiers as used by the BROM
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index 641df58ac2..736b2603fd 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -39,6 +39,11 @@ static inline int rk_pll_id(enum rk_clk_id clk_id)
return clk_id - 1;
}
+struct sysreset_reg {
+ unsigned int glb_srst_fst_value;
+ unsigned int glb_srst_snd_value;
+};
+
/**
* clk_get_divisor() - Calculate the required clock divisior
*