diff options
Diffstat (limited to 'arch/mips/mach-mscc/reset.c')
| -rw-r--r-- | arch/mips/mach-mscc/reset.c | 27 |
1 files changed, 25 insertions, 2 deletions
diff --git a/arch/mips/mach-mscc/reset.c b/arch/mips/mach-mscc/reset.c index e0e610ade6..a555fc9d9a 100644 --- a/arch/mips/mach-mscc/reset.c +++ b/arch/mips/mach-mscc/reset.c @@ -12,7 +12,7 @@ void _machine_restart(void) { -#if defined(CONFIG_SOC_JR2) +#if defined(CONFIG_SOC_JR2) || defined(CONFIG_SOC_SERVALT) register u32 reg = readl(BASE_CFG + ICPU_GENERAL_CTRL); /* Set owner */ reg &= ~ICPU_GENERAL_CTRL_IF_SI_OWNER_M; @@ -27,7 +27,30 @@ void _machine_restart(void) ICPU_RESET_CORE_RST_CPU_ONLY | ICPU_RESET_CORE_RST_FORCE, BASE_CFG + ICPU_RESET); -#else +#elif defined(CONFIG_SOC_SERVAL) + register unsigned long i; + + /* Prevent VCore-III from being reset with a global reset */ + writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET); + + /* Do global reset */ + writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST); + + for (i = 0; i < 1000; i++) + ; + + /* Power down DDR for clean DDR re-training */ + writel(readl(BASE_CFG + ICPU_MEMCTRL_CTRL) | + ICPU_MEMCTRL_CTRL_PWR_DOWN, + BASE_CFG + ICPU_MEMCTRL_CTRL); + + while (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) & + ICPU_MEMCTRL_STAT_PWR_DOWN_ACK)) + ; + + /* Reset VCore-III, only. */ + writel(ICPU_RESET_CORE_RST_FORCE, BASE_CFG + ICPU_RESET); +#else /* Luton || Ocelot */ register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST; (void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST); |